JPH0531310B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a gate array master slice integrated circuit device.

In general, large-scale integrated circuits (hereinafter referred to as logic LSIs) such as complex integrated logic circuits are produced in small quantities in a wide variety of products in order to be manufactured according to customer requirements.
A master slicing method has been proposed as a method for manufacturing such high-mix, low-volume logic LSIs quickly and at low cost.

In the master slicing method, a large number of basic cells are manufactured in advance in a regular manner, and a wiring pattern mask for each unit cell is manufactured according to customer requirements or developed product types, and the wiring within these basic cells and between the basic cells are divided. Only the wiring of 1 is manufactured separately later. Therefore, the manufacturing or development period is shortened, and since the basic cell structure is common to each logic LSI, the manufacturing or development cost is also reduced.
Note that the basic cell structure is determined by the impurity diffusion region in the semiconductor substrate and the minimum necessary wiring in the basic cell, so it is also called the bulk structure.

The present invention improves the bulk structure of a gate array master slice logic LSI in which the basic cells described above are arranged in an array.

2. Prior Art FIG. 2 shows a basic cell used in a complementary MIS (CMIS) gate array and an example equivalent circuit, FIG. 3 shows a plan view thereof, and FIGS.
A cross-sectional view taken along the - line and a cross-sectional view taken along the - line in the figure are respectively shown. As shown in Figure 2, this basic cell consists of a pair of P-channel transistors Q _P1 and Q _P2 that share a source (or drain), and a pair of N-channel transistors Q o1 that share a source (or _drain ). , Q _o2 , and these pairs of transistors of different conductivity types Q _P1 , Q _o1 , and Q _P2 ,
Q _o2 gates are commonly connected. The manufacturing method will be explained with reference to FIGS. 3 to 5. The above basic cell has P ^- as N channel transistors Q _o1 and Q _o2 forming regions on an N ^- silicon substrate 1.
A well 2 is formed, and then a field oxide film 3 is formed as an isolation layer. Next, a gate oxide film 4 for each transistor is formed, and a P ⁺ impurity diffusion layer 5 for P channel transistors Q _P1 and Q _P2 is formed in the N ^- silicon substrate 1.
On the other hand, an N ⁺ impurity diffusion layer 6 for an N channel transistor is formed in the P ^- well, and finally, a polysilicon layer is formed to commonly connect the gates of each transistor Q _P1 and Q _o1 and the gate of each transistor Q _P2 and Q _o2 . The layer 7 is formed to complete the preliminary process for forming the bulk structure. In other words, the subsequent steps are performed using masks for unit cells according to customer requirements or developed product types.

Conventional basic cells are arranged in an array in the center of a chip, as shown in FIG. In other words, each array BC1 consists of one row of basic cells, and a wiring channel region CH is provided between them. In FIG. 6, I/O is an input/output circuit for connection with the outside, and P is a pad.

FIG. 7 shows an example in which unit cells are configured in the above-mentioned single-row basic cell array BC1. The wiring LA shown by the solid line parallel to the basic cell array BC1 is formed of the first layer of aluminum, and
The wiring LB shown by the dotted line perpendicular to BC is formed from the second aluminum layer. The wiring LA and LB provide wiring between the unit cells and between the unit cells.

Problems to be Solved by the Invention However, the above-mentioned one-row type basic cell array
When a unit cell is configured in BC1, the vertical length of one unit cell becomes large, and therefore the above-mentioned wiring
LA and LB also become longer, which affects characteristics such as signal transmission speed, and as a result of longer wiring LA and LB, the wiring channel area CH between basic cell arrays must be enlarged, which is disadvantageous in terms of integration. There was a problem.

Means for Solving the Problems In view of the problems of the conventional type described above, an object of the present invention is to configure a basic cell array with two rows of basic cells, thereby reducing the vertical length of the same unit cell. Therefore, the above wiring
The goal is to improve characteristics such as signal transmission speed by shortening LA and LB, and also to reduce the wiring channel area between basic L arrays to improve the degree of integration.

Embodiment FIG. 1A is a plan view showing an embodiment of a basic cell array according to the present invention. In Figure 1A,
A two-column basic cell array BC2 is shown in which the CMIS basic cells shown in FIGS. 3 to 5 are arranged in two columns. In other words, although the wiring channel region CH is provided outside the two-row basic cell array BC2,
There is no wiring channel region between each of the single-row basic cell arrays BC1 and BC1' in the two-row basic cell array BC2.
1, BC1' are arranged symmetrically. Also,
FIG. 1B shows the entire gate array master slicing device including the two-row type basic cells of FIG. 1A.

FIG. 8 is a plan view showing an example of wiring for unit cells in a two-row basic cell array according to the present invention, and FIG. 9 is a plan view showing wiring for the same unit cells in a conventional single-row basic cell array. FIG. As can be seen by comparing Figures 8 and 9,
In Figure 8, the number of basic cell stages used is 4.
In contrast, in FIG. 9, the number of elementary cell stages used is doubled to 8, and therefore the first layer of aluminum inside the elementary cell array (shown as a dotted line and its contacts as single circles) The wiring in FIG. 8 is generally shorter than that in FIG. 9. Further, the intervals between the wirings LB ₁ to _{LB 5} of the second layer aluminum (indicated by dotted lines, and the contacts thereof are indicated by double circles) for connection with other unit cells are also short. As a result, the number of wires passing through the wiring channel region CH for connection with other unit cells can be reduced, and the length of the wires can also be shortened.

In the above embodiment, two P channel transistors and the same number of N channel transistors are used as basic cells.
In this example, we used a structure composed of P-channel transistors and the gates of each pair of P-channel/N-channel transistors connected in common, but a structure composed of three or more P-channel transistors and the same number of N-channel transistors, or
The gates of N-channel transistors may be commonly connected.

Effects of the Invention As explained above, according to the present invention, since the basic cell array is constituted by two rows of basic cells, when a unit cell is constituted, its vertical length can be reduced.
Therefore, the signal characteristics can be improved because the wiring length can be shortened, and the wiring channel area can also be reduced by reducing the number of wiring lines and the wiring length, which is useful for improving the degree of integration.

[Brief explanation of the drawing]

FIG. 1A is a plan view showing an example of a basic cell array of a gate array master slice integrated circuit device according to the present invention, FIG. 1B is an overall view thereof, and FIG. 2 is a plan view of a basic cell array used in a complementary MIS gate array. An equivalent circuit showing an example, Figure 3 is a plan view of Figure 2, Figure 4 is a plan view of Figure 2.
5 and 5 are a sectional view and a sectional view, respectively, of FIG. 3, FIG. 6 is a plan view of a conventional gate array master slice integrated circuit device, and FIG. FIG. 8 is a diagram showing wiring for unit cells in a cell array.
FIG. 9 is a diagram showing an example of wiring for unit cells in a column-type basic cell array. FIG. 9 is a diagram showing a conventional one-row basic cell array with the same wiring as the unit cell shown in FIG. BC1: 1-row basic cell array, BC2: 2-row basic cell array, CH: wiring channel area.

Claims (1)

[Scope of Claims] 1. A plurality of two-row type basic cell rows BC2 are provided, each of the two-row type basic cell rows having a first type in which at least one pair of P-channel MIS transistors and an N-channel MIS transistor are juxtaposed. Basic cell BC1
and a plurality of second basic cells BC1' whose transistor arrangement is a mirror image of the first basic cell, and the column of the first basic cell in the two-row type basic cell column and the The first basic cell column and the second basic cell column are juxtaposed closely such that the distance between the second basic cell column and the second basic cell column is narrower than the width of the first basic cell. , and a signal line is wired between the first basic cell column and the second basic cell column in a direction parallel to the column, and the signal line connects the first basic cell to the second basic cell column. The two basic cells are connected to each other, and the plurality of two-row basic cell rows are arranged such that the spacing between the plurality of two-row basic cell rows is approximately the same as the width of the first basic cell. gates arranged in parallel and having a signal line arranged in a direction parallel to the columns between the plurality of two-row type basic cell columns, and the plurality of two-row type basic cell columns are interconnected by the signal line; Array master slice integrated circuit.