JPH0531335B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a timing recovery circuit, and more specifically, to a signal timing recovery circuit in an asynchronous signal transmission system.

As a timing recovery circuit for the original signal in conventional asynchronous transmission systems, a phase-locked loop (PLL:
PhaseLockedLoop). However, the number of staff pulses was about 1%, so even a PLL with a narrow synchronization range was sufficient. On the other hand, asynchronous transmission is extremely versatile in that it can transmit signals at arbitrary transmission speeds of 8 MHz or less using a 16 MHz transmission clock, for example. FIG. 1 is a time chart of encoding and decoding in an asynchronous transmission system. FIG. 1a shows an original signal, b shows a signal obtained by encoding the original signal into a code suitable for transmission, and c and d show decoded signals. c indicates the position of the decoded signal, and d indicates the value at that time. This shows the case where the ratio of the original signal clock to the transmission clock is T/T ₀ =3.3.

Although signals c and d correctly decode the original signal a, the positions of the signals are irregularly spaced, and it is not practical to use these signals directly as decoded signals of the original signal. Therefore, it is necessary to reproduce the original signal clock from these decoded waveforms c and d and output it in the form of the original signal a.

Waveform c has timing information, but the signal interval changes from T ₀ to 5T ₀ , and the phase relationship with the original signal is uncertain, so it is not used conventionally.
Timing cannot be reproduced with a PLL circuit.

The present invention provides a timing regeneration circuit that can regenerate timing even when the interval between input signals changes significantly and it is difficult to ensure synchronization with a normal PLL.

In order to achieve the above object, the present invention calculates the frequency difference between a signal proportional to the number of pulses of an asynchronous input signal and a signal proportional to the number of pulses of a voltage controlled oscillator, and uses the signal corresponding to the frequency difference as described above. It is configured to control the frequency of a voltage controlled oscillator. In other words, the present invention uses an input signal and a voltage controlled oscillator (VCO:
Instead of detecting the phase difference between the input signal and the VCO (Voltage Controlled Oscillator), it detects the frequency difference between the input signal and the VCO. Therefore, even when the jitter of the input signal is large as shown in c and d of FIG. 1 above, timing recovery is possible.

The present invention will be explained in detail below using examples.

FIG. 2 shows the configuration of an embodiment of the timing recovery circuit according to the present invention, in which signals at irregular intervals as shown in FIG. 1c are applied to the input terminal IN.
Block 1 is a circuit that generates a signal with a value proportional to the number of pulses of the input signal, and block 2 has the same configuration as block 1, and is a circuit that generates a signal with a value proportional to the number of output pulses of the VCO 6. be. The outputs of these circuits 1 and 2 are sent to comparator circuit 3.
is converted into a signal proportional to the difference in frequency between the two signals. The output of comparison circuit 3 is output from circuit 4.
The signal is converted into a predetermined waveform and applied to the VCO 6 via the feedback loop filter 5.

FIG. 3 is a more detailed circuit diagram of the above embodiment. Transmission clock is 8MHz, signal clock is
The case of 2.048MHz is shown. 11, 18 in the figure
is a four-stage binary counter. The input signal is applied to the input terminal 10 of the counter 11, frequency-divided by 4, and then sampled with a signal obtained by negating the output of the VCO 26 with a logical negation circuit 17. Although the pulse interval of the input signal varies greatly, since the frequency is divided by 4, no unsampled pulses are generated. The output of the VCO 26 is similarly divided into four.
The frequency-divided output is shaped into a pulse with a pulse width of about 40 ns by delay elements 13 and 19, logic NOT circuits 14 and 20, and NAND circuits 15 and 21. Here, since the input signal is sampled at the negative of the output of the VCO 26, it does not overlap with the pulse from the VCO.
These two pulse trains are input to a four-stage binary up-down counter 16, and the difference in the number of pulses is output. Outputs 16-a, b, c, d are each 2 ⁰ ,
Represents the 2 ¹ , 2 ² , and 2 ³ digits. Further, 16-e outputs a pulse when underflow occurs, and 16-f outputs a pulse when overflow occurs. 16-e and 16-f are applied to the set (S) and reset (R) terminals of the flip-flop 22, and the output Q is set to logic 1 or logic 0 depending on overflow or underflow. 23 and 24 surrounded by broken lines are simple digital-to-analog conversion circuits, which convert from 23 when an overflow occurs (that is, when the VCO frequency is high), and from 24 when there is an underflow (that is, when the VCO frequency is low). From input signal pulse number and VCO
It outputs an output proportional to the difference in the number of pulses from This output is fed back to the VCO 26 through an operational amplifier 25 equipped with a low-pass waveform (R ₃ , C ₁ ).

Further, the operation of the circuit shown in FIG. 3 will be explained using flowcharts shown in FIGS. 4, 5, and 6. 4 shows the operations of the counters 11, 18 and flip-flop 12 shown in FIG. 3, and FIGS. 5 and 6 show the operations of the up-down counter 16, flip-flop 22, and digital-to-analog conversion circuits 23, 27.

A pulse train arranged at irregular intervals as shown in FIG. 1c is input to the input terminal 10. (Figure 4, 10
−IN). This is divided into 4, and the VCO 26 output (Figure 4, 26-OUT) is negated (output 17).
Since it is sampled at flip-flop 1
The output of 2 is as shown in Fig. 4, 12-OUT. On the other hand, the output 26-OUT of VCO26 is also
The frequency is divided by 4 to obtain 18-OUT. Furthermore,
Delay elements 13, 19 and logical NOT circuits 14, 2
0, NAND circuits 15 and 21 in Figure 4 15-
A pulse train like OUT, 21-OUT is obtained.

These pulse trains are processed by up-down counter 16.
becomes the input. The up-down counter 16 has a function of comparing the numbers of both pulses. for example,
When the VCO frequency is high, overflow occurs and 16-f becomes high level. Therefore, the output of flip-flop 22 also becomes high level, 24 of the digital-to-analog conversion circuits do not output, and only 23 outputs an output corresponding to the output of up-down counter 16 (16-a to 16-d). By the way, when the VCO frequency is high, that is, when there are many pulses from the gate 21, the output of the up-down counter 16 becomes as shown in FIG. 5, 16-a to 16-d. Therefore, the output of the digital-to-analog conversion circuit 23 is as shown in FIG. 5, 23-OUP, which is averaged and amplified by the operational amplifier 25.
It is fed back to the VCO 26 and works to lower the frequency of the VCO 26. Conversely, if the frequency of the VCO 26 is low, the up-down counter 16
, many pulses from the gate 15 are input, and the up-down counter 16 underflows.
16-e becomes high level. Therefore, 23 of the digital-to-analog conversion circuits do not output an output, and only 24 outputs an output corresponding to the output (16-a to 16-d) of the up-down counter 16. The output of the up-down counter 16 in this case (16-a~
d) is shown in FIG. Contrary to FIG. 5, the numbers are counted in a decreasing direction. These outputs (16-a~
d) of the digital-to-analog conversion circuit 24
At the NOR gate, it becomes OUT in Figure 6, 24-OUT. This waveform is the same as 23-OUT in FIG.
Unlike -OUT, it works in the direction of increasing the frequency of VCO26.

The jitter of the timing signal of the timing recovery circuit according to the embodiment shown in FIG. 2 is about ±5%, and even though the position of the input signal pulse varies greatly as shown in FIG. 1, it is possible to use a PLL. It is possible to reproduce timing signals with little jerk.

As explained above, according to the present invention, timing recovery is possible even in an asynchronous transmission decoder with extremely large jitter. Also, since most of the circuits can be constructed with digital circuits, it has the advantage of being less susceptible to noise.

[Brief explanation of the drawing]

Fig. 1 is a time chart of encoding and decoding when an asynchronous signal is transmitted at a speed of 1/3.3 of the transmission line clock, Fig. 2 is a block diagram of an embodiment of the timing recovery circuit according to the present invention, and Fig. 3 is a FIGS. 4 to 6, which are circuit diagrams of one embodiment of the timing recovery circuit according to the present invention, are flowcharts for explaining the operation of the circuit shown in FIG. 3. 1, 2...A circuit that outputs an output proportional to the number of input signal pulses, 3...Comparison circuit, 5...Loop filter, 6...VCO.

Claims (1)

[Claims] 1. Means for outputting a number of pulses proportional to the number of output pulses of a voltage controlled oscillator in a timing recovery circuit for a transmission signal used in a decoder of a communication system that transmits a signal asynchronous to the clock frequency of a transmission line, the above-mentioned voltage controlled oscillator means for sampling an asynchronous input signal using a signal obtained by negating the output pulse of the voltage controlled oscillator by the logic negation circuit, and outputting a number of pulses proportional to the number of the asynchronous input signals; A timing regeneration circuit comprising means for detecting a difference in the number of pulses, means for outputting a signal corresponding to the difference in the number of pulses, and a filter circuit for feeding back this output to the voltage controlled oscillator. .