JPH05314043A - Data processing device - Google Patents

Abstract

(57) [Abstract] [Purpose] The central processing unit 1 stabilizes the reception cycle of data received from the central processing unit 1 side regardless of the time length of processing of data received from the terminal unit 4. .. [Structure] Clock pulse generator 13, 1/10 frequency divider 14, 1
The clock pulse generation circuit consisting of 5 etc. creates the clock pulse B, the leading edge of which causes the central processing unit 1 to start processing the received data, and the trailing edge causes the terminal correspondence unit 3 to transmit to the terminal unit 4. It is configured to start.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing device for performing communication with a terminal and processing communication data, such as a central control unit in a traffic control system.

[0002]

2. Description of the Related Art As shown in FIG. 7, a traffic control system comprises a central control unit 50 and a large number of terminals (signals, vehicle detectors, etc.) 54, 54 connected to the central control unit 50 via communication lines. .. The central control unit 50 is located between the central processing unit 51, which is the control center, the communication control unit 52 that controls data communication between the central processing unit 51 and the terminals 54, 54, ... The terminal support unit 53, 53 that performs communication control corresponding to each terminal
It consists of ... and.

FIG. 8 is a timing chart of conventional data communication in the central control unit 50. The central processing unit 51 processes the data received from the terminal, and then, based on the processing result, processes the data to be transmitted to the terminals 54, 54 ... And transfers the data to the communication control unit 52. .. The communication control unit 52 separates the data for each of the terminals 54, 54 ... As the transmission target, and transfers the data to the terminal corresponding units 53, 53. Terminal support part 5
3,53 ... transfers the transferred data to the terminal 5 via the communication line.
Send to 4,54 .... Such a series of control is repeatedly executed by the timer in the central processing unit 51 so that the received data processing is started at 1 second intervals.

[0004]

On the other hand, terminals 54, 54 ...
In particular, in the traffic signal, the step signal (a signal that advances the lighting color of the traffic signal by one step) is received for the purpose of preventing improper operation due to an illegal command from the side of the central control unit 50, or as a countermeasure against noise contamination. When the interval is less than 0.95 seconds, it is considered to be abnormal and the terminals 54, 54 ... side make their own steps for safety. The times t ₁ and t ₂ for processing the received data performed by the central processing unit 51 described above vary depending on the amount of received data. On the other hand, the required time in the communication control unit 52, the terminal corresponding units 53, 53 ... Does not change much depending on the transmission data length, and the data length itself does not change so much. Therefore, the processing times t ₁ and t ₂ that follow _{each other} are 0.1
If it is 0.02 seconds, the data reception interval t ₀ at the terminals 54, 54 ... Is 0.92 seconds, and the terminals 54, 54 ... Stop the control based on the received data. For this reason, the fact that the online control of the traffic light cannot be performed is caused as it is.

In order to solve this, it may be considered that the period of the start time of the received data processing should be set longer than 1 second, and accordingly, the time length of the abnormality determination on the side of the terminals 54, 54 ... Also need to be longer than 0.95 seconds, it is not a solution. In addition, even if a relatively long time of 0.15 seconds can be spent for processing the received data from the viewpoint of the processing capability of the central processing unit 51, if the difference from the case where the time required for processing the received data in the subsequent cycle is short exceeds 0.05 seconds. Since the time on the terminal 54, 54 ... side is 0.95 seconds or less, in order to avoid it,
There is a problem in that the time spent processing received data cannot be filled to the full capacity. The present invention has been made to solve such a problem, and by adopting a configuration in which the transmission timing from the terminal corresponding unit to the terminal is regulated by the clock pulse, the data reception time interval in the terminal varies. In the case of applying to a traffic control system, it is possible to provide a data processing device that does not interfere with the online control of a traffic light and allows the received data processing capacity of the central processing unit to be used to the limit. To aim.

[0006]

A data processing apparatus according to the present invention processes a data received from a terminal and then processes the data to be transmitted to the terminal, and a central processing unit for processing the data to be transmitted to the terminal. In a data processing device including a terminal corresponding unit that transmits data to be transmitted to a corresponding terminal, a clock pulse generating circuit and data received from the terminal in synchronization with a leading edge of a clock pulse generated by the clock pulse generating circuit. It is characterized by comprising means for starting processing and means for executing data transmission to the terminal in synchronization with the trailing edge of the clock pulse.

[0007]

The central processing unit processes the reception data and then the transmission data in synchronization with the leading edge of the clock pulse. The transmission data is sent to the terminal corresponding section via the communication control section, and the terminal corresponding section transmits this data to the terminal in synchronization with the trailing edge of the clock pulse. Since the subsequent cycle is also performed in synchronization with the clock pulse, the time interval of the reception timing at the terminal matches the cycle of the clock pulse.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to the drawings showing the embodiments. FIG. 1 is a block diagram showing a data processing device of the present invention and a terminal device to which the data processing device is connected. This data processing device is used as a central control unit shown in FIG. 8 when used in a traffic control system, and like the conventional device, the central processing unit 1, the communication control unit 2, and the terminal corresponding units 3, 3 are used.
, And terminal units 4, 4, ... Are connected to the terminal corresponding units 3, 3 ,. The central processing unit 1 processes data received from the terminals 4, 4, ..., Creates data to be transmitted based on the data, and sends the data to the communication control unit 2. The microprocessor 11 is a control center. A data buffer 12 for temporarily storing transmission / reception data is connected to the data bus 5. A clock pulse generator 13 outputs a clock pulse A having a cycle of 10 msec. The clock pulse A is frequency-divided by the 1/10 frequency dividing circuits 14 and 15 sequentially, is input to the delay circuit 6, and is output as the clock pulse B according to the present invention. The clock pulse B generating circuit according to the gist of the present invention is a clock pulse generator 13, 1/10 frequency dividing circuits 14 and 15 and a delay circuit in this embodiment.
It consists of 16, but is not limited to this. The clock pulse generator 13 also supplies the basic clock of the microprocessor 11.

FIG. 2 is a timing chart showing the clock pulses A and B, and the cycle of the clock pulse B is 10 μse.
It is 1/100 of c, and the pulse width is 200 msec. This pulse width is set to a value that does not fall below the assumed maximum value of the time required for processing the received data and creating and transmitting the transmitted data in this data processing device. The delay circuit 16 gives a delay of several tens of microseconds, and the rising timing of the clock pulses A and B is 1/10 frequency dividing circuits 14 and 15.
The delay time is different from the delay time of the delay circuit 16 by. These clock pulses A and B are given as interrupt signals to the interrupt terminal of the microprocessor 11 via the interrupt controller 17. Due to the existence of the delay time, the rising edges of the interrupt signals do not overlap.

The clock pulse B is used as one input of the AND gate 23 of the communication control unit 2. In order to deal with the occurrence of a failure, the central processing unit 1 and the communication control unit 2 have the same configuration for two systems to form a duplex system (not shown).
The working signal is given from the host computer or manually to this working signal.
23 other inputs. The data bus 5 has a communication controller 2
The data buffer 22 is connected, and the reception data and the transmission data are also temporarily stored therein. The microprocessor 21 controls the transmission / reception of data in the communication control unit 2, and when looking at the transmission data, it identifies the terminals 4, 4 ... From the data transferred from the central processing unit 1 and supports the corresponding terminals. .. controls the transfer of the data to the parts 3, 3 ...

Further, the data bus 3 connected to the microprocessor 21 is connected to the data buffer 3 of the terminal corresponding parts 3, 3, ....
2,32… are connected. Transmitted / received data is also temporarily stored in the data buffer 32. The microprocessor 31 of each terminal corresponding unit 3 stores the data transmitted from the terminal 4 connected thereto in the data buffer 32, and the data transferred from the central processing unit 1 side and stored in the data buffer 32. Is read out and transmitted to the terminal 4. A fall detection circuit 33 is provided in each terminal corresponding unit 3. The falling edge detection circuit 33 inputs the output of the AND gate 23 and detects the falling edge of the clock pulse B.
It consists of a differentiating circuit. When the falling edge detection circuit 33 detects the falling edge, it outputs a predetermined pulse signal and supplies it to the interrupt terminal of the microprocessor 31.

FIG. 3 is a timing chart showing the operation of the apparatus of the present invention thus constructed, and each microprocessor 1 of the central processing unit 1, the communication control unit 2 and the terminal corresponding unit 3.
Flowchart showing the processing procedure of 1, 21 and 31 (Fig.
And 6). The microprocessor 11 uses the interrupt signal generated by the interrupt controller 17 based on the clock pulse A to perform processing other than the reception data processing and the transmission data processing described below. The interrupt controller 17 detects the leading edge of the clock pulse B, that is, the rising edge in this example, and issues an interrupt signal. The microprocessor 11 enters the received data processing (# 1, # 2) with this interrupt signal. This process is a process of reading the data transmitted from the terminals 4, 4 ... And stored in the data buffer 12 and performing a required calculation. When the reception data processing is completed (# 3), transmission data processing such as creating data to be transmitted is executed (# 4). When this is complete (#
5), transfer the transmission data to the communication control unit 2 (# 6). The transmission data is transmitted through the data bus 5, but after the completion (# 7), the microprocessor 21 of the communication control unit 2 is interrupted (# 8) through a signal line (not shown).

When there is an interrupt (# 11), the communication control unit 2 fetches data into the data buffer 22 and communicates with the terminal 4,
Transmission data processing (# 12) such as identification of 4 ... is performed, and when this is completed (# 13), transmission data is transferred to each terminal corresponding unit 3, 3 ... (# 14). Microprocessor of communication control unit 2
21 is a microprocessor 31, 31 of the terminal corresponding part 3, 3 ...
... are connected, and when the contents of the data buffers 32, 32 ... Are updated by performing transfer to each terminal corresponding unit 3, the update pointers provided in the microprocessors 31, 31 ,.
(# 15). When the transfer to all terminal support parts 3, 3 ... is completed (#
16) Return. Microprocessor of the terminal support unit 3
31 reads the update pointer (# 21) and when this is set
(# 22), transmission data processing such as conversion to serial data is performed (# 23). When this processing is completed (# 24) and a pulse signal is input from the detection circuit 33 (# 25), transmission to the terminal 4 is started (# 26).

The apparatus of the present invention repeats such processing in the cycle of the clock pulse B, that is, in the cycle of 1 second. The time required to process the received data of # 2 is different in each processing cycle,
The timing for starting transmission from the terminal corresponding parts 3, 3 ... To the terminals 4, 4 ... Is synchronized with the trailing edge of the clock pulse, that is, the falling timing. Becomes Therefore, in the traffic control system, the time interval of the step signal sent from the central control unit 1 to the terminal 4 does not change. Therefore, the time for abnormality determination will not be less than 0.95 seconds.

[0015]

As described above, according to the present invention, the data reception cycle at the terminal side is stable, and when applied to a traffic control system, the traffic signal is online regardless of fluctuations in the received data processing time of the central processing unit. Control can be performed reliably. Further, the processing time of the received data is set to the microprocessor of the central processing unit
Even when the capacity of 11 is full, the problem of the online control stop does not occur, so that the present invention has excellent effects such as efficient operation of resources.

[Brief description of drawings]

FIG. 1 is a block diagram of a data processing device of the present invention.

FIG. 2 is a timing chart of clock pulses.

FIG. 3 is a timing chart for explaining the operation of the entire data processing device of the present invention.

FIG. 4 is a timing chart showing a processing procedure of a central processing unit.

FIG. 5 is a timing chart showing a processing procedure of a communication control unit.

FIG. 6 is a timing chart showing a processing procedure of a terminal corresponding unit.

FIG. 7 is a schematic block diagram of a traffic control system.

FIG. 8 is a timing chart for explaining the operation of the conventional traffic control system.

[Explanation of symbols]

 1 Central processing unit 2 Communication control unit 3 Terminal corresponding unit 4 Terminal device 11,21,31 Microprocessor 13 Clock pulse generator 14,15 1/10 frequency divider circuit 16 Delay circuit 23 AND gate 33 Fall detection circuit

Front page continuation (72) Inventor Kuniichi Sawai 1-3-3 Shimaya, Konohana Ward, Osaka Industrial Co., Ltd. (72) Inventor Tadaaki Kamiyama 1006 Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. Seiji Fujimoto, Omron Co., Ltd. 10, Hanazono Dodo-cho, Ukyo-ku, Kyoto

Claims (1)

[Claims] 1. A central processing unit for processing data to be transmitted to a terminal after processing data received from the terminal, and a terminal corresponding unit for transmitting data to be transmitted to the terminal to a corresponding terminal. And a means for starting processing of data received from a terminal in synchronization with a leading edge of a clock pulse generated by the clock pulse generating circuit, and a trailing edge of the clock pulse. And a means for executing data transmission to the terminal in synchronization with the data processing apparatus.