JPH05314055A - Information processor and microprocessor semiconductor device for same - Google Patents

Abstract

PURPOSE:To simplify circuits and to decrease the pattern amount of a printed wiring board by unifying bus systems in the case of connecting a ROM and a DRAM, for which the timing of address and data signals is different each other, through the buses to a microprocessor. CONSTITUTION:Signals on buses 8 and 9 from a microprocessor 1 are converted to signals for a DRAM 6 and connected through buses 10 and 11 to a bus interface circuit 4 by a DRAM control circuit 3. It is identified from address signals on the bus 8 by an address decoder circuit 2 whether the access destination is a ROM 5 or the DRAM 6, and the result is transmitted to the bus interface circuit 4. Based on this identified result, the bus interface circuit 4 selects either the side of buses 8 and 9 or the side of buses 10 and 11 and connect the selected side through buses 12 and 1 3 to the ROM 5 and the DRAM 6.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing device and its microprocessor semiconductor device, and more particularly to a microprocessor.
It relates to the configuration of address and data buses between a processor and a plurality of memories.

[0002]

2. Description of the Related Art A conventional information processing apparatus includes a microprocessor 1 and a DRAM control circuit 3 as shown in FIG.
And a ROM 5 and a DRAM 6, which are directly connected to the CPU address bus 8 and the CPU data bus 9 output by the microprocessor 1.
6 is a DRAM address bus 10 and a DR which are generated in the DRAM control circuit 3 and which are in timing with the DRAM.
The AM data bus 11 is connected. That is, in the conventional information processing apparatus, the timings of the address signal and the data signal are different between the ROM and the DRAM, so that two lines of bus signals are required in the apparatus.

[0003]

In this conventional information processing apparatus, since there are two independent bus signals in the apparatus, the circuit becomes complicated and the amount of patterns on the printed wiring board increases. There was a point.

[0004]

According to an information processing apparatus of the present invention, a microprocessor and an R and which stores a program or data in which timings of address and data signals on a bus connecting the microprocessor are different from each other.
In an information processing device having an OM and a DRAM, an address decoder circuit for monitoring the first bus from the microprocessor and discriminating between access to the ROM and access to the DRAM, and the first bus Second timing signal for the DRAM based on the signal
A DRAM control circuit connected to the bus, a third bus connecting the ROM and the DRAM, and the address
A bus interface circuit is provided which selects either the first bus or the second bus according to the identification result of the decoder circuit and connects the selected bus to the third bus.

A microprocessor semiconductor device according to the present invention is a semiconductor device including the microprocessor used in the information processing device having the above configuration, wherein the address decoder circuit, the DRAM control circuit, and the bus An interface circuit is included in the same chip as the microprocessor.

[0006]

The present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention. A CPU address bus 8 and a CPU data bus 9 are output from the microprocessor 1 and input to the address decoder circuit 2, the DRAM control circuit 3 and the bus interface circuit 4, respectively. The DRAM control circuit 3 converts the timing signal corresponding to the DRAM 6 based on the CPU address bus 8 and the CPU data bus 9, and D
RAM address bus 10 and DRAM data bus 1
1 is output and input to the bus interface circuit 4. The address decoder circuit 2 monitors the CPU address bus 8 so that the microprocessor 1 can
It is detected whether or not 6 is accessed, and the bus switching signal 7 is output. The bus interface circuit 4 responds to the bus switching signal 7 by the CPU address bus 8, CPU data bus 9 side or DARAM address bus 10, DR.
The AM data bus 11 side is selected, output to the system address bus 12 and the system data bus 13, respectively, and connected to the ROM 5 and the DRAM 6, respectively.

Next, the operation will be described. When the microprocessor 1 accesses the ROM 5, the address for accessing the ROM 5 is output from the microprocessor 1 to the CPU address bus 8, and the access to the ROM 5 is detected by the address decoder circuit 2. A low level signal is output as the bus switching signal 7.
The bus interface circuit 4 selects the CPU address bus 8 and the CPU data bus 9 from the level of the bus switching signal 7 and outputs them to the system address bus 12 and the system data bus 13. The ROM 5 outputs data to the system data bus 13 according to the address information on the system address bus 12 and is input to the microprocessor 1 through the bus interface circuit 4.

When the microprocessor 1 accesses the DRAM 6, the CPU address bus 8 and CP
D in the DRAM control circuit 3 based on the signal of the U data bus 9
The timing signal for RAM is converted and output to the DRAM address bus 10 and the DRAM data bus 11, respectively, and the address decoder circuit 2 detects access to the DRAM 6 and outputs a high level signal to the bus switching signal 7. The bus interface circuit 4 outputs the bus switching signal 7
DRAM address bus 10 and DR according to the level of
The AM data bus 11 is selected and output to the system address bus 12 and the system data bus 13, respectively, and the DRAM 6 is accessed.

Although the microprocessor semiconductor device may be composed of only the microprocessor 1, the address decoder circuit 2, the DRAM control circuit 3 and the bus interface circuit 4 are connected to the microprocessor 1 and signals between them. Microprocessor semiconductor devices can be configured with the wires in the same chip. In this case, the microprocessor and other circuits can be integrated without increasing the number of input / output pins of the microprocessor semiconductor device.

[0011]

As described above, the information processing apparatus of the present invention outputs the address decoder circuit for identifying whether to access the ROM or the DRAM, the address bus for the DRAM, and the data bus. It has a DRAM control circuit and a bus interface circuit for selecting a bus system according to the identification result of the address decoder circuit, and the address bus, data bus and D of the microprocessor itself.
By selecting the address bus and data bus for RAM in a time-division manner, it becomes possible to have one bus system in the device, which simplifies the circuit and reduces the amount of patterns on the printed wiring board. You can

Further, in the microprocessor semiconductor device of the present invention, since the address decoder circuit, the DRAM control circuit and the bus interface circuit are formed on the same chip as the microprocessor, the number of input / output pins is increased. It is possible to integrate without further, the circuit configuration can be further simplified, and the amount of wiring patterns can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a block diagram of a conventional information processing device.

[Explanation of symbols]

 1 Microprocessor 2 Address Decoder Circuit 3 DRAM Control Circuit 4 Bus Interface Circuit 5 ROM 6 DRAM 8 CPU Address Bus 9 CPU Data Bus 10 DRAM Address Bus 11 DRAM Data Bus 12 System Address Bus 13 System・ Data bus

Claims (2)

[Claims] 1. An information processing apparatus comprising: a microprocessor; and a ROM and a DRAM for storing programs or data in which timings of address and data signals on a bus connected to the microprocessor are different from each other. An address decoder circuit for monitoring a first bus from the memory device to identify whether the access is to the ROM or the DRAM,
Of the address control circuit, a DRAM control circuit for converting the timing signal for the DRAM based on the signal of the bus and connecting it to the second bus, a third bus for connecting the ROM and the DRAM, and the address decoder circuit An information processing apparatus, comprising: a bus interface circuit that selects either the first bus or the second bus according to a result and connects the selected bus to the third bus. 2. A semiconductor device including the microprocessor used in the information processing apparatus according to claim 1, wherein the address decoder circuit, the DRAM control circuit, and the bus interface circuit are the microprocessors. A microprocessor semiconductor device characterized by being included in the same chip as a processor.