JPH05314676A - Data playback device - Google Patents

Abstract

(57) [Abstract] [Purpose] To further simplify the configuration in decoding using a simplified decoding algorithm (Wood's algorithm). [Structure] Partial response class IV as modulation code
In a data reproducing apparatus in which a code is used and a maximum likelihood decoding method such as a Viterbi decoding method is used as a decoding method, the time axis is aligned as a read clock RCK to the memory 75 for decoding data store used in the decoding circuits 40A and 40B. The clock from the clock generation circuit 21 is used, and the RAM 75 is made to function not only for data storage but also for jitter correction.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data reproducing apparatus suitable for application to a digital magnetic recording / reproducing apparatus and the like.

[0002]

2. Description of the Related Art In a digital magnetic recording / reproducing apparatus, when a partial response class IV code is used as its modulation code, a maximum likelihood decoding method such as a Viterbi decoding method is used as a decoding method to decode the reproduction data. Are known. The reproducing system of this digital magnetic recording / reproducing apparatus is constructed as shown in FIG.

In the data reproducing apparatus 10 shown in FIG. 7, the magnetic tape 11 has a partial response class IV.
A modulation code of (1, 0, -1) is recorded and reproduced by the magnetic head 12. The reproduced code is supplied to the A / D converter 14 via the amplifier 13 and converted into a digital signal, and then written in a memory (FIFO type memory in this example) 15 for removing jitter. Reference numeral 20 denotes a PLL circuit for reproducing a clock from a reproduced code, and the reproduced code is written based on the clock whose time axis varies according to the input jitter obtained from the PLL circuit.

Reference numeral 21 is a clock generation circuit for generating a clock whose time axis is aligned, and a reproduction code is read based on this clock. The read reproduction code is supplied to the digital decoding circuit 40, and the reproduction code is decoded. The decoded data is supplied to the sync detection circuit 16, a sync is detected from the decoded data, and then the signal is supplied to the signal processing circuit 17 and signal processing is performed based on the reproduced sync. Decoded data without jitter can be obtained at the terminal 18.

Partial response class IV (1, 0,
The system polynomial of the code of -1) is given by G (D) = 1-D ² (1). Here, D is the delay time of the unit arithmetic element.

The modulation circuit 30 given by this system polynomial G (D) is as shown in FIG.

In the figure, the input code supplied to the terminal 31 is supplied to the adder 32, and at the same time, a pair of delay elements (unit operation elements) 33 and 34 connected in cascade
A code delayed by D is formed, which is added to the adder 32 in reverse polarity. As a result, the output terminal 35 has (1)
The modulated data given by the formula will be output.

The system polynomial shown in equation (1) can be transformed into equation (2). G (D) = (1-D) (1 + D) (2) This is equivalent to one consisting of two sequences thinned out every other bit, which is an independent partial response. It is a system of (1, -1) code.

Consider that the partial response (1, -1) code shown in the equation (2) has two independent sequences having a memory order of 1 and a number of states of 2 and is interleaved. You can Therefore, if the decoding process is performed for each of the reproduction systems, the number of states is small, and thus the determination method for decoding can be simplified.

A state transition diagram when the number of states is 2 is shown in FIG.
And the trellis diagram at that time is shown in FIG. Since the number of states is 2, two states of ak = + 1 and ak = −1 are shown.

As the data decoding method, the Viterbi decoding method, which is a kind of maximum likelihood decoding method, is used. However, as described above, the class IV partial response code is considered to be two independent sequences interleaved with each other. Also, as the Viterbi decoding circuit 40, two independent decoding circuits 40A and 40B are provided as shown in FIG. 11, and these are selectively operated alternately bit by bit. Therefore, the reproduction code supplied to the terminal 41 can be switched alternately bit by bit.
It is separated into odd bits and even bits by 2 and supplied to the corresponding decoding circuits 40A and 40B.

Since the data decoded by the decoding circuits 40A and 40B are alternately selected by the changeover switch 43, the same data as that obtained by decoding the class IV partial response code is obtained at the output terminal 44.

Here, when the Viterbi decoding method is adopted as the maximum likelihood decoding method, one surviving path (branch metric) of two states (-1, + 1) is calculated from the current state and the previous state. Must. Since the surviving path is the path with the maximum sum of branch metrics, the following processing is performed to find this path.

[0014] a certain path metric L _k to the sample time (time) k may use the expression as follows the value L _k-2 of the path metrics up to one previous sampling time k-2.

L _k ⁺ = max {L _k−2 ⁺ + [− (y _k −0) ² ], L _k−2 ⁻ + [− (y _k −2) ² ]} (3 ^{_{) L k - = max {L}} k-2 + + [- (y k +2) 2], L k-2 - + [- (y k -0) 2]} ····· (4) here , L _k ⁺ is a path metric that goes to the state of ak = + 1, and L _k ⁻ is a path metric that goes to the state of ak = −1.

FIG. 12 shows a concrete example of the decoding circuit 40A (40B) for outputting the optimum path while calculating this metric. This is a circuit configuration that faithfully reproduces the equations (3) and (4), and this is a well-known circuit configuration. In the figure, it is shown as y _k = y.

A reproduction code y is supplied to the terminal 50. The coefficient unit 51 outputs "-2", and the coefficient unit 52 outputs "+2". The adder 53 performs an addition process of x = y−2, and the adder 54 performs an addition process of x = y + 2.

Numerals 55, 56 and 57 are squarers from which-(y-0) ² ,-(y-2) ² and-(y
Each squared output of +2) ² is obtained. Reference numerals 60 and 61 denote circuits that output path metrics L _k-2 ⁺ and L _k-2 ⁻ one sample before.

In the adder 62, {L _k-2 ⁺ -(y _k-
0) ² } is added to the adder 63, and {L _k-2
^- - addition processing (y _k -0) ^2} is performed. Further, in another adder ^{_{64, {L k-2 +}} - (y k -2) 2} - the process of adding is performed, the adder _{65, {(y k +2)} 2 L k-2 +} Addition processing is performed.

In the comparator 66, the size discrimination processing of the equation (3) is performed, and the larger one Lk ⁺ is one shift register 68.
Stored in. In the comparator 67, the size discrimination processing of the equation (4) is performed, and the larger one Lk ^- is used for the other shift register 6
8 is stored.

If the processes of the equations (3) and (4) are faithfully reproduced in this way, the configuration of the decoding circuit 40A becomes complicated, so that a simplified configuration is considered. The simplified Viterbi decoding circuit is a so-called Wood decoding method, and a Viterbi decoding circuit (also referred to as Wood decoding circuit) using this simplified Viterbi algorithm (hereinafter referred to as Wood algorithm) is already known. (For example,
`` Viterbi Detection of Class IV Partial Response on
a Magnetic Recording Channel ”IEEE TRANSACTIONS
ON COMMUNICATIONS. VOL.COM-34.NO.5, MAY 1986).

[0022]

However, even the Viterbi decoding circuit using the Wood algorithm requires the FIFO type memory 15 as shown in FIG. 7, so that the configuration is simplified. I'm still not completely satisfied.

Therefore, the present invention solves such a conventional problem, and proposes a data reproducing apparatus using a Viterbi decoding circuit using the Wood algorithm which can omit the memory of the FIFO format. ..

[0024]

In order to solve the above problems, according to the present invention, a partial reproduction class IV code is used as a modulation code and a maximum likelihood decoding method is used as a decoding method. A feature is that a function for removing jitter from reproduced data is added to a memory for storing decoded data used in a decoding circuit.

[0025]

[Function] A partial response class IV code is used as a data modulation code. The maximum likelihood decoding method, particularly the Viterbi decoding method, is applied as the decoding method. Even in the Viterbi decoding method, the simplified Wood decoding method is adopted particularly to simplify the configuration. As shown in FIG. 3, a dual port memory 75 is used for the decoding circuit 40, and the write clock WCK is the clock extracted from the reproduction code. This clock is a clock with jitter.

Reading from the memory 75 is performed by a clock RCK whose time axis is aligned. As a result, even if the A / D-converted reproduced code with jitter is directly written to the memory 75, the data having the uniform time axis can be output from the memory 75. As a result, the time axis correction FIFO memory 15 is not required, and the structure can be further simplified.

[0027]

EXAMPLES Next, an example of applying the data reproducing apparatus according to the present invention to the above-mentioned magnetic recording / reproducing apparatus will be described.
A detailed description will be given with reference to the drawings.

FIG. 1 is a system diagram showing an example of a data reproducing apparatus 10 to which the present invention is applied. As with FIG. 7, the modulation code recorded on the magnetic tape 11 is reproduced by the magnetic head 12 and is amplified. A / D converter 1 via 13
4 and is converted into a digital signal. In addition to the magnetic tape 11, the recording medium may be a magnetic disk, an optical disk, an optical tape, or the like.

The digitized reproduction code is directly supplied to the digital decoding circuit 40 for decoding and the write clock WCK from the PLL circuit 20.
Decoded data is written in the memory 75 (see FIG. 3) by the, and the data is read by the read clock RCK obtained from the clock generation circuit 21 with the aligned time axis. As a result, the decoded data whose time axis is corrected by the operation of the memory 75 is output.

As described above, the maximum likelihood decoding method is used for decoding the reproduction code. In the present invention, the decoding process is performed by the Wood's simplified decoding circuit. In the decoding process using the simplified Viterbi algorithm, partial response codes (1,
Since it handles -1), the number of states is 2.

When there are only two states, there are only the following three branches (paths) that can survive at that time. (1) A branch having a positive divergence state (FIG. 2A), which is a path from the state “−1” to the state “−1” and a path from the state “−1” to the state “+1” (2) A branch in a parallel state (Fig. 2B), which is a path from the state "-1" to the state "-1" and a path from the state "+1" to the state "+1" (3) A negative divergence state Branch (Figure 2C),
This is the path from state "+1" to state "+1",
In addition, the differential metric ΔL _k is calculated by the Wood algorithm, which is a simpler survivor path determination method in the path Viterbi algorithm from the state “+1” to the state “−1”. The differential metric ΔL _k is obtained from the difference between the path metrics L _k ⁺ L _k ⁻ of “+1” and “−1”. ^{_{ΔL k = L k + -L k}} - ···· (5) This equation can be modified as follows. ^{_{△ L k = L k + -L}} k - = max {L k-2 +, L k-2 - + 4y k -4} -max {L k-2 + -4y k -4, L k-2 -} ···· (6) = - △ L k-2 + 8y k -max {4,4y k - △ L k-2} -max {-4,4y k - △ L k-2} ···· ( 7) Here, (4y _k −ΔL _{k −2} ) is a common term, so
By comparing this value with "4" and "-4" and judging the magnitude, it is possible to know which branch was selected. By calculating this, it is possible to determine which pattern of the branch described above survives.

That is, even if the path metric itself is not calculated, if the differential metric is calculated, the path can be determined in that process. (△ 4y _k − △ L
When the case divided into three types depending on the value of the _{k-2), △ L k} = 4y k -4; 4 <4y k - △ L k-2 ···· (8) △ L k = △ L k; -4 _{<4y k - △ L k-} 2 <4 ···· (9) △ L k = 4y k +4; 4y k - △ L k-2 <-4 ···· (10) further △ L _k = 4y _{If p-} 4β is used for variable conversion, y _p −β = y _k −1; −β + 1 <y _k −y _p ··· (11) y _p −β = y _p −β; −β-1 <y is as _{y k -y p <-β-1} ···· (13); k -y p <-β + 1 ···· (12) y p -β = y k +1.

Now, let us consider the meanings of β and y _p .

Β takes a value of βE {-1, + 1} (where E is a symbol representing an element), and represents the transition pattern at the immediately preceding state transition candidate (position p). In other words, it represents the type of transition at the time point p where the transition (plus divergence or minus divergence) other than the first parallel path going back from the current time k is considered as a candidate. y
_p is the value of y at that time.

[0035] For example, when the likely positive divergence occurs in the time p of the previous (last branch that is not determined), beta = + 1, and the update rule judgment condition and beta and y _p at this time is FIG. 2 become that way.

The meaning of β can be regarded as having a role of adding an offset to the threshold value for the judgment in the above equation.

In the Wood algorithm simplified in this way, the probability of the state transition candidate at the previous time point p and the transition at the current sampling time point k are compared, and the more probable one is the new state transition candidate. While repeating, the judgment is repeated. Since the person who loses the judgment is regarded as having no transition, the memory 75 for storing the surviving path can be randomly accessed so that the information (reproduction code) at the time point p or the time point k can be freely updated. used.

Therefore, the state of divergence or the parallel state at the current time k can be known depending on the range of the reference coefficient value where the level difference between the path metric at the current time k and the path metric at the time point p before one time point is present. Depending on time k
You can ask for your previous survival path.

FIG. 3 shows an example of a decoding circuit (Wood decoding circuit) 40A based on the Wood algorithm for realizing such an algorithm. Decoding circuit 40 shown in FIG.
Since A and 40B have the same configuration, only the decoding circuit 40A will be described.

The reproduced signal yk supplied to the terminal 50 is delayed by one time point by the delay element 71, and the delayed signal and the reproduced signal are supplied to the subtractor 72 to generate a difference signal (yk-y
p) is generated. The difference signal is supplied to the discriminating circuit 73 and discriminated from the reference coefficient value. This discriminant is as described above.

Reference numeral 74 denotes a coefficient unit, which outputs three kinds of coefficient values (+2, 0, -2) in this example. Coefficient value "+
2 "is a coefficient value when the state" -1 "transits to the state" +1 ", and a coefficient value" -2 "is a coefficient value when the state" +1 "transits to the state" -1 ". A coefficient value of "0" is applied to the parallel transition.

The discrimination circuit 73 carries out three types of discrimination processing as described above, and the value of β {+
1, −1} is set, and this is loaded into the load circuit 75 having a latch function. Discrimination circuit 7 for loading
A load signal (update signal) is also output from 3.
When the load signal is "1", the load process of the load circuit 75 is executed.

According to the result of the state determination, write data (output data from the determination circuit 73) to the RAM 75 functioning as a dual port memory and an address indicating its storage position (indicated by the write clock WCK for convenience).
Is different.

Therefore, first, the write clock WCK generated from the PLL circuit 20 is supplied to the address counter 77, and the write address k (which also indicates the present time) obtained from this is supplied to the changeover switch 79. The write address k is supplied to the load circuit 78, and its value is loaded when the load signal becomes "1". Therefore, the timing of loading is when the state of the path metric one time before indicates divergence.

The loaded write address p is supplied to the changeover switch 79, the write address k or p is selected by the switch control signal output from the discrimination circuit 73, and the RAM 75 is selected according to the selected write address.
Is specified. The switch control signal is a signal which becomes "1" when the point one time before indicates divergence, and at that time, the write address p is selected.

The relationship between the input data to the RAM 75, β, the control signal and the load signal is summarized as shown in FIG.

The RAM 75 is supplied with a read address (for convenience indicated as a read clock) formed by the read clock RCK whose time axis is aligned from the clock generation circuit 21, and the data is sequentially output. This data is the decoded data. Decoded data is data from which the influence of inter-code interference has been removed and jitter has been removed.

Next, the decoding circuit 40A configured as described above.
An example of the decoding operation of will be described with reference to FIGS. 4 and 5. However, the initial values are y _p = −2 and β = −1. (1) k = 0: input k0 = 1.6 y _k −y _p > 2. (See FIG. 4). That because the divergence of positive (upward), the β +1, and _{p = 0, y p = y} 0. (2) k = 1: input k1 = 0.2 −2 <y _k −y _p ≦ 0. It can be judged that it was. In other words, since it is a parallel path, β, y
Data _p is written to address 1 with _p unchanged. (3) k = 2: input k2 = −0.2 −2 <y _k −y _p ≦ 0. It can be judged that it was. In other words, since it is a parallel path, β, y
Data _p is written to address 2 with _p unchanged. (4) k = 3: input k3 = 2 y _k −y _p > 0. It can be judged that it was.
That is, since it is a positive divergence, β is set to +1 and p =
3, y _p = y ₃ . Here, since the previous candidate has been lost, the data 0 is written in the address 0 of the RAM 75. (5) k = 4: input k4 = 0.2 −2 <y _k −y _p ≦ 0. It can be judged that it was. In other words, since it is a parallel path, β, y
Data _p is written to address 4 with _p unchanged. (6) k = 5: input k5 = −0.4 y _k −y _p ≦ −2, so the condition A. It can be judged that it was. In other words, since it is a minus (downward) divergence, β
Is set to −1 and p = 5 and y _p = y ₅ . Here, since the previous candidate is correct, the data 1 is written in the address 3 of the RAM 75. (7) k = 6: input k6 = −0.2 0 ≦ y _k −y _p <+2. It can be judged that it was. In other words, since it is a parallel path, β, y
Data _p is written to address 6 with _p unchanged. (8) k = 7: input k7 = −2.0 y _k −y _p ≦ 0. It can be judged that it was.
That is, since it is a negative divergence, β is set to −1 and p
= 7, y _p = y ₇ . Here, since the previous candidate is lost, the data 0 is written in the address 5 of the RAM 75. (9) k = 8: input k8 = 0.20 ≦ y _k −y _p ≦ + 2. It can be judged that it was. In other words, since it is a parallel path, β, y
Data _p is written to address 8 with _p unchanged.

Here, the write clock WCK for the RAM 75 is a clock generated by the PLL circuit 20, and this clock is a clock having input jitter (FIG. 6A). Therefore, the data is written to the RAM 75 following this input jitter (B in the figure).

Read clock R supplied to RAM 75
Since CK is a clock whose time axis is aligned as in C of the same figure, the time axis of read data is also constant (D of the same figure). Therefore, by driving the RAM 75 in this way, the time axis correction FIFO 15 used in the past can be substituted by the RAM 75.

[0051]

As described above, in the maximum likelihood decoding according to the present invention, the reproduction code can be decoded using a simplified decoding algorithm such as the Wood algorithm, and
A memory for storing code data is also used as a memory for time axis correction.

According to this, there is a feature that the structure can be greatly simplified as compared with the conventional one.

[Brief description of drawings]

FIG. 1 is a system diagram showing an example of a data reproducing apparatus according to the present invention.

FIG. 2 is a diagram showing conditions for determining a surviving path.

FIG. 3 is a system diagram showing an example of a Wood decoding circuit.

FIG. 4 is a diagram showing determination conditions used in Wood's algorithm.

FIG. 5 is a waveform diagram for explaining the operation of Wood's algorithm.

FIG. 6 is a waveform diagram for explaining a time axis correction operation.

FIG. 7 is a system diagram showing an example of a conventional data reproducing device.

FIG. 8 is a system diagram of a modulation circuit.

FIG. 9 shows a state transition diagram of a partial response {+1, −1} code.

10 is a trellis diagram of FIG. 9.

FIG. 11 is a system diagram of a Viterbi decoding circuit using a differential metric.

FIG. 12 is a system diagram showing an example of a Viterbi decoding circuit.

[Explanation of symbols]

 10 Data Reproducing Device 14 A / D Converter 16 Sync Detection Circuit 17 Signal Processing Circuit 20 PLL Circuit 21 Clock Generation Circuit 40 Digital Decoding Circuit 40A, 40B Wood Decoding Circuit 73 Discrimination Circuit 75 RAM

Claims (5)

[Claims] 1. In a data reproducing apparatus in which a partial response class IV code is used as a modulation code and a maximum likelihood decoding method is used as a decoding method, a decoded data store memory used in the decoding circuit stores data from the reproduced data. A data reproducing device having a function of removing jitter. 2. A pair of decoding circuits for partial response {-1,1} code reproduction are used as a decoding circuit, and the input data is decoded by using these decoding circuits while interleaving them. Item 1
The described data reproducing device. 3. The data reproducing apparatus according to claim 1, wherein a Viterbi decoding method is used as the maximum likelihood decoding method used in the decoding process. 4. A decoding circuit for a Viterbi algorithm used for partial response {-1,1} code reproduction, which uses a simple algorithm for calculating a differential metric and sequentially determining surviving paths. The data reproducing apparatus according to claim 1, wherein a circuit is used. 5. The memory is configured such that data decoded based on a clock reproduced from input data is written, the decoded data is read by a clock having a uniform time axis, and data without jitter is output. The data reproducing apparatus according to claim 1, characterized in that.