JPH05315190A - Chip type electric double layer capacitor - Google Patents
Chip type electric double layer capacitorInfo
- Publication number
- JPH05315190A JPH05315190A JP4115604A JP11560492A JPH05315190A JP H05315190 A JPH05315190 A JP H05315190A JP 4115604 A JP4115604 A JP 4115604A JP 11560492 A JP11560492 A JP 11560492A JP H05315190 A JPH05315190 A JP H05315190A
- Authority
- JP
- Japan
- Prior art keywords
- electrode plate
- electric double
- double layer
- element laminated
- layer capacitor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000003990 capacitor Substances 0.000 title claims description 28
- 229920005989 resin Polymers 0.000 claims abstract description 22
- 239000011347 resin Substances 0.000 claims abstract description 22
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 12
- 238000002347 injection Methods 0.000 claims description 5
- 239000007924 injection Substances 0.000 claims description 5
- 239000008151 electrolyte solution Substances 0.000 claims description 4
- 238000010030 laminating Methods 0.000 claims 1
- 238000003475 lamination Methods 0.000 abstract 2
- 239000011248 coating agent Substances 0.000 abstract 1
- 238000000576 coating method Methods 0.000 abstract 1
- 238000000465 moulding Methods 0.000 description 7
- 229910052799 carbon Inorganic materials 0.000 description 5
- 239000003822 epoxy resin Substances 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 229920000647 polyepoxide Polymers 0.000 description 3
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 2
- 239000004734 Polyphenylene sulfide Substances 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- 229920000069 polyphenylene sulfide Polymers 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 229920001169 thermoplastic Polymers 0.000 description 2
- 239000004416 thermosoftening plastic Substances 0.000 description 2
- 229910000640 Fe alloy Inorganic materials 0.000 description 1
- 229910001030 Iron–nickel alloy Inorganic materials 0.000 description 1
- 229910000990 Ni alloy Inorganic materials 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
Classifications
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E60/00—Enabling technologies; Technologies with a potential or indirect contribution to GHG emissions mitigation
- Y02E60/13—Energy storage using capacitors
Landscapes
- Electric Double-Layer Capacitors Or The Like (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は電気二重層コンデンサに
関し、特に表面実装に対応するチップ型電気二重層コン
デンサの素子およびケーシング構造に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electric double layer capacitor, and more particularly to an element and a casing structure of a chip type electric double layer capacitor which is compatible with surface mounting.
【0002】[0002]
【従来の技術】近年、ヘッドホンステレオ,コードレス
電話等携帯用の電子機器の小形化・薄形化には著しいも
のがある。これらの電子機器に実装される電気二重層コ
ンデンサも他の電子部品と同様に小型化・薄形化し、さ
らには表面実装化への要求が頻繁化しつつある。従来、
この種の電気二重層コンデンサとしては、大容量のコン
デンサを得る手段の一つとして、米国特許第35369
63号明細書にて開示されているように、カーボン粉末
と電解液とを接触させて、電気二重層を発生させること
を利用したものがある。図5は円筒形の電気二重層コン
デンサ素子(以下、素子と称す)の断面図である。2. Description of the Related Art In recent years, there have been remarkable reductions in the size and thickness of portable electronic devices such as headphone stereos and cordless phones. Electric double-layer capacitors mounted on these electronic devices are becoming smaller and thinner like other electronic parts, and moreover, the demand for surface mounting is increasing. Conventionally,
As an electric double layer capacitor of this type, one of means for obtaining a large capacity capacitor is disclosed in US Pat. No. 35369.
As disclosed in Japanese Patent No. 63, there is one utilizing contact between carbon powder and an electrolytic solution to generate an electric double layer. FIG. 5 is a sectional view of a cylindrical electric double layer capacitor element (hereinafter referred to as an element).
【0003】図5において、10は電子伝導性でかつイ
オン不浸透性の導電性セパレータ、12は分極性電極を
構成する粉末活性炭と電解質溶液からなるカーボンペー
スト電極、13はカーボンペースト電極間の導通を防止
するために設けたイオン透過性で、かつ非電子伝導性を
有する多孔性セパレータ、11はカーボンペースト電極
を保持し、かつ外界から遮断するために設けた非導電性
ガスケットである。図4は従来のチップ型電気二重層コ
ンデンサの右側面図およびそのA−A断面図である。In FIG. 5, 10 is an electrically conductive and ion-impermeable conductive separator, 12 is a carbon paste electrode made of powdered activated carbon and an electrolyte solution which constitutes a polarizable electrode, and 13 is a conduction between the carbon paste electrodes. An ion-permeable and non-electroconductive porous separator 11 is provided to prevent the above phenomenon, and a non-conductive gasket 11 is provided to hold the carbon paste electrode and shield it from the outside. FIG. 4 is a right side view of a conventional chip type electric double layer capacitor and a cross-sectional view taken along the line AA.
【0004】図4において、9aは素子9を積層した素
子積層体、4および5は夫々リード端子部4aおよび5
aを有する第1の電極板と第2の電極板、2は素子積層
体を加圧・保持するための保持部2aを有する挾持体、
3は第1および第2の電極板と挾持体とを絶縁するため
の絶縁層、1は外装のためのエポキシ樹脂等の絶縁樹脂
である。従来の電気二重層コンデンサは挾持体2にて素
子積層体9aを加圧保持した後、素子積層体9aの側面
での電気的短絡を防ぐために、エポキシ樹脂の溶液中に
浸漬させ、その後恒温室内で加熱硬化させて外装を行な
っていた。In FIG. 4, reference numeral 9a denotes an element laminated body in which the element 9 is laminated, and 4 and 5 lead terminal portions 4a and 5 respectively.
a first electrode plate and a second electrode plate having a, 2 is a holding body having a holding portion 2a for pressing and holding the element stack,
3 is an insulating layer for insulating the first and second electrode plates from the holding body, and 1 is an insulating resin such as an epoxy resin for exterior packaging. In the conventional electric double layer capacitor, after holding the element laminate 9a by the holding body 2 under pressure, it is dipped in a solution of epoxy resin in order to prevent an electrical short circuit on the side surface of the element laminate 9a, and then in a thermostatic chamber. It was heat-cured and was used for exterior packaging.
【0005】[0005]
【発明が解決しようとする課題】この従来のチップ型電
気二重層コンデンサは、断面コの字型の挾持体に第1の
電極板、素子積層体、第2の電極板を所定の位置に配置
し、第1の電極板を介して素子積層体を加圧した状態で
挾持体の先端を内側に略直角に折り曲げて保持部を形成
するため、およびエポキシ樹脂の溶液中に浸漬した後、
加熱硬化させるという外装方法のため、下記の問題点が
あった。 (1)挾持体の保持部は、成形後材料のスプリングバッ
クおよび素子積層体の圧縮応力により、図4(b)に示
す通り矢印方向に戻るため、素子積層体への保持圧力の
低下による電気二重層コンデンサの等価直列抵抗の増大
および外形寸法が増大する。 (2)付着樹脂量が多くなると外形寸法が増大すると同
時に寸法バラツキが増大する。 (3)外装面が凸凹しているため、真空吸着法によるプ
リント配線板への自動搭載が不可能である。 (4)2つのリード端子部が同一方向から突出している
ため、固着安定性が悪く、プリント配線板へのはんだ付
け後に振動が加わった場合、プリント配線板から離脱す
るものがある。In this conventional chip-type electric double layer capacitor, a first electrode plate, a device laminate and a second electrode plate are arranged at predetermined positions on a holding body having a U-shaped cross section. Then, in order to form the holding portion by bending the tip of the holding body inwardly at a substantially right angle in a state in which the element laminated body is pressed through the first electrode plate, and after immersing in the epoxy resin solution,
Due to the exterior method of curing by heating, there were the following problems. (1) The holding portion of the holding body returns in the direction of the arrow as shown in FIG. 4 (b) due to the springback of the material after molding and the compressive stress of the element laminated body, so that the holding pressure on the element laminated body reduces the electric The double-layer capacitor has an increased equivalent series resistance and an increased external dimension. (2) When the amount of adhered resin increases, the outer dimension increases and the dimensional variation increases at the same time. (3) Since the exterior surface is uneven, it cannot be automatically mounted on a printed wiring board by the vacuum suction method. (4) Since the two lead terminal portions project from the same direction, the fixation stability is poor, and when vibration is applied after soldering to the printed wiring board, the lead terminal portion may be separated from the printed wiring board.
【0006】本発明の目的は、小型で等価直列抵抗が低
く、プリント配線板への自動搭載が可能で、実装の安定
性がよいチップ型電気二重層コンデンサを提供すること
にある。An object of the present invention is to provide a chip type electric double layer capacitor which is small in size, has a low equivalent series resistance, can be automatically mounted on a printed wiring board, and has stable mounting.
【0007】[0007]
【課題を解決するための手段】本発明のチップ型電気二
重層コンデンサは、活性炭に電解液を含浸させた一対の
分極性電極を電子絶縁性でイオン透過性の多孔性セパレ
ータを介して対向させ、電子伝導性でイオン不浸透性の
導電性セパレータおよび非導電性のガスケットにより、
前記分極性電極を保持した素子を複数直列に接続する矩
形の素子積層体を2個並列に配置し、前記素子積層体の
積層方向の片面に2個の素子積層体を電気的に直列に接
続する中間電極板、他の片面に夫々が電気的に独立し、
外部へ電気的に引き出すリード端子を連接した一対の終
端電極板を介して2個の素子積層体を加圧・保持すべく
周囲を絶縁樹脂で被覆し、かつ前記素子積層体の各素子
間を接続する導電性セパレータを上下一体化したことを
特徴とする。さらに、中間電極板と接触している2個の
素子積層体の導電性セパレータを左右一体化したことお
よび絶縁樹脂を終端電極板側中央に設けた絶縁樹脂注入
ゲートより注入することを特徴とする。In a chip type electric double layer capacitor of the present invention, a pair of polarizable electrodes in which activated carbon is impregnated with an electrolytic solution are opposed to each other via an electronically insulating and ion permeable porous separator. , Electronically conductive, ion-impermeable conductive separator and non-conductive gasket,
Two rectangular element laminates that connect a plurality of the elements holding the polarizable electrodes in series are arranged in parallel, and the two element laminates are electrically connected in series on one surface of the element laminate in the stacking direction. The intermediate electrode plate, which is electrically independent on the other side,
The surroundings are covered with an insulating resin in order to pressurize and hold the two element laminated bodies through a pair of terminal electrode plates connected to lead terminals that are electrically drawn out to the outside, and the space between each element of the element laminated bodies is It is characterized in that the conductive separators to be connected are integrated vertically. Further, it is characterized in that the conductive separators of the two element laminated bodies in contact with the intermediate electrode plate are integrated left and right, and the insulating resin is injected from the insulating resin injection gate provided at the center of the end electrode plate side. .
【0008】[0008]
【実施例】次に、本発明について図面を参照して説明す
る。図1は本発明の第1の実施例のそれぞれ上面図、分
図(d)のA−A断面図,下面図および側面図である。
また図2は本発明の第1の実施例の電気二重層コンデン
サ素子の右側面図およびそのA−A断面図である。DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. 1A and 1B are a top view, a sectional view taken along line AA in FIG. 1D, a bottom view and a side view, respectively, of a first embodiment of the present invention.
FIG. 2 is a right side view of the electric double layer capacitor element according to the first embodiment of the present invention and a sectional view taken along the line AA.
【0009】図1および図2において、まず各素子9間
に導電性セパレータ10を1枚介在させて各素子9間を
接続する3枚分の素子9を積層した幅3.8mm,長さ
8.0mm,厚さ2.9mmの素子積層体9aを得る。
素子積層体9aは、2個を1辺が8mmの正方形で厚さ
0.4mmの鉄・ニッケル合金にはんだメッキを施した
中間電極板8に素子9の積層方向の片面が全面接触し、
かつ2個の素子積層体9aの間隔が約0.4mmとなる
ように配置する。次に、素子積層体9aの積層方向の他
の片面に幅3.0mm,厚さ0.4mm,長さ5.0m
mのリード端子6a,7aを突出させた幅3.8mm,
長さ8.0mmの鉄・ニッケル合金にはんだメッキを施
した1対の終端電極板6,7が全面接触するように配置
する。終端電極板6,7,中間電極板8,素子積層体9
aの相対位置関係を維持するようにかしめ,溶接等の公
知の手段で仮固定した後、縦10mm,横10mm,厚
さ4.1mmの中空部を有するモールド型に中間電極板
8側を下にしてセットし、終端電極板6,7,中間電極
板8を介して上下各4個の金型ピン(図示省略)で素子
積層体9aを無負荷時の約80%の厚さに圧縮させ、P
PS(ポリフェニレンサルファイド)等の熱可塑性で高
耐熱性の絶縁樹脂1を金型内の全間隙へ終端電極板6,
7側の上部中央の絶縁樹脂注入ゲート1cより注入し成
形する。絶縁樹脂注入ゲート1cは通称ピンポイントゲ
ートと呼ばれるもので、モールド成形完了時点の金型が
開く際に自動的に製品側の根本より切断される。また、
終端電極板側穴部1aおよび中間電極板側穴部1bは前
記金型ピンの後で、素子積層体9aはモールド成形完了
後も無負荷の約80%の厚さに圧縮されているため、透
過直列抵抗が低い電気二重層コンデンサとなる。次に、
リード端子6a,7aをリード成形金型を用いて、所定
の形状に成形する。図1はリード端子を外側に曲げるガ
ルウィングリードタイプ(図示省略)と比べて高密度実
装が可能なリード端子を内側に曲げるJベンドリードタ
イプにリード端子6a,7aを成形した例であり、製品
本体の下面の絶縁樹脂1に設けたリード収納溝1dにリ
ード端子6a,7aの先端部を収納することにより、製
品の厚さ方向の寸法増加を抑えると共にプリント配線板
へ実装した際のがたつきが小さくなる。以上により、本
発明の第1の実施例のチップ型電気二重層コンデンサを
得た。In FIG. 1 and FIG. 2, first, a conductive separator 10 is interposed between the respective elements 9 and three elements 9 for connecting the respective elements 9 are stacked, and a width of 3.8 mm and a length of 8 are obtained. An element stack 9a having a thickness of 0.0 mm and a thickness of 2.9 mm is obtained.
In the element stack 9a, one side in the stacking direction of the element 9 is entirely in contact with the intermediate electrode plate 8 formed by solder-plating two pieces of iron-nickel alloy with a side of 8 mm and a thickness of 0.4 mm.
In addition, the two element laminated bodies 9a are arranged so that the distance between them is about 0.4 mm. Next, a width of 3.0 mm, a thickness of 0.4 mm, and a length of 5.0 m are provided on the other surface of the element stack body 9a in the stacking direction.
The width of the lead terminals 6a, 7a of m is 3.8 mm,
A pair of terminal electrode plates 6 and 7 each having a length of 8.0 mm and having an iron / nickel alloy plated with solder are arranged so as to be in full contact. Termination electrode plates 6, 7, intermediate electrode plate 8, element stack 9
After caulking so as to maintain the relative positional relationship of a, and temporarily fixing it by a known means such as welding, the intermediate electrode plate 8 side is placed downward in a mold having a hollow portion of 10 mm in length, 10 mm in width, and 4.1 mm in thickness. Then, the element laminate 9a is compressed to a thickness of about 80% of that when no load is applied by using four upper and lower mold pins (not shown) through the terminal electrode plates 6 and 7 and the intermediate electrode plate 8. , P
A thermoplastic and highly heat-resistant insulating resin 1 such as PS (polyphenylene sulfide) is filled into the entire gap in the mold to form the terminal electrode plate 6,
It is injected from the insulating resin injection gate 1c at the center of the upper part on the 7 side and molded. The insulating resin injection gate 1c is generally called a pin point gate, and is automatically cut from the root of the product side when the mold is opened at the time of completion of molding. Also,
Since the terminal electrode plate side hole portion 1a and the intermediate electrode plate side hole portion 1b are compressed to a thickness of about 80% of no load after completion of molding, the element laminated body 9a is compressed after the mold pin. The electric double layer capacitor has a low transmission series resistance. next,
The lead terminals 6a and 7a are molded into a predetermined shape using a lead molding die. FIG. 1 shows an example in which the lead terminals 6a and 7a are molded into a J-bend lead type in which the lead terminals capable of high-density mounting are bent inward as compared with the gull-wing lead type (not shown) in which the lead terminals are bent outward. By accommodating the leading end portions of the lead terminals 6a and 7a in the lead accommodating groove 1d provided in the insulating resin 1 on the lower surface of the product, an increase in the size of the product in the thickness direction is suppressed and rattling occurs when the product is mounted on a printed wiring board. Becomes smaller. As described above, the chip type electric double layer capacitor of the first embodiment of the present invention was obtained.
【0010】図3は本発明の第2の実施例を説明するた
めの図面で図2の(b)に相当する。第1の実施例とは
中間電極板と接触している2個の素子積層体の導電性セ
パレータを左右一体化したことのみ異なる。そのため、
2個の素子積層体9aを同時に位置決めやハンドリング
できることおよび2個の素子積層体9aを同時に位置決
めやハンドリングができることおよび2個の素子積層体
9aの間隔を一定に保つことができる。その結果、素子
9および素子積層体9aの形成や終端電極6,7,中間
電極板8等との組立が容易となる。FIG. 3 is a drawing for explaining the second embodiment of the present invention and corresponds to FIG. 2 (b). It differs from the first embodiment only in that the conductive separators of the two element laminated bodies which are in contact with the intermediate electrode plate are integrated left and right. for that reason,
The two element laminated bodies 9a can be simultaneously positioned and handled, the two element laminated bodies 9a can be simultaneously positioned and handled, and the distance between the two element laminated bodies 9a can be kept constant. As a result, it becomes easy to form the element 9 and the element laminated body 9a and to assemble the terminal electrodes 6 and 7, the intermediate electrode plate 8 and the like.
【0011】次に本発明の一実施例と従来例のチップ型
電気二重層コンデンサの各100個の製品寸法値の測定
結果およびそのばらつきを表1に示した。Next, Table 1 shows the measurement results of 100 dimensional values of each of the chip type electric double layer capacitors of the embodiment of the present invention and the conventional example and their variations.
【0012】[0012]
【表1】 [Table 1]
【0013】表1から明らかなように、本発明の実施例
の電気二重層コンデンサは寸法が小さくなり、かつばら
つきも約1/4と小さくすることができた。As is apparent from Table 1, the electric double layer capacitors according to the examples of the present invention were small in size and the variation could be reduced to about 1/4.
【0014】[0014]
【発明の効果】以上説明したように本発明は下記の効果
を有する。 (1)非導電性ガスケットに設けるカーボンペースト電
極の充填部も含めて、電気二重層コンデンサ素子が矩形
のため、概略正四方形で構成される面積と前記正四方形
の内接円で構成される面積との比の分だけ、電気二重層
コンデンサ素子の体積効率が改善され、素子の外形寸法
を小さくできる。さらに、素子積層体を2個並列に配置
するため、1個の素子積層体の素子の積層枚数を従来の
1/2にでき、かつ各素子間を接続する導電性セパレー
タを上下一体化したため、素子積層体の厚さを薄くする
ことができる。また、素子積層体を加圧した状態でモー
ルド成形を行ない、モールド成形完了後も絶縁樹脂によ
り、モールド成形時の加圧状態を維持しているため、電
気二重層コンデンサの等価直列抵抗を小さくし、かつ外
形寸法を小さくできる。 (2)中間電極板と接触している2個の素子積層体の導
電性セパレータを左右一体化することにより、2個の素
子積層体が連結し、2個の素子積層体の間隔を一定に保
つことができるため、素子積層体同士の接触による短絡
や、離間による素子積層体の絶縁樹脂表面からの露出を
防止できる。また、2個の素子積層体を同時に位置決め
やハンドリングができるため、素子および素子積層体の
形成や組立が容易となる。 (3)熱可塑性の絶縁樹脂を終端電極板側の中央部より
注入するモールド成形による外装方法のため、2個の素
子積層体の間に絶縁樹脂が注入された後、金型内の全間
隙へ樹脂が注入されるため、2個の素子積層体同士の接
触による短絡を防止できる。また、素子積層体および終
端電極板,中間電極板を金型内の所定位置に保持し、注
入する絶縁樹脂の量も金型で制御されるので、外形寸法
を小さくすると同時に寸法バラツキも小さくできる。ま
た、外装面が平滑なため、真空吸着によるプリント配線
板への自動搭載が可能となる。さらに2つの終端電極板
と連接するリード端子の突出方向を互いに180°反対
方向にできるので、プリント配線板への固着安定性が良
くなる。As described above, the present invention has the following effects. (1) Since the electric double layer capacitor element is rectangular, including the filling portion of the carbon paste electrode provided in the non-conductive gasket, the area formed by the substantially square shape and the area formed by the inscribed circle of the square shape. The volumetric efficiency of the electric double layer capacitor element is improved by the amount of the ratio and the outer dimension of the element can be reduced. Furthermore, since the two element laminated bodies are arranged in parallel, the number of laminated elements of one element laminated body can be reduced to half of the conventional one, and the conductive separators connecting the respective elements are vertically integrated, The thickness of the element stack can be reduced. In addition, the element laminated body is molded under pressure, and the insulating resin maintains the pressure during molding even after the molding is completed, so the equivalent series resistance of the electric double layer capacitor is reduced. In addition, the external dimensions can be reduced. (2) By integrating left and right conductive separators of two element laminates that are in contact with the intermediate electrode plate, the two element laminates are connected and the distance between the two element laminates is made constant. Since this can be maintained, it is possible to prevent a short circuit due to contact between the element laminated bodies and an exposure of the element laminated body from the insulating resin surface due to separation. Further, since the two element laminated bodies can be positioned and handled at the same time, the elements and the element laminated bodies can be easily formed and assembled. (3) Since the insulating resin is injected between the two element laminated bodies due to the exterior method by molding in which the thermoplastic insulating resin is injected from the central portion on the side of the terminal electrode plate, the entire gap in the mold is obtained. Since the resin is injected into the structure, it is possible to prevent a short circuit due to contact between the two element laminated bodies. Further, since the element laminate, the terminal electrode plate, and the intermediate electrode plate are held at predetermined positions in the mold, and the amount of the insulating resin to be injected is also controlled by the mold, it is possible to reduce the outer dimensions and at the same time reduce the dimensional variation. . Further, since the exterior surface is smooth, it can be automatically mounted on the printed wiring board by vacuum suction. Furthermore, since the protruding directions of the lead terminals connected to the two termination electrode plates can be opposite to each other by 180 °, the fixing stability to the printed wiring board is improved.
【図1】本発明の第1の実施例のチップ型電気二重層コ
ンデンサの上面図,図1(d)のA−A断面図,下面図
および右側面図である。FIG. 1 is a top view of a chip type electric double layer capacitor of a first embodiment of the present invention, an AA sectional view of FIG. 1 (d), a bottom view and a right side view.
【図2】図1に示した素子積層体の右側面図およびその
A−A断面図である。2 is a right side view of the element stack body shown in FIG. 1 and a cross-sectional view taken along the line AA. FIG.
【図3】本発明の第2の実施例のチップ型電気二重層コ
ンデンサの素子積層体の断面図である。FIG. 3 is a sectional view of an element laminate of a chip-type electric double layer capacitor according to a second embodiment of the present invention.
【図4】従来のチップ型電気二重層コンデンサの右側面
図およびそのA−A断面図である。FIG. 4 is a right side view of a conventional chip type electric double layer capacitor and a cross-sectional view taken along the line AA.
【図5】図4に示した従来の電気二重層コンデンサ素子
の断面図である。5 is a cross-sectional view of the conventional electric double layer capacitor element shown in FIG.
1 絶縁樹脂 1a 終端電極板側穴部 1b 中間電極板側穴部 1c 絶縁樹脂注入ゲート 1d リード収納溝 2 挟持体 2a 保持部 3 絶縁層 4 第1の電極板 4a 第1の電極板のリード 5 第2の電極板 5a 第2の電極板のリード端子 6 第1の終端電極板 6a 第1の終端電極板のリード端子 7 第2の終端電極板 8 中間電極板 9 素子 9a 素子積層体 10 導電性セパレータ 11 非導電性ガスケット 12 カーボンペースト電極 13 多孔性セパレータ DESCRIPTION OF SYMBOLS 1 Insulating resin 1a Termination electrode plate side hole 1b Intermediate electrode plate side hole 1c Insulating resin injection gate 1d Lead accommodating groove 2 Clamp 2a Holding part 3 Insulating layer 4 First electrode plate 4a First electrode plate lead 5 Second electrode plate 5a Lead terminal of second electrode plate 6 First terminal electrode plate 6a Lead terminal of first terminal electrode plate 7 Second terminal electrode plate 8 Intermediate electrode plate 9 Element 9a Element laminate 10 Conductivity Separator 11 Non-conductive gasket 12 Carbon paste electrode 13 Porous separator
Claims (3)
性電極を電子絶縁性でイオン透過性の多孔性セパレータ
を介して対向させ、電子伝導性でイオン不浸透性の導電
性セパレータおよび非導電性のガスケットにより、前記
分極性電極を保持した素子を複数直列に接続する矩形の
素子積層体を2個並列に配置し、前記素子積層体の積層
方向の片面に2個の素子積層体を電気的に直列に接続す
る中間電極板、他の片面に夫々が電気的に独立し、外部
へ電気的に引き出すリード端子を連接した一対の終端電
極板を介して2個の素子積層体を加圧・保持すべく周囲
を絶縁樹脂で被覆し、かつ前記素子積層体の各素子間を
接続する導電性セパレータを上下一体化したことを特徴
とするチップ型電気二重層コンデンサ。1. A pair of polarizable electrodes, in which activated carbon is impregnated with an electrolytic solution, are opposed to each other via an electronically insulating and ion-permeable porous separator, and an electrically conductive and ion-impermeable conductive separator and a non-conductive separator are provided. Two rectangular element laminates that connect a plurality of elements holding the polarizable electrodes in series by a conductive gasket are arranged in parallel, and two element laminates are provided on one surface of the element laminate in the laminating direction. An intermediate electrode plate that is electrically connected in series, each of which is electrically independent on the other side, and two element laminated bodies are added through a pair of terminal electrode plates that are connected to lead terminals that electrically lead to the outside. A chip-type electric double layer capacitor, characterized in that the periphery thereof is covered with an insulating resin so as to be pressed and held, and conductive separators for connecting the respective elements of the element laminate are vertically integrated.
層体の導電性セパレータを左右一体化したことを特徴と
する請求項1記載のチップ型電気二重層コンデンサ。2. The chip type electric double layer capacitor according to claim 1, wherein the conductive separators of the two element laminated bodies which are in contact with the intermediate electrode plate are integrated left and right.
縁樹脂注入ゲートより注入されたことを特徴とする請求
項1記載のチップ型電気二重層コンデンサ。3. The chip type electric double layer capacitor according to claim 1, wherein the insulating resin is injected from an insulating resin injection gate provided at the center of the terminal electrode plate side.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4115604A JPH05315190A (en) | 1992-05-08 | 1992-05-08 | Chip type electric double layer capacitor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4115604A JPH05315190A (en) | 1992-05-08 | 1992-05-08 | Chip type electric double layer capacitor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH05315190A true JPH05315190A (en) | 1993-11-26 |
Family
ID=14666749
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4115604A Pending JPH05315190A (en) | 1992-05-08 | 1992-05-08 | Chip type electric double layer capacitor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH05315190A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2014535062A (en) * | 2011-09-07 | 2014-12-25 | クォルコム・メムズ・テクノロジーズ・インコーポレーテッド | Large area laminated metal structures and related methods |
-
1992
- 1992-05-08 JP JP4115604A patent/JPH05315190A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2014535062A (en) * | 2011-09-07 | 2014-12-25 | クォルコム・メムズ・テクノロジーズ・インコーポレーテッド | Large area laminated metal structures and related methods |
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