JPH05315526A - Semiconductor device - Google Patents

Abstract

(57) [Summary] [Structure] The circuit formation surface side of the semiconductor element 1 is connected to the electrode pad 1
Adhesive 2 is used to adhere to tab 3 having a shape that does not interfere with p, and electrode pad 1p and appropriate lead 4 are connected to wire 5
Electrically connected with the non-circuit forming surface side of the semiconductor element 1,
The tabs 3 are sealed and molded with a sealing resin so that both sides of the tab 3 where the semiconductor element 1 does not exist are exposed to the outside. [Effect] It is possible to obtain a semiconductor device which is thinner than the conventional TSOP, does not warp even when the temperature of the environment changes, and is cheaper than the case of using TAB.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a thin outer shape and applied to thin products such as memory cards.

[0002]

2. Description of the Related Art A cross section of a general semiconductor device is shown in FIG. Conventional semiconductor devices generally have 42%
A semiconductor element 1 is mounted on one surface of a mounting plate of a semiconductor element 1 called a tab 3 made of an iron material such as a nickel alloy (hereinafter referred to as 42 alloy) with an adhesive 2 from a non-circuit forming surface. Electrode pad 1p on the circuit formation surface of No. 1
The appropriate lead 4 is electrically connected (wire bonding) using a wire 5, and the whole of them is sealed and molded (molded) with a sealing resin 6, and the outer thickness is 2. It was about 5 to 3.5 mm. In recent years, due to demands for high-density mounting of semiconductor devices or application to thin products such as memory cards, a thin semiconductor device called TSOP (Thin Small Outline Package) with a thickness of 1 mm or less can be seen. However, they were not to change the structure but to mainly manufacture the semiconductor element 1, the tab 3, the sealing resin 6 and the like as thinly as possible. As another technique for providing a thin semiconductor device, as shown in FIG. 12, a foil lead 5b is used instead of a wire, and TAB (Tape Automated Bonding) is performed.
The semiconductor element 1 is electrically connected to the appropriate lead 4 by the above method, and the liquid crystal sealing resin 6 is dropped onto the circuit forming surface of the semiconductor element or the lead 4 and sealed (Tape C
arrier Package) is known. With this technology,
Since the foil lead 5b to be used can be connected without drawing a large loop like a wire, the thickness of the sealing resin 6 in the same portion can be reduced, and further, the semiconductor resin can be formed by the sealing method in which the sealing resin 6 is dropped. Since the non-circuit forming surface side of the element 1 is generally not covered with the sealing resin 6, there is a feature that the thickness of the semiconductor device can be reduced.

[0003]

The conventional thin semiconductor device as described above has the following problems and problems, respectively.

(1) TSOP: With the current structure, it is difficult to make it thinner than the current structure. Also, for example, when the thickness of the sealing resin on the circuit formation surface side of the semiconductor element is reduced or removed, the wire that draws the loop is exposed to the outside, and conversely the sealing resin on the back surface of the tab is exposed. If the above is removed, the same defect as described in detail in (2) may occur.

(2) TCP: As can be seen from FIG. 11, in this semiconductor device, only the back surface of the semiconductor element is exposed to the outside, and the member (resin 6) on the upper surface of the semiconductor device is formed.
And the lower surface member (semiconductor element 1 = silicon) have a greatly different linear expansion coefficient (sealing resin 6 >> silicon), so when the environmental temperature changes, a difference occurs in the amount of expansion (or amount of contraction) between them. As a result, warpage may occur in the outer shape of the semiconductor device, and the stress at that time may cause a defect such as cracking in the semiconductor element 1 or the sealing resin 6, or peeling of the bonding interface between the members. Such a defect is caused by the semiconductor element 1
The foil lead 5b may be violated by moisture in the outside air, or the foil lead 5b may be cut off, which may be a fatal injury. In addition, the TAB technology has a very high cost as compared with the case of using a wire, and is not suitable for mass production.

[0006]

It is apparent from the above figures that the thickness of the semiconductor device can be greatly reduced by removing the sealing resin on both surfaces of the semiconductor element and the tab. The present invention achieves this while solving the above problems, and the main means therefor is as follows.

That is, the side of the semiconductor element on which the circuit is formed is
A tab having a shape that does not interfere with the electrode pad is bonded with an adhesive, and the electrode pad and an appropriate lead are electrically connected by a wire, and the non-circuit forming surface side of the semiconductor element and the tab Encapsulate them with a resin for encapsulation so that the surface without the semiconductor element is exposed to the outside.
Mold.

[0008]

By taking such means, the following actions will occur.

The semiconductor device obtained by the above means is
It has a structure in which silicon is exposed on the upper surface and 42 alloy and other metal materials are exposed on the lower surface. Therefore, compared to the conventional semiconductor device, it is possible to reduce the thickness of the sealing resin on both sides by the thickness. Further, the wire draws a loop on the side surface of the tab at a height that is dimensionally less than or equal to the thickness of the tab, and therefore, the wire is never exposed to the outside and is sufficiently sealed. Therefore, TS
When manufacturing a semiconductor device thinner than OP, it is not necessary to use the TAB technique, and an inexpensive thin semiconductor device can be obtained. Furthermore, the upper and lower parts of the semiconductor device (silicon-
42 alloy) has a small difference in linear expansion coefficient, the semiconductor device does not warp even if the temperature of the environment changes, and thus it is possible to prevent the defects described in the section of the problem.

[0010]

Embodiments of the present invention will be introduced below with reference to the drawings.

FIG. 1 is a partial sectional perspective view of a semiconductor device according to a first embodiment of the present invention. On the front surface of tab 3,
The semiconductor element 1 is adhered using an adhesive 2 so that its circuit forming surface faces the tab 3. The tab 3 and the adhesive 2 are slightly smaller than the semiconductor element 1 in a portion where the electrode pad 1p group is configured so that the tab 3 and the adhesive 2 do not interfere with the electrode pad 1p when the semiconductor element 1 is bonded. .. After this state, the electrode pad 1p and the appropriate lead 4 are electrically connected by the wire 5, and the non-circuit forming surface of the semiconductor element 1 and the back surface of the tab 3 are exposed on the surface of the semiconductor device. Thus, it is sealed and molded with the sealing resin 6.

FIG. 2 is a sectional view taken along the line AA of the semiconductor device of FIG. As is apparent from the figure, the non-circuit forming surface of the semiconductor element 1 and the back surface of the tab 3 are both flush with the front surface of the semiconductor device. By doing so, the semiconductor device of the present invention can be thinned most effectively. In the case of a thin semiconductor device, the tab 3 has a thin thickness of about 150 μm in order to reduce the stress of the device after mounting on the substrate and the solder. Even so, the distance from the circuit forming surface of the semiconductor element 1 to the surface of the semiconductor device is 20 together with the thickness of the adhesive 2 (about 50 μm).
About 0 μm can be secured, and the loop height drawn by the wire 5 is 5 h
Since the wire 5 is thicker than, the wire 5 is sufficiently sealed without being exposed to the outside. The warp of the semiconductor device according to the present invention due to the change in the ambient temperature becomes the smallest when the planar shapes of the tab 3 and the semiconductor element 1 become congruent. Therefore, it is desirable that both have the same shape as much as possible, and the dimensional difference for avoiding interference with the electrode pad 1p portion should be suppressed as small as possible. Further, the leads 4 and the tab suspension leads 4t are provided with some down-sets (steps) with respect to the tabs 3 in order to improve the flow balance when the sealing resin 6 is sealed. In terms of the flow balance of the sealing resin 6, the downset value is optimally such that the leads 4 and 4t come to the center of the semiconductor device in the thickness direction, but in reality, the external lead 4g is bent. It should be considered separately from the viewpoint of the strength of the solder joint, depending on the direction and lead width.

FIG. 3 is a sectional view of the same portion as FIG. 2 of the semiconductor device according to the second embodiment of the present invention. In this embodiment, the two surfaces of the semiconductor device are slightly raised with respect to the non-circuit forming surface of the semiconductor element 1 and the back surface of the tab 3. For example, when the tab 3 and the adhesive 2 are very thin and their thickness dimension becomes smaller than the loop height 5h of the wire 5, in this way, only the thickness of the sealing resin 6 is required. It is good to make it thick.

FIG. 4 is a sectional view of a semiconductor device according to a third embodiment of the present invention, similar to FIG. In the present embodiment, the sealing resin 6 reaches the non-circuit forming surface of the semiconductor element 1 and part of the back surface of the tab 3. By doing so, the strength of the semiconductor device against a load in the thickness direction is improved, and it is possible to effectively prevent defects such as the tab 3 and the semiconductor element 1 coming off when such an external force acts.

FIG. 5 is a sectional view of the same portion as FIG. 2 of the semiconductor device according to the fourth embodiment of the present invention. In this embodiment, the side surface of the tab 3 is obliquely etched. By doing so, since the sealing resin 6 is interposed between the semiconductor element 1 and the tab 3, the strength of the semiconductor device against a load in the thickness direction is improved as in the third embodiment. It is to be noted that the purpose of the present embodiment is that the result is that the sealing resin 6 is interposed between the semiconductor element 1 and the tab 3, and in addition to this, for example, the shape of the adhesive 2 can be reduced. Even if you do it, you can get the corresponding effect.

FIG. 6 is a top plan view of the semiconductor device according to the fifth embodiment of the present invention. In this embodiment, the corner portion of the tab 3 is processed into an arc shape. By doing so, the stress generated in the semiconductor device when the semiconductor device is heated to a high temperature or when another external force is applied is relaxed, so that a defect such as cracking in the sealing resin 6 may occur. Suppressed.

FIG. 7 is a top plan view of the semiconductor device according to the sixth embodiment of the present invention. In this embodiment, the tab 3 is divided into two. By doing so, the relative displacement between the tabs 3 and the sealing resin 6 caused by the difference in thermal expansion between the respective tabs 3 when the environmental temperature changes is half that in the case where the tabs 3 are not divided. Becomes Therefore, the present embodiment is effective in preventing problems such as interface peeling between the tab 3 and the sealing resin 6 in such a case. If the semiconductor device is larger, the tab 3
The number of divisions may be increased.

FIG. 8 is a sectional view of the same portion as FIG. 2 of the semiconductor device according to the seventh embodiment of the present invention. In this embodiment, the non-circuit forming surface of the semiconductor device 1 and the back surface of the tab 3 are coated with a polyimide coat 7.

A general semiconductor device as shown in FIG. 11 is sealed with a sealing resin 6 by transfer molding. This is to inject the sealing resin 6 softened by heat at a high pressure into the cavity of the mold which is vertically separated by sandwiching the lead 4 group, the semiconductor element 1, the tab 3 and the like. In the present invention, the semiconductor element 1 and the tab 3 are exposed on the surface of the semiconductor device. Therefore, when molding by transfer molding, those hard members directly contact the cavity, so that there is no space between them. High dimensional accuracy is required. However, when a change in the amount of the adhesive 2 or a slight warp of the tab 3 occurs, for example, when the distance from the non-circuit forming surface of the semiconductor element 1 to the back surface of the tab 3 becomes smaller than the cavity size, When is covered with the sealing resin 6 and becomes large, on the other hand, inconvenience such as cracking of the semiconductor element 1 may occur due to tightening of the mold.

According to this embodiment, the semiconductor element 1 and the tab 3 are
Since the surface exposed portion of the is coated with a soft and stress-relieving coat 7, even if a dimensional error is unavoidable in the manufacturing process as described above, an appropriate load is always applied to the semiconductor element 1 and the tab 3. Is loaded, the above-mentioned inconvenience can be prevented. The coating 7 may be applied to only one side, if necessary. The coat 7 is not limited to the polyimide type, and may be a high heat resistant rubber material.

Next, as the semiconductor device of the eighth embodiment of the present invention, the surface coated in the previous example, that is, the non-circuit forming surface of the semiconductor element 1 and the back surface of the tab 3, or one of the surfaces is coated. It may also be painted black. By doing so, that portion has the same color as the color of the sealing resin 6, so that the semiconductor element 1 and the tab 3 are inconspicuous in appearance, and a design effect such that the texture of the semiconductor device itself is enhanced can be obtained. .. Note that this coating may be used as a marker for identifying a semiconductor device,
Therefore, a coating other than black may be used depending on the type and usage of the semiconductor device.

FIG. 9 is a sectional view of the same portion as FIG. 2 of the semiconductor device according to the ninth embodiment of the present invention. In this embodiment, the upper and lower surfaces of the semiconductor device are reversed by forming the leads 4 by bending them in the opposite direction. By doing so, the arrangement order of the leads can be reversed, and thus such a method may be adopted depending on the conditions and the form of the board to be mounted.

FIG. 10 is a sectional view of a semiconductor device according to the tenth embodiment of the present invention. In this embodiment, the tab suspension lead 4
The offset part of t is thinly processed by half etching. By doing so, it is possible to eliminate the protrusion in the plane of the same portion that has been seen in the above examples after the sealing resin 6 is sealed, so that the appearance quality of the semiconductor device is improved.

[0024]

According to the present invention, it is possible to obtain a semiconductor device which is thinner than the conventional TSOP, does not warp even when the environmental temperature changes, and is cheaper than the case where TAB is used.

[Brief description of drawings]

FIG. 1 is a partial cross-sectional perspective view of a semiconductor device according to a first embodiment of the present invention.

2 is a sectional view taken along line AA in FIG.

FIG. 3 is a sectional view of the same portion as FIG. 2 of a semiconductor device according to a second embodiment of the present invention.

FIG. 4 is a sectional view of the same portion as FIG. 2 of a semiconductor device according to a third embodiment of the present invention.

FIG. 5 is a sectional view of the same portion as FIG. 2 of a semiconductor device according to a fourth embodiment of the present invention.

FIG. 6 is a top plan view of a semiconductor device according to a fifth embodiment of the present invention.

FIG. 7 is a top plan view of a semiconductor device according to a sixth embodiment of the present invention.

FIG. 8 is a sectional view of the same portion as FIG. 2 of a semiconductor device according to a seventh embodiment of the present invention.

FIG. 9 is a sectional view of the same portion as FIG. 2 of a semiconductor device according to a ninth embodiment of the present invention.

FIG. 10 is a partial sectional view of a semiconductor device according to a tenth embodiment of the present invention.

FIG. 11 is a cross-sectional view of a conventional general semiconductor device.

FIG. 12 is a sectional view of TCP.

[Explanation of symbols]

1 ... Semiconductor element, 1p ... Electrode pad, 2 ... Adhesive, 3 ...
Tab, 4 ... Lead, 4t ... Tab suspension lead, 5 ... Wire, 5h ... Loop height, 6 ... Resin.

─────────────────────────────────────────────────── ───

[Procedure amendment]

[Submission date] May 18, 1992

[Procedure Amendment 1]

[Document name to be corrected] Drawing

[Name of item to be corrected] Figure 1

[Correction method] Change

[Correction content]

[Figure 1]

[Procedure Amendment 2]

[Document name to be corrected] Drawing

[Name of item to be corrected] Figure 2

[Correction method] Change

[Correction content]

[Fig. 2]

[Procedure 3]

[Document name to be corrected] Drawing

[Name of item to be corrected] Figure 3

[Correction method] Change

[Correction content]

[Figure 3]

[Procedure amendment 4]

[Document name to be corrected] Drawing

[Name of item to be corrected] Fig. 4

[Correction method] Change

[Correction content]

[Figure 4]

[Procedure Amendment 5]

[Document name to be corrected] Drawing

[Name of item to be corrected] Figure 5

[Correction method] Change

[Correction content]

[Figure 5]

[Procedure Amendment 6]

[Document name to be corrected] Drawing

[Name of item to be corrected] Figure 6

[Correction method] Change

[Correction content]

[Figure 6]

[Procedure Amendment 7]

[Document name to be corrected] Drawing

[Name of item to be corrected] Figure 7

[Correction method] Change

[Correction content]

[Figure 7]

[Procedure Amendment 8]

[Document name to be corrected] Drawing

[Correction target item name] Figure 8

[Correction method] Change

[Correction content]

[Figure 8]

Claims (12)

[Claims] 1. In a semiconductor device including a semiconductor element, a tab, an adhesive, a lead group, a wire, and a sealing resin for sealing them, which is an electrically effective lead group? Also, in a perspective view from the plane of the semiconductor device, it is arranged at a position not overlapping the semiconductor element, the circuit formation surface side of the semiconductor element is adhered to the tab using an adhesive,
The electrode pads in the circuit forming surface of the semiconductor element are electrically connected to appropriate leads by the wires, and the non-circuit forming surface of the semiconductor element and the surface of the tab where the semiconductor element does not exist. The semiconductor device is characterized in that both are sealed and molded so that there is a portion that does not come into contact with the sealing resin. 2. The portion of the semiconductor element in the non-circuit forming surface and the portion of the tab in the surface where the semiconductor element does not exist, which is not in contact with the sealing resin, are exposed to the outside air. A semiconductor device that makes direct contact. 3. The semiconductor device according to claim 1, wherein neither the adhesive nor the tab is present in the vicinity of and directly above the electrode pad of the semiconductor element. 4. The maximum height dimension of an arc formed by the one wire itself from the circuit forming surface of the semiconductor element is defined by the thickness of each of the adhesive and the tab. Semiconductor devices that are smaller than the total. 5. The non-circuit forming surface of the semiconductor element and any one of the sealing resin surfaces forming the outer shape of the semiconductor device are present in the same surface according to claim 1,
A semiconductor device in which the surface of the tab on which the semiconductor element does not exist and one of the sealing resin surfaces that form the outer shape of the semiconductor device exist in the same plane. 6. The semiconductor according to claim 1, wherein among the length dimensions of the respective portions that determine the planar shape of each of the semiconductor element and the tab, there are at least one portion where the values at the same portions are the same. apparatus. 7. The flat surface according to claim 1, wherein the flat surfaces of the tab and the lead after forming the semiconductor device are different from each other.
A semiconductor device existing in a plane. 8. The method according to claim 1, wherein a point on the circuit formation surface of the semiconductor element and a point on the surface of the tab facing the semiconductor element are a start point and an end point, and the gap is the sealing resin. A semiconductor device that has a certain straight line. 9. The semiconductor device according to claim 1, wherein an arc portion is present in the planar shape of the tab. 10. The semiconductor device according to claim 1, wherein a plurality of the tabs each having its own plane portion are present in the same plane. 11. The method according to claim 1, wherein the non-circuit forming surface of the semiconductor element and the surface of the tab on the side where the semiconductor element does not exist are not in contact with the sealing resin.
A semiconductor device having a resin body different from the sealing resin. 12. The semiconductor device according to claim 1, wherein a portion of the lead, which is in direct contact with the tab, near a connection portion with the tab is thinner than other portions of the lead.