JPH05324018A - Control circuit for pc - Google Patents

Abstract

PURPOSE:To increase the processing speed of the control circuit of the PC which executes sequence instructions. CONSTITUTION:A processor 1 reads two sequence instructions of the same address out of a memory 3 for a sequence program in one execution cycle at the same time, and reads data of two sequence instructions, reads in the last execution cycle out of a dual-port RAM 2 and processes them in the same execution cycle. Consequently, the reading and processing of two sequence instructions can be performed at the same time in one execution cycle.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a control circuit for a PC (programmable controller) that executes a sequence command, and more particularly to a control circuit for a PC that can simultaneously read and process a sequence command.

[0002]

2. Description of the Related Art Generally, when a sequence instruction is executed by a PC, data processing is performed in bit address units. Therefore, a processor dedicated to the PC is often used for the control circuit. The number of machines controlled by this PC is increasing year by year, and it is important to increase the processing speed.

As a method of increasing the processing speed, first, there is a method of shortening the reading time of the sequence instruction and the data operation time by using a memory for storing the sequence instruction and the operation data with a high access time. ..
There is also a method of widening the data width of the memory for storing the sequence instruction and shortening the read cycle of the instruction code and the operand.

However, the processing speed is limited only by these methods. Therefore, a method is generally used in which a memory bus for storing a sequence instruction and a memory bus for storing operation data are separated and coupled to a processor.

FIG. 4 is a block diagram showing a schematic configuration of a control circuit of a conventional PC in which buses of respective memories are separated and combined with a processor. The processor 21 is manufactured exclusively for a PC and processes data in bit address units. The processor 21 is coupled to the RAM 22 and the interface circuit 24 via the control signal line C1, the address bus A1, and the data bus D1. The processor 21 also includes a control signal line C2, an address bus A2,
And a sequence program memory 23 via a data bus D2.

Next, a procedure of executing a sequence instruction by the control circuit of such a conventional PC will be described. FIG. 5 is a diagram showing an example of a ladder program. Here, WA to WF are signal names. The code of this ladder program is as follows.

RD WA AND. NOT WB AND WC AND WD OR WE WRT WF The processor 21 sequentially executes this sequence program from the instruction number to.

FIG. 6 shows this ladder program in a conventional PC.
3 is a time chart showing a procedure when the control circuit of FIG. The processor 21 first reads the sequence instruction with the instruction number from the sequence program memory 23 within one execution cycle (F). Then, in the next execution cycle, the sequence instruction with the instruction number is executed (E), while the sequence instruction with the instruction number is read in (F). Here, the execution of the sequence instruction means that the processor 21 reads the data necessary for the sequence instruction from the RAM 22 and further processes it according to the instruction.

In this way, the same processing is repeated until the instruction number. As described above, in the conventional PC control circuit, the RAM 22 and the sequence program memory 23 are used.
By coupling and with the processor 21 via another bus, the processor 21 simultaneously reads the sequence instruction and executes it in one execution cycle.

[0010]

However, the control circuit of the conventional PC can handle only one sequence instruction for both reading and executing within one execution cycle. Therefore, the processing speed is limited.

Therefore, as a method for further increasing the speed,
The data width of the data bus D2 of the sequence program memory 23 is set to an integer multiple of the word length of the sequence instruction, and the processor 21 side is also provided with a corresponding data bus so that a plurality of sequence instructions can be simultaneously read and executed. There are possible ways to do it.

However, the data from the RAM 22 can be accessed only one by one, and the conventional processor 21 is not provided with the function of simultaneously performing the arithmetic processing of a plurality of data. For this reason, even if a plurality of sequence commands can be read at the same time, in actual calculation, only one data can be handled at a time. Particularly in the PC, most of the sequence instructions require access to the data memory, so if the data access time is the same as the conventional one, it is not possible to expect high speed.

The present invention has been made in view of the above points, and a PC capable of further increasing the processing speed.
It is an object of the present invention to provide a control circuit of.

[0014]

According to the present invention, in order to solve the above problems, in a control circuit of a PC (programmable controller) for executing a sequence instruction, a sequence program for storing a plurality of sequence instructions at the same address. The memory, the multi-port RAM in which the data is stored, the plurality of sequence instructions at the same address are simultaneously read in one execution cycle, and the data of the plurality of sequence instructions read in the previous execution cycle during the same execution cycle A processor for reading from a multiport RAM and processing the P.
A C control circuit is provided.

[0015]

In the processor, the plurality of sequence instructions having the same address are simultaneously read from the sequence program memory during one execution cycle, and the data of the plurality of sequence instructions read in the previous execution cycle during the same execution cycle are read from the multiport RAM. Read and process. As a result, a plurality of sequence instructions can be read and processed simultaneously in one execution cycle.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a schematic configuration of a control circuit of the PC of this embodiment. The control circuit of the PC of this embodiment is
Mainly PC dedicated processor 1, dual port RAM
2, a sequence program memory 3, and an interface circuit 4.

The dual port RAM 2 is a kind of RAM which is commercially available and has two ports P0 and P1 and can be simultaneously accessed from the two ports. The port P0 is coupled to the processor 1 via the control signal line CS1, the address bus AB1, and the data bus DB1. On the other hand, the port P1 is coupled to the processor 1 and the interface circuit 4 via the control signal line CS2, the address bus AB2, and the data bus DB2.

The sequence program memory 3 stores two sequence instructions at the same address.
When the processor 1 reads two sequence instructions simultaneously from the sequence program memory 3, the processor 1 reads the data handled by each sequence instruction simultaneously from the dual port RAM 2 in the next execution cycle. However, when reading two data, one data is read from the port P0 and the other data is read from the port P1.

When the sequence command read from the sequence program memory 3 is a write command, the processor 1 writes data in the dual port RAM 2 according to the command.

The processor 1 also writes data from a switch (not shown) or the like into the dual port RAM 2 via the interface circuit 4. Further, the processor 1 sends the data in the dual port RAM 2 to a relay (not shown) or the like via the interface circuit 4. Data is exchanged between the dual port RAM 2 and the interface circuit 4 by the port P1.

FIG. 2 is a block diagram showing the internal structure of the processor 1. The processor 1 has a control circuit 11
Is provided and controls the entire circuit in the processor 1. The control circuit 11 reads two sequence instructions stored in the same address for each execution cycle from the sequence program memory 3 via the data bus DB3.

The control circuit 11 decodes each sequence instruction read from the sequence program memory 3 and, in the next execution cycle, handles the data handled by each sequence instruction in each port P0 of the dual port RAM 2.
And read from P1. Here, reading of each data is executed by sending a read control signal to each control signal line CS1 and CS2 and sending address data to each address bus AB1 and AB2.

As a result, two data are simultaneously read from the dual port RAM 2 into the processor 1 via the data buses DB1 and DB2. In reading the two data, the earlier data is read from the data bus DB1 of the port P0, and the later data is read from the data bus DB2 of the port P1. The data read from the data bus DB1 is the multiplexer (M
UX) 12 and the data read from the data bus DB2 are sent to the multiplexer (MUX) 13, respectively.

When data is sent to each of the multiplexers 12 and 13, the control circuit 11 first sends a bit address selection signal to the multiplexer 12,
A bit address selection signal is sent to the multiplexer 13 after measuring an appropriate timing.

Further, the control circuit 11 decodes each sequence instruction read from the sequence program memory 3, and the arithmetic unit (ALU) 14 and the arithmetic unit (AL).
U) sends an operation command signal to each of the AND and OR operations. However, here, the calculation command signal is sent to the calculator 14 first.

The control circuit 11 further includes a data replacement circuit 17 when a sequence command read from the sequence program memory 3 has a write command.
Alternatively, a data write signal is sent to the data replacement circuit 18.

As described above, the control circuit 11 reads the next sequence command from the sequence program memory 3 while sending the operation command to each circuit. That is,
The control circuit 11 reads the sequence instruction in one execution cycle and, at the same time, executes the sequence instruction read in the previous execution cycle.

The multiplexer 12 has a data bus DB
For example, 16-bit data is input via 1. Upon receiving the bit address selection signal from the control circuit 11, the multiplexer 12 takes out only the bit data at the specified bit address and sends it to the arithmetic unit 14.

On the other hand, 16-bit data is also input to the multiplexer 13 via the data bus DB2. Upon receiving the bit address selection signal from the control circuit 11, the multiplexer 13 takes out only the bit data at the specified bit address and sends it to the calculator 15.

The arithmetic unit 14 receives the bit data sent from the multiplexer 12 and an accumulator (ACC), which will be described later, according to the arithmetic command signal from the control circuit 11.
The final calculation result data from 16 is calculated, and the calculation result data is sent to the calculator 15.

The computing unit 15 computes the bit data sent from the multiplexer 13 and the computing data sent from the computing unit 14 according to the computing command signal from the control circuit 11, and sends the final computing result data to the accumulator 16.

Upon receipt of the final operation result data, the accumulator 16 holds the value until new final operation result data is sent, and during that time, sends it to the operator 14, the data replacement circuit 17, and the data replacement circuit 18.

When the data write signal is sent from the control circuit 11, the data replacement circuit 17 synthesizes the final operation result data with other bits that are not operated and outputs it to the data bus DB1. That is, as the arithmetic processing processes one bit at a time, the other bits are read out as they are without arithmetic operation, and written to the corresponding address at the same time as the arithmetically processed bits. Similar processing is performed also in the data replacement circuit 18, and new data is transferred to the data bus DB.
2 is output.

Next, the sequence program execution procedure by the control circuit of the PC of this embodiment having such a processor 1 will be described. Here, the execution procedure will be described by taking the ladder program of FIG. 5 used in the description of the related art as an example.

The coding of the ladder program of FIG. 5 is as follows. RD WA AND. NOT WB AND WC AND WD OR WE WRT WF In these ladder programs, two sequence instructions are stored at one address in the sequence program memory 3. That is, the instruction number and the instruction number are stored in the same address, and the instruction number and the instruction number are stored in the same address.

FIG. 3 is a time chart showing the procedure for executing this ladder program by the control circuit of the PC of this embodiment. The processor 1 first reads a sequence instruction with an instruction number from the sequence program memory 3 within one execution cycle (F).
Then, in the next execution cycle, the sequence instruction with the instruction number and is executed (E), while the sequence instruction with the instruction number and is read in (F).
).

When the instruction number and the sequence instruction of are read, they are executed in the next execution cycle (E
), On the other hand, reads the sequence number and the sequence instruction of (F). Here, since the sequence instruction of the instruction number is a write instruction, only the sequence instruction of the instruction number is executed in the next execution cycle (E
). Then, the sequence instruction of the instruction number is executed in the execution cycle after executing the instruction number.

As described above, in this embodiment, the dual port RAM 2 is used as the data memory, two sequence instructions are stored in the same address in the sequence program memory 3, and the function of the processor 1 is as follows. Since two sequence instructions included in the same address are executed simultaneously in the next execution cycle, the processing speed can be increased.

In this embodiment, a multiport RAM is used.
Although the dual port RAM 2 is used as the above, the present invention can be implemented even with a RAM having three or more ports. That is, the sequence instruction in one address may be designed to be the same as the number of ports of the multiport RAM, and the number of processed data in one execution cycle of the processor 1 may be the same.

[0040]

As described above, according to the present invention, a single processor simultaneously reads and processes a plurality of sequence instructions in one execution cycle, so that the processing speed can be increased. ..

[Brief description of drawings]

FIG. 1 is a block diagram showing a schematic configuration of a control circuit of a PC of this embodiment.

FIG. 2 is a block diagram showing an internal configuration of a processor.

FIG. 3 is a time chart showing a procedure when a ladder program is executed by the control circuit of the PC of this embodiment.

FIG. 4 is a block diagram showing a schematic configuration of a control circuit of a conventional PC.

FIG. 5 is a diagram showing an example of a ladder program.

FIG. 6 is a time chart showing a procedure when a ladder program is executed by a control circuit of a conventional PC.

[Explanation of symbols]

 1 Processor 2 Dual Port RAM 3 Sequence Program Memory 4 Interface Circuit

Claims (2)

[Claims] 1. A control circuit of a PC (programmable controller) for executing a sequence instruction, a sequence program memory storing a plurality of sequence instructions at the same address, a multiport RAM storing data, and 1 execution. A processor for simultaneously reading the plurality of sequence instructions of the same address during a cycle, and reading the data of the plurality of sequence instructions read in the previous execution cycle during the same execution cycle from the multiport RAM for processing. Characteristic PC control circuit. 2. The processor has, inside the processor, an arithmetic unit having the same number as the plurality of sequence instructions of the same address and arranged to perform arithmetic operation serially according to the order of the sequence instructions. A control circuit for a PC according to claim 1.