JPH05328247A - Sub screen display circuit - Google Patents

Abstract

(57) [Summary] [Purpose] To prevent the "overtaking" phenomenon that occurs when the reading speed of child screen data is faster than the writing speed with a simple configuration, and to support multiple functions. [Structure] A memory 10 having a plurality of areas 1 to 4 for storing child screen data in field units is provided, and a plurality of stages of registers 81 to 84 for temporarily storing the area names of the respective areas are connected in cascade to write data. The completed area name is stored in the register 81 of the first stage, and the contents of each register are shifted each time the writing is completed, and the writing end pulse is selectively given to each of the above registers, and the writing end pulse is not given. The still image display data is derived from the area of the memory 10 corresponding to the contents, and the moving image display data is derived from the area of the memory 10 corresponding to the contents of the register to which the writing end pulse is applied.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sub-screen display circuit used in a multi-screen display video device in which a sub-screen is superimposed and displayed on a main screen.

[0002]

2. Description of the Related Art Conventionally, a child screen display circuit in a television receiver having a multi-screen display function has a memory for storing a picture signal of the child screen, but the writing speed and the reading speed to this memory are different. Therefore, a phenomenon called "overtaking" occurs.

FIG. 4 shows NTSC for both the parent screen and the child screen.
It shows a case where the video signal of the child screen is compressed to 1/9 of the area and is displayed on a part of the parent screen by the system signal. In this case, the video signal of the child screen is compressed to 1/9 and written in the memory 40, while it takes the most of the video signal of the effective image 41 of the child screen, whereas the video signal of the child screen is compressed in the memory 40. The written video signal of the child screen is quickly read out on the parent screen 42 in about 1/9 of the time.

Therefore, reading may overtake writing depending on the timing of reading from the memory 40, and in such a state, the latest data written in the memory 40 is switched to old data.
As a result, a disturbance occurs such that a boundary line appears on the screen when displaying a moving image or the like (the disturbance due to the interlace inversion shall be processed by another method).

Therefore, as shown in FIG. 5, memory areas 1, 2, 3, 4 for a plurality of screens (four fields in this example) are provided in a memory for writing a video signal of a child screen.
There is a method of controlling so as not to read from the memory area in which writing is being performed so that "overtaking" does not appear on one screen. In FIG. 5, (a) shows the legend of the figure. Each of the memory areas 1, 2, 3, shown in FIGS.
4 is adapted to record one field of the video signal, and the video signal A of each successive field of the small screen,
B, C, ..., J, K, ... Are sequentially written into the four memory areas 1, 2, 3, and 4 repeatedly over a time period of one field. Each of the above memory areas 1, 2,
The continuous 4-field video signals written in 3 and 4 are sequentially read over the time of 1/3 field.

FIG. 5B shows a case where the read cycle is slow, and there is no problem in the period of reading the video signals A, B, and C of each field from the memory areas 1, 2, and 3, but the video is read from the memory area 4. When trying to read the signal D, the above-mentioned "overtaking" phenomenon occurs during the reading period of the memory area 4. In order to avoid this, the occurrence of the "overtaking" phenomenon is monitored, and if the read cycle is slow as described above, the video signal D is written in the memory area 4 instead of being read, and the video signal D is written in the next memory area 1. The video signal E is read out. Therefore, the video signal of each field read from the memory is A, B, C, E, F, G, H, ... As shown in the lower part of FIG.

FIG. 5C shows a case where the read cycle is short, and a "passing" phenomenon occurs when the video signal G written in the memory area 3 is read. In this case, the occurrence of the "overtaking" phenomenon is monitored, and instead of reading the video signal G in the memory area 3, the video signal F written in the immediately preceding memory area 2 is read again. As a result, the video signal of each field read from the memory is C, D, E, as shown in the lower part of FIG.
F, F, G, H, I, J, K, ... As described above, the measures of "overtaking" were taken.

[0008]

In the above-mentioned conventional apparatus, the timing when the video signal of the sub-picture is written to the memory and read from the memory is constantly monitored, and it is detected that "overtaking" is likely to occur. Then, it is necessary to adjust the read time such as changing the read area of the memory, and as shown in FIG. 5, a plurality of memory areas for storing a number of consecutive fields of the video signal of the sub-screen are provided, and "overtaking" is performed. In order to reduce the frequency of occurrence of the phenomenon, there is a problem that read control becomes complicated, because it is necessary to change the switching method of the read area of the memory depending on the direction of "overtaking".

[0009]

In order to solve the above problems, the present invention comprises a plurality of storage areas for writing a compressed video signal of a sub-screen on a screen-by-screen basis. Memory means for selectively reading data for each storage area; first storage means for storing a storage area name of data for one screen last written in the memory means; The reading means for reading the child screen data from the storage area of the memory means corresponding to the storage area name stored in the first storage means is provided.

Further, a plurality of storage areas for writing the compressed video signal of the sub-screen in screen units are provided so that the data written in the storage areas can be selectively read out for each storage area simultaneously with the writing. Memory means,
Each storage area name of the memory means is temporarily stored in a plurality of registers connected in cascade, and the storage area name newly written by the writing end pulse of the data for one screen to the memory means is stored in the register of the first stage. And reading out the sub-screen data from the storage area name storage means for shifting the contents of the temporarily stored register and the storage area of the memory means corresponding to the storage area name written in the first stage register. And a writing means for writing the data of the next child screen in the storage area of the memory means corresponding to the storage area name written in the cascade-connected final stage register. A control means for selectively stopping the supply of the write end pulse is provided in a predetermined register of the plurality of registers, and the write end is completed. The data of the sub-screen is read from the storage area of the above-mentioned memory means corresponding to the storage area name written in the register in which the supply of the noise has been stopped, and the still picture is displayed on the sub-screen. , Second reading means for reading the data of the child screen from the storage area of the memory means corresponding to the storage area name written in the frontmost register, and the last-stage register among the remaining plurality of registers. A second writing means for writing the data of the next child screen is provided in the storage area of the memory means corresponding to the written storage area name.

[0011]

According to the above construction, the storage area name read from the first storage means is always the area in which the last screen data written in the memory means is stored.
No. 1 whether the read timing is early or late
By reading the data from the storage area of the memory means corresponding to the storage area name read from the storage means by the reading means, it is possible to automatically derive the child screen data for which the "overtaking" measure is taken.

Further, since the storage area name of the oldest one screen data among the screen data written in the memory means is stored in the second storage means, it is read from the second storage means. When new small screen data is written in the storage area of the memory means corresponding to the storage area name, the plural pieces of small screen data written in the memory means are sequentially rewritten from the oldest one.

On the other hand, the supply of the write end pulse is selectively supplied by the control means to a part of the register of the plurality of stages in which the storage area name of the memory means for storing the data of the plurality of screens of the child screen is written by the write end pulse. If you try to stop
It is possible to derive the still image of the small screen from the storage area of the memory means corresponding to the storage area name stored in the register in which the supply of the write end pulse is stopped. Further, from the remaining registers to which the write end pulse is supplied, it is possible to derive a moving picture of the sub-screen on which the "overtaking" measure is taken from the memory means corresponding to the area name written in the register at the front stage. By providing two sub-screens, the sub-screens of moving images and still images can be simultaneously displayed on the main screen. In this case, the new data of the child screen is written in the area of the memory means corresponding to the area name written in the last-stage register to which the write end pulse is supplied, so that the oldest data in the moving image storage area is sequentially updated. The screen data is written.

[0014]

FIG. 1 is a block diagram of an embodiment of the present invention. In FIG. 1, reference numeral 10 is provided with storage areas 1, 2, 3, 4 for four fields for storing the data of the picture signal of the sub-picture supplied from the terminal T _{1 in} units of fields by a control signal from the memory control circuit 5. The video signals of the child screen for four fields written in the respective storage areas 1, 2, 3, 4 of the memory 10 are the above-mentioned memory control circuit 5.
It is designed to be read out to the output terminal T ₂ in a field unit by a control signal from.

Reference numerals 81, 82, 83, 84 are registers for storing the area names of the respective storage areas 1, 2, 3, 4 of the memory 10 as binary addresses such as 00, 01, 10, 11, etc. , Each register 81, 82, 83, 84
Is provided with a latch, and these registers 81, 82,
83 and 84 are sequentially connected in series. Reference numeral 6 denotes a write address generation circuit. When the write address generation circuit 6 is used to display a moving image in 2 fields, the area name data of the memory 10 from the register 82 and a moving image display in 4 fields are performed. The data of the area name of the memory 10 is input from the register 84 used for.

Further, the write address generating circuit 6 gives a signal for designating the address of the memory 10 into which the picture signal of the child screen is written to the memory control circuit 5 and writes when the writing to the memory 10 is completed. The end area name is written in the register 81.

Reference numeral 7 denotes a read address generation circuit. The read address generation circuit 7 uses the register 81 used for displaying a moving image and the area name data of the memory 10 and the register used for displaying a still image. Data of each area name of the memory 10 from 83 and 84 is input, and the read address generating circuit 7 outputs a control signal for designating the read address of the memory 10 to the memory control circuit 5. Further, the memory control circuit 5 includes the registers 81, 82, 83,
A write end pulse is selectively supplied to each 84.

Since the embodiment of the present invention has the above-mentioned structure, the area name of the memory 10 in which the video signal of the sub-picture supplied from the terminal T ₁ is written in the latches corresponding to the registers 81, 82, 83, 84. Is the address 00, 01, 10, 11
The value of the area name of the memory 10 for which writing has been completed is taken in by a writing end pulse from the memory control circuit 5 at the same time as the area held in the registers 81 to 84. The name is shifted to each register in the next stage.

Now, when data is written in the storage area 1 whose address is 00 in the memory 10 and the writing is completed, the write address generating circuit 6 outputs the address 00 which is the above-mentioned write end area name. The contents of the register 81 are given to the register 81 and taken in by the write end pulse from the memory control circuit 5, and at the same time, the contents of the register 81 are shifted to the register 82 of the next stage.

Normal moving image display is performed using all four fields in order to reduce the frequency of occurrence of "overtaking". FIG. 2 is a diagram for explaining the write and read operations in this case. Each storage area 1, 2, of the memory 10
2A shows continuous fields A, B, C, ..., K of the picture signal of the sub-screen supplied from the terminal T ₁ by the control signal from the memory control circuit 5. As described above, the write contents of the respective storage areas 1, 2, 3, 4 are sequentially updated so that the last written data for one field is stored.

When successive fields of the sub-picture video signal are sequentially written in the storage areas 1, 2, 3, 4 of the memory 10 one by one, the memory control circuit 5 registers each time the writing operation is completed. 81, 82, 8
3, the write end pulse a or b is shown in FIG.
A write end area name (1, 2, ...) Is given as shown in (b) and is the area name of the memory 10 in which the write address generation circuit 6 has finished writing to the register 81 at the first stage.
3, 4, etc.) are applied and held as shown in FIG. 2 (b).

That is, each storage area 1, 2,
3 and 4 are consecutive fields A of the sub-picture video signal,
When B, C, ..., K, ... are stored, the address names of the above storage areas are sequentially stored in the first-stage register 81 as 1 → 2 → 3.
→ 4 → 1 → 2 → ... is retained, and when the latest writing area in the register 81 is, for example, the area 4, the content of the register 81 also becomes 4, etc. The address of the most recently written storage area is held.

Then, the writing of the next field is performed in the storage area of the memory 10 corresponding to the storage area name held in the final stage register 84. That is, the storage area name derived from the register 84 is given to the write address generation circuit 6 and further derived as a control signal of the memory 10 via the memory control circuit 5, and written in the register 84 by this control signal. Writing is performed to the address of the memory 10 corresponding to the existing address. As a result, rewriting is performed from the storage area of the memory 10 in which the oldest data is written in the continuous 4 fields.

Data reading of each field written in each storage area 1, 2, 3, 4 of the memory 10 is performed for the address held in the register 81 of the first stage. That is, the address data for displaying a moving image is taken out from the register 81, is given to the read address generating circuit 7, and a control signal is supplied to the memory 10 via the memory control circuit 5 so that the address held in the register 81 is obtained. The data is taken out from the storage area of the memory 10 corresponding to, and the video signal for the child screen is derived at the output terminal T ₂ .

In this case, since the address held in the register 81 at the first stage is the address of the storage area of the memory 10 in which the writing is completed immediately before the timing of reading, the reading timing is as shown in FIG. As shown in c) or (d), even if it is late or early, the "overtaking" measure is automatically taken, and the "overtaking" phenomenon can be prevented.

That is, when the read timing is late as shown in FIG. 2C, the fields C → D → E of the sub-picture video signal are sequentially read from the storage area 3 → 4 → 1 and then the register 81 in the first stage is read. The read timing does not come while the address of the storage area 2 is held. Therefore, storage area 2
The frame F written in the memory area is not read, and the next read timing is when the storage area 3 is held in the register 81. Therefore, the field G written in the storage area 3 is read and the same applies to the frame H. , I, J are read. Therefore, the frame F written in the storage area 2 is skipped, and as shown in FIG. 2C, C → D → E → G →
Each frame of H → I → J ... is sequentially read.

When the read timing is early as shown in FIG. 2 (d), after the fields C → D → E of the sub-picture video signal are sequentially read from the storage areas 3 → 4 → 1, the first stage register 81 is still in place. Since the read timing comes again while the address of the storage area 1 is held, the field E is read again at this timing. Then, at the next read timing, the address held in the register 81 of the first stage is 2 →
Since it is 3 → 4 → 1 → 2, the fields F → G → H → I → J written in the memory 10 are sequentially read. Therefore, when such a read timing is early, the same field written in the same area such as the storage area 1 is read twice, and C → D → E → as shown in FIG.
Each frame of E->F->G->H->I-> J ... Is sequentially read.

The data for each field read from the memory 10 as described above and provided with the measure of "passing" is derived from the output terminal T _{2 and} is used as a sub-picture image signal in the sub-picture area 43 of FIG. Displayed in.

Next, a description will be given of an embodiment in which the circuit shown in FIG. 1 is adapted to the multi-functionalization while taking the above-mentioned measure of "passing" of the sub-screen. This embodiment has a plurality of child screens such as two screens in the parent screen, and one child screen has two child screens.
Still images are displayed in the field, and moving images are simultaneously displayed in the remaining two fields on the other sub-screen.

FIG. 3 is a diagram for explaining the operation. The region X is for displaying a moving image using 4 fields, as in the case of the above embodiment shown in FIG. 2, and the region Y is 2 fields. This is a case where a moving image is displayed on one of the child screens and a still image is displayed on the other child screen in the remaining two fields.

In the case of the normal display in which the moving image is displayed by using the four fields shown in the area X, all the registers 8 as shown in FIGS.
A write end pulse a or b is given to 1, 82, 83, 84 to transmit the storage area name to be written in the memory 10 to the final stage register 84, and the next write is held in the final stage register 84. The data is read from the storage area and read from the register 81 at the first stage to sequentially display the C → D → E fields as shown in FIG.

When the moving picture and the still picture shown in the area Y are simultaneously displayed on the respective child screens, a pulse for requesting the still picture display is first inputted from the outside, and this pulse causes the register 83 as shown in FIG. 3 (c). , 84 to stop writing of new information in the storage area of the memory 10 held in the registers 83, 84.

Then, the data corresponding to the storage areas 4 and 3 shown in FIG. 3C held in the registers 83 and 84 is taken out from the registers 83 and 84, and the read address generating circuit 7 and the memory control circuit 5 are taken out. 3 from the storage areas 4 and 3 of the memory 10 by a memory control signal obtained via
Data of fields D and C as shown in (e) are taken out alternately and a frame still image display is realized on one of the child screens.

During this time, the registers 81 and 82 are set in FIG.
As shown in (b), the write end pulse a is continuously given,
The display is the memory 10 corresponding to the area name indicated by the register 81.
Of the memory area 2 → 1 → 2 → 1 ..., which is taken out as a moving image display by the fields F → G → H → I ..., and the writing is performed by the register 82 as indicated by a circle in FIG. Storage area 1 of the memory 10 corresponding to the area name indicated by
It is performed for 2 → 1.

In this case, the moving image display is performed only by switching the two storage areas of the memory 10, so that "overtaking" is performed.
Although it is expected that the frequency will increase, it is possible to easily realize simultaneous display of still images and moving images. To return the above-mentioned state of simultaneously displaying a still image and a moving image to the state of displaying only a moving image by the original 4 fields, all registers 8 again
A write end pulse may be given to 1, 82, 83 and 84 to write in the area indicated by the register 84.

In a system having 3 areas, 2
If the data of the third area is continuously updated while the frame still image is displayed in the area, the transition to the next moving image can be smoothly performed.

[0037]

Since the present invention has the above-described configuration, "passing" occurs because the writing speed to the memory is slower than the reading speed from the memory in the sub-screen display circuit.
Can be prevented by a simple circuit configuration using a plurality of stages of registers and can be adapted to multiple functions, so that it is possible to provide a child screen display circuit of extremely high practical value.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a first operation explanatory diagram of FIG.

FIG. 3 is a second operation explanatory diagram of FIG. 1.

FIG. 4 is a conceptual diagram of signal processing of child screen display in a multi-screen display television receiver.

FIG. 5 is an operation explanatory view of a conventional example.

[Explanation of symbols]

 1, 2, 3, 4 Storage area 5 Memory control circuit 6 Write address generation circuit 7 Read address generation circuit 10 Memory 81, 82, 83, 84 Register

Claims (2)

[Claims] 1. A plurality of storage areas for writing a compressed video signal of a sub-screen on a screen-by-screen basis are provided, and data written in the storage areas can be selectively read out for each storage area simultaneously with writing. Corresponding to the storage area name stored in the first storage means, the first storage means for storing the storage area name of the data for one screen last written in the memory means, A child screen display circuit comprising: a reading means for reading the child screen data from the storage area of the memory means. 2. A plurality of storage areas for writing the compressed video signal of the sub-screen on a screen-by-screen basis are provided, and the data written in the storage areas can be selectively read out for each storage area simultaneously with the writing. The memory means and the storage area name of the memory means are temporarily stored in a plurality of registers connected in cascade, and the storage area name newly written by the writing end pulse of the data for one screen to the memory means. Is stored in the register at the first stage, and storage means of the storage area name for shifting the contents of the temporarily stored register, and a storage area of the memory means corresponding to the storage area name written in the register at the first stage Read-out means for reading out the screen data, and the memory means corresponding to the storage area name written in the cascade-connected final stage register In a sub-screen display circuit having a writing means for writing the data of the next sub-screen in the storage area, a control means for selectively stopping the supply of the write end pulse to a predetermined register of the plurality of registers is provided. Provided,
The data of the sub-screen is read from the storage area of the memory means corresponding to the storage area name written in the register in which the supply of the write end pulse is stopped, and the still image of the sub-screen is displayed and the remaining plural Second reading means for reading the data of the child screen from the storage area of the memory means corresponding to the storage area name written in the frontmost register among the registers, and the remaining plurality of registers,
A second screen writing circuit for writing the data of the next small screen to the storage area of the memory means corresponding to the storage area name written in the last-stage register, the small screen display circuit.