JPH05335330A - Connection hole embedding method - Google Patents

Abstract

(57) [Summary] [Object] To provide a method for forming a buried contact hole, which has barrier properties and good embedding properties for an electrode material such as aluminum. A method of embedding a wiring material in a connection hole 15 formed by patterning an interlayer insulating film formed on the entire upper surface of a silicon substrate 1, wherein the interlayer insulating film is patterned to form a connection hole. After forming 15, the step of depositing a metal for forming a silicide in the contact hole 15 at a temperature at which the silicon substrate 1 and the metal for forming the silicide react with each other.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of filling a fine connection hole.

[0002]

2. Description of the Related Art In recent years, as the integration density of memory devices has increased, the devices have become finer. For this reason, due to the miniaturization of the contact holes, it is becoming more difficult to embed metal in the contact holes.

In order to enable connection with an element, it is necessary to embed a wiring material such as aluminum (Al) used as wiring. As a method thereof, attention has recently been paid to a technique of embedding Al by high temperature sputtering. The method is
A silicon (Si) substrate is heated to a high temperature of several hundred degrees A
This is a technique in which Al alloy is reflowed, Al is filled in the connection hole and flattened by forming an alloy film by sputtering. In this case, A such as Ti is used as the base of Al.
If a material that easily reacts with 1 is used, Al during film formation and the base T
It is known that the progress of the interfacial reaction with i improves the wettability between the two and makes it possible to perform good embedding with Al spread.

To embed Al in the connection hole, Al
It is required to have good burying characteristics between the underlayer and the underlayer, and to prevent Al from penetrating into the silicon substrate.

In response to these requirements, the Al film forming structure as described below has been conventionally used.

(1) Al film formation structure is Al / TiON /
Ti These three layers are continuously formed in a vacuum by a single mode multi-chamber sputtering apparatus.

(2) Al film formation structure is Al / Ti / Ti
ON / Ti (3) Al film formation structure is Al / Ti / TiN / Ti (4) SALICIDE (Self
SIOX (Silicidation through oxicide) -Ti
After forming Si ₂ , an interlayer insulating film and a connection hole are formed on the upper layer thereof, and Al is formed.

The case (4) of these conventional techniques for burying connection holes will be described below by taking the manufacturing of a MOS transistor as an example.

9 and 10 are sectional views of the MOS transistor manufacturing process.

The steps will be described below in order.

(1) As shown in FIG. 9A, a field oxide film 2 for element isolation is formed on a silicon substrate 1.

(2) When gate oxidation is performed to deposit polycrystalline silicon and WSi ₂ and patterning is performed, FIG.
Gate oxide film 4 and gate electrode 3 are formed as shown in FIG. Next, LDD (Lightly doped drain) ion implantation is performed to form an LDD diffusion layer 5.

(3) After forming an oxide film on the entire surface of the silicon substrate 1, the entire surface is etched back to form sidewalls 18 as shown in FIG. 9 (c).

Next, in order to form source / drain regions, ion implantation 6 is performed on the entire surface of the silicon substrate 1 as shown in FIG. 9C, and a diffusion layer 8 is formed as shown in FIG. 10A. ..

(4) A thin oxide film is formed on the entire surface of the silicon substrate 1.

Next, after depositing Ti on the entire surface, SITO X-TiSi ₂ 21 is formed on the source and drain regions by heat treatment as shown in FIG. 10 (a).

Next, the unreacted Ti on the oxide film is selectively etched.

(5) An interlayer insulating film is formed on the entire upper surface of the silicon substrate 1, resist patterning is performed, and dry etching is performed to form the interlayer insulating film 7 as shown in FIG. 10B.
a and the connection hole 15 are formed.

(6) After depositing Ti 13 on the entire surface, A
l is formed on the entire surface.

Next, resist patterning is performed and dry etching is performed to form an Al wiring 1 as shown in FIG.
Form 2.

[0021]

However, there are the following problems in any of the conventional connection hole embedding techniques described above.

(1) Al film formation structure is Al / TiON /
In the case of Ti, Al and TiON do not easily react with each other, the wettability of both is poor, and the embedding characteristics of Al are extremely deteriorated.

(2) Al film formation structure is Al / Ti / Ti
In the case of ON / Ti The burying property is improved as compared with the case (1) in which Al directly contacts the TiON, but not so much as in the case of the Ti single layer. This is because oxygen in TiON diffuses into the upper Ti film when the silicon substrate is heated to several hundred degrees during Al film formation.
This is because this oxygen reaches the surface, the Ti in this portion is oxidized, the reaction with Al deteriorates, and the embedding characteristics deteriorate.

(3) Al film formation structure is Al / Ti / Ti
In the case of N / Ti If TiN is used as a barrier metal for Al instead of TiON, the problem of defective embedding can be solved, but TiN has an insufficient Al barrier property compared to TiON, so high temperature sputtering or Al sintering, etc. Through the above heating process, penetration of Al occurs.

(4) SALIC on the entire surface of the source / drain
In order to form SITOX-TiSi ₂ 21 by IDE,
As shown in FIG. 10A, this SITOX-TiSi
₂ 21 will be in contact with the field oxide film 2. However, TiSi ₂ has a tensile stress, which induces a crystal defect in the silicon substrate 1 at the edge of the field oxide film 2 and causes a junction leak in the silicon diffusion layer to increase by one digit as compared with a normal case.

Therefore, an object of the present invention is to provide a method of forming a contact hole embedded in an electrode material such as aluminum which has barrier properties and good burying properties.

[0027]

According to the present invention, there is provided a connection hole embedding forming method for embedding a wiring material in a connection hole formed by patterning an interlayer insulating film formed on the entire upper surface of a silicon substrate. After patterning the interlayer insulating film to form a connection hole, a metal for forming a silicide in the connection hole is deposited at a temperature at which the silicon substrate and the metal for forming the silicide react with each other. A contact hole embedding forming method is characterized by including the step of:

Further, according to the present invention, the above-mentioned problems are preferably solved by a method for forming a buried contact hole, wherein the metal is a transition metal. Furthermore, the transition metal is preferably cobalt, which is preferably solved by the embedding forming method.

Further, according to the present invention, there is provided a method of embedding a connection hole in which a wiring material is embedded in a connection hole formed by patterning an interlayer insulating film formed on the entire upper surface of a silicon substrate. Patterning the insulating film to form a contact hole, and then depositing a metal for forming a silicide in the contact hole at a temperature at which the silicon substrate and the metal for forming the silicide react with each other; A step of removing a metal that has not reacted with the silicon substrate, a step of performing a high temperature heat treatment for stabilizing a reaction material of the metal and the silicon substrate, and a metal for forming the silicide in the connection hole. And a step of depositing at a temperature at which the silicon substrate and a metal for forming a silicide react with each other. It is solved Te.

Further, according to the present invention, the above-mentioned problem is a method for embedding a connection hole, in which a wiring material is embedded in a connection hole formed by patterning an interlayer insulating film formed on the entire upper surface of a silicon substrate. After forming a connection hole by patterning the insulating film, a step of forming a thin oxide film in the connection hole, a metal for forming a silicide in the connection hole, a metal for forming the silicon substrate and the silicide A contact hole embedding formation method is characterized by including a step of depositing at a temperature at which a metal reacts.

Further, according to the present invention, the above-mentioned problem is that the oxide film is a silicon oxide film or a silicon oxynitride film, the thickness thereof is 10 nm or less, and the metal for forming the silicide is titanium, and the connection hole is formed. This is preferably solved by a method for forming a buried contact hole, which is characterized in that the temperature at which the metal is deposited is 600 ° C. or higher.

Further, according to the present invention, there is provided a method of embedding a connection hole in which a wiring material is embedded in a connection hole formed by patterning an interlayer insulating film formed on the entire upper surface of a silicon substrate. Patterning the insulating film to form a contact hole, and then depositing a metal for forming a silicide in the contact hole at a temperature that reacts with the silicon substrate and the metal for forming the silicide. This is solved by the method of forming a buried contact hole.

[0033]

According to the present invention, as shown in FIG. 8, after the interlayer insulating film is patterned to form the connection hole 15, the silicon substrate 1 and the metal for forming the silicide are deposited in the connection hole 15. By carrying out the reaction at a temperature at which this metal reacts with the silicon substrate 1, metal atoms are converted into silicon (Si).
In order to react with Si, it actively diffuses in the silicon direction and reacts with Si to form a silicide. As a result, a flat surface is formed on the metal deposition surface by the diffusion of the metal atoms, and the coverage with the silicon substrate 1 in the connection hole 15 can be improved.
Moreover, since the silicide is formed only in the contact hole 15, it is possible to prevent crystal defects of silicon at the edge portion of the field oxide film.

Further, according to the present invention, when the above-mentioned metal is a transition metal, this transition metal becomes main atoms (move spieces) that diffuse because it reacts with silicon, so that the transition metal diffuses in the connection hole 15. Becomes more active, and the metal deposition surface in the connection hole 15 can be suitably flattened.

Further, according to the present invention, as shown in FIG. 4B, when a metal is deposited in the connection hole 15 at a temperature at which the silicon substrate 1 reacts with the metal, the reaction between the silicon substrate 1 and the metal. Since the unreacted metal is deposited on the upper layer of the substance (silicide), only the unreacted metal can be selectively removed. As a result, the deposition surface of the connection hole 15 can be made flatter. Further, the silicide can be stabilized by further performing a high temperature treatment after removing only the unreacted metal.

Further, by depositing the metal on the flat silicide in the contact hole 15 at a temperature at which it reacts with the silicon substrate 1, the deposited metal actively diffuses and reacts with silicon. Can be flattened.

According to the present invention, after the thin oxide film 9 is formed in the connection hole 15 as shown in FIG. 2C, the metal in the connection hole 15 reacts with the silicon substrate 1 and the metal. By depositing at a temperature, SIOX (Silicidation through oxime), which is a reaction material with oxide film, metal, and silicon
cide) -silicide can be formed. This reaction material has a barrier property when forming an electrode such as aluminum,
Moreover, a suitable electrode base having a low sheet resistance is formed.

According to the present invention, the thin oxide film is a silicon oxide film or a silicon oxynitride film, and the deposited metal is titanium (Ti).
-TiSi ₂ is formed. This SITO X-TiSi ₂
Has a low sheet resistance of 10Ω or less, and is 500 ° C.
It has a barrier property against aluminum up to the temperature of and forms a suitable base material for electrodes.

Further, according to the present invention, as shown in FIG. 5B, after the silicon nitride film (SiN) 14 is formed on the surface of the contact hole 15, the metal is deposited in the contact hole 15 with the silicon substrate 1. When the process is carried out at a temperature at which the metal reacts, the oxidation of the metal is reduced because the silicon nitride film 14 is interposed between the metal and the interlayer insulating film 7a, which is the silicon oxide film, on the side wall of the connection hole. It can be done. As a result, it is possible to improve the burying property with the electrode such as aluminum.

[0040]

Embodiments of the present invention will be described in detail below with reference to the drawings.

1 to 3 are sectional views of a MOS transistor manufacturing process showing a first embodiment according to the present invention.

The first embodiment will be described below in the order of steps.

(1) As shown in FIG. 1A, a field oxide film 2 for element isolation is formed on a silicon substrate 1.

(2) Oxidation for the gate is performed. Condition gas H ₂ / O ₂ = 6/4 liter / min, temperature 8
Polycrystalline silicon is deposited on the entire surface at 50 ° C. and a film thickness of 16 nm. Condition gas SiH ₄ / PH ₃ / H ₂ = 500 / 0.35
/ 50 sccm, temperature 580 ° C., pressure 79.8 Pa,
Film thickness 200 nm Next, WSi ₂ is deposited on the entire surface. Conditions WF ₆ / SiH ₄ / He = 10/1000/360
sccm, temperature 360 ° C, pressure 26.6Pa, film thickness
100 nm Next, resist patterning is performed and a gate wiring portion is formed by dry etching. Condition gas C ₂ Cl ₃ F ₃ / SF ₆ = 65/5 sccm,
Pressure 1.33Pa, Microwave power 100W, RF
Power 100W In this way, as shown in FIG. 1B, the gate oxide film 4,
The gate electrode 3 is formed.

Next, LDD ions (As or BF ₂ ) are implanted to form the LDD diffusion layer 5.

(3) After forming an oxide film on the entire surface of the silicon substrate 1, the entire surface is etched back to form sidewalls 18 as shown in FIG. 1 (c).

Next, in order to form source / drain regions, ion implantation 6 is performed on the entire surface of the silicon substrate 1 as shown in FIG. 1C, and a diffusion layer 8 is formed as shown in FIG. 2A. .. In the case of NMOS, As 50 KeV, 5e15 / cm ² ,
In the case of PMOS, BF _{2 20} KeV, 3e15 / cm ²
Perform under the conditions of.

(4) As shown in FIG. 2A, an interlayer insulating film 7 is formed on the entire surface of the silicon substrate 1. Conditions Gas flow rate SiH ₄ / O ₂ / N ₂ = 250/250
/ 100sccm, temperature 420 ° C, pressure 13.3P
a, film thickness 500 nm and activation annealing at 1100 ° C. for 10 seconds.

(5) Resist patterning is performed, and patterning is performed by dry etching to form connection holes 15 as shown in FIG. 2 (b). Condition gas C ₄ F ₈ = 50 sccm, RF power 120
0W, pressure 2Pa

(6) Thin oxide film 9 as shown in FIG. 2 (c)
To form. Condition gas H ₂ O / O ₂ = 1.5 / 6 1 / min,
Temperature 850 ℃, film thickness 3nm

(7) As shown in FIG. 3A, Ti10 is formed on the entire surface of the silicon substrate 1. At this time, silicon substrate 1
Increase the temperature to about 600 ° C. Example of Ti sputtering conditions Ar = 40 sccm, pressure 0.
04 Pa, sputtering power 1 kW, film thickness 30 nm As a result, the metal atoms to be sputtered react with the underlying Si one after another and diffuse into the connection hole 15. Since the atoms flow into the connection holes 15, the coverage of Ti10 does not have an overhang shape and can be uniformly formed in the connection holes 15.

Further, since Ti 10 in contact with Si in the contact hole 15 forms a silicide, the contact hole 15 is formed.
The sheet resistance inside is kept as low as 10Ω or less. The contact resistance with the Al wiring after that also becomes a low resistance of 10Ω or less. Further formed silicide is SITOX-TiSi.
Since ₂ 11, with a barrier against Al to a temperature of 500 ° C..

(8) Al is formed on the entire surface of the silicon substrate 1. Conditions Ar flow rate 40 sccm, pressure 0.04 Pa,
Sputtering power DC 1 kW, film thickness 500 nm Next, resist patterning is performed, and the above Al dry etching is performed. As shown in FIG.
Form 2. As an example of conditions, an RF applied type ECR etcher is used, gas flow rate BCl ₃ / Cl ₂ = 60/90 sccm, microwave power 100 W, RF power 50 W, pressure 21.3 P
a Through the above steps, the MOS transistor according to the first embodiment is manufactured.

FIG. 4 is a sectional view of the second half of the MOS transistor manufacturing process showing the second embodiment.

This embodiment is shown in FIG. 3A shown in the first embodiment.
In the step of, the unreacted Ti during the formation of SITOX-TiSi ₂ is selectively removed. Then stable TiS
A high temperature anneal at about 900 ° C. is performed to form i ₂ . Then, Ti is newly deposited to embed the Al wiring. The process will be described below.

In this embodiment, first, the interlayer insulating film is patterned on the silicon substrate 1 through the steps (1) to (6) shown in the first embodiment, and the contact hole 15 and the surface of this contact hole 15 are thinly oxidized. Form a film.

(7) As shown in FIG. 4A, Ti10 is formed on the entire surface of the silicon substrate 1. At this time, silicon substrate 1
Increase the temperature to about 600 ° C. Example of Ti sputtering conditions Ar = 40 sccm, pressure 0.
04Pa, RF bias 50W, Sputter power 1K
W, film thickness 30 nm As a result, the metal atoms sputtered diffuse into the connection hole 15 because they react with the underlying Si one after another. Since the atoms flow into the connection hole 15, Ti atoms can be uniformly supplied to the lower portion of the connection hole 15. As a result, T with stable film thickness
i-silicide can be formed.

(8) As shown in FIG. 4B, the interlayer insulating film 7
a and unreacted Ti on SITO X-TiSi ₂ 11
10 is selectively etched. Example of condition Immerse in a NH ₄ OH: H ₂ O ₂ : H ₂ O = 1: 2: 2 solution for 10 minutes.

Next, heat treatment is performed at 900 ° C. for about 30 seconds in order to form stable TiSi ₂ .

Since the silicide is formed in the connection hole 15, the sheet resistance in the connection hole 15 maintains a low resistance of 10Ω or less. Contact resistance with Al wiring after that is also 10Ω
It has the following low resistance. The silicide to be formed is SI
Since in TOX-TiSi ₂ 11, with a barrier against Al to a temperature of 500 ° C..

(9) As shown in FIG. 4C, Ti 13 is formed on the entire surface. In this case also, TiSi formed beforehand
_In order to gain coverage of Ti by reacting Ti and Si through ₂ , the deposition is performed while heating at about 600 ° C. at the time of forming the Ti. Example of Ti sputtering conditions Ar = 40 sccm, pressure 0.
04Pa, RF bias 50W, Sputter power 1K
W, film thickness 30 nm Next, Al is formed on the entire surface of the silicon substrate 1. Condition example Ar flow rate 40 sccm, pressure 0.04 Pa,
Sputtering power DC 1 kW, film thickness 500 nm Next, resist patterning is performed, and the above Al dry etching is performed to perform Al wiring 12 as shown in FIG.
To form. As an example of conditions, an RF applied type ECR etcher is used, gas flow rate BCl ₃ / Cl ₂ = 60/90 scc
m, microwave power 1000W, RF power 50
W, pressure 21.3 Pa Through the above steps, the MOS transistor according to the second embodiment is manufactured.

Next, FIG. 5 and FIG. 6 show M showing a third embodiment.
FIG. 7 is a sectional view of a latter half step of manufacturing an OS transistor.

In this embodiment, Si is formed on the SiO ₂ on the side of the connection hole.
By forming N, it is a method of suppressing the oxidation of Ti to be formed thereafter. The steps of this example will be described below.

In this embodiment, first, through the steps (1) to (5) shown in the first embodiment, the interlayer insulating film is patterned on the silicon substrate 1 to form the connection hole 15.

(6) As shown in FIG. 5 (a), SiN14
Are formed on the entire surface. Condition example Gas SiH ₄ / NH ₃ / N ₂ = 180/500 /
720 sccm, temperature 250 ° C., pressure 40 Pa, film thickness 100 nm

(7) As shown in FIG. 5B, SiN 14 is etched back to form SiN 14a on the side wall of the interlayer film 7a. Condition example Gas CHF ₃ = 50 sccm, RF power 1
50 W, pressure 2 Pa Condition example Ar flow rate 40 sccm, pressure 0.04 Pa,
Sputtering power DC 1kW, film thickness 500nm

(8) As shown in FIG. 5C, unreacted Ti is selectively etched. Example of condition Immerse in a NH ₄ OH: H ₂ O ₂ : H ₂ O = 1: 2: 2 solution for 10 minutes.

Then, heat treatment is performed at 900 ° C. for about 30 seconds to form stable TiSi ₂ .

(9) Ti13 is deposited as shown in FIG. Also in this case, since Ti and Si are reacted with each other through TiSi ₂ formed in advance to obtain coverage of Ti, deposition is performed while heating at about 600 ° C. during Ti film formation. Example of Ti sputtering conditions Ar = 40 sccm, pressure 0.
04Pa, RF bias 50W, Sputter power 1K
W, film thickness 30 nm Next, Al is formed on the entire surface.

Next, resist patterning is performed, and then the metal wiring film is dry-etched to form Al wirings 12 and transistors are formed. Examples of conditions are RF applied ECR
Use etcher, gas flow rate BCl ₃ / Cl ₂ = 60 /
90 sccm, microwave power 1000 W, RF power 50 W, pressure 21.3 Pa Through the above steps, the MOS transistor according to the present embodiment is manufactured.

Next, FIG. 7 is a sectional view of a MOS transistor manufacturing latter half process showing the fourth embodiment according to the present invention.

This example shows a case where the main diffusing atoms (move spieces) for reacting with Si are metals.
(In the case of Ti, move speices are Si.) In order to positively improve the coverage in the connection hole, it is necessary to more actively diffuse the atoms to be sputtered into the connection hole. If the move spieces of the reaction with Si are metal atoms to be sputtered, the metal in the connection hole will easily flow.

As an example, the substance in which the move spieces of the reaction is a metal is considered to be a silicide of a transition metal such as Co, Ni or Pd.

The process using Co as an example will be described below.

In this embodiment, first, through the steps (1) to (4) shown in the first embodiment, as shown in FIG. 7A, the interlayer insulating film 7a and the connection hole 15 are formed on the silicon substrate 1. To form.

(5) As shown in FIG. 7B, Co16 is formed on the entire surface. At this time, the temperature of the silicon substrate 1 is 600 ° C.
Heat to a degree. Next, as shown in FIG.
Are formed on the entire surface. Condition example Ar = 40 sccm, pressure 0.04 Pa, R
F bias 50W, temperature 600 ℃, sputter power
1 KW, film thickness 30 nm As shown in FIG. 7B, Co silicide CoSi ₂ 17 is formed in the lower portion of the contact hole 15. Also, Co is the connection hole 15
The side wall portion of is not overhanged and is formed with good coverage.

(6) Al is formed on the entire surface by high temperature sputtering. Condition example Ar flow rate 40 sccm, pressure 0.04 Pa,
Temperature 500 ° C. Sputtering power DC 1 KW, 500 nm At this time, since Co is uniformly deposited in the connection hole 15, Al reacts with Co and uniformly fills the inside of the connection hole 15. Therefore, it is possible to completely flatten the connection hole.

Next, resist patterning is performed, and then a metal wiring film is dry-etched to form an Al wiring 12 and a transistor is formed as shown in FIG. 7C. As an example of conditions, an RF applied type ECR etcher is used, gas flow rate B
Cl ₃ / Cl ₂ = 60/90 sccm, microwave power 1000 W, RF power 50 W, pressure 21.3 Pa The MOS transistor according to the present embodiment is manufactured through the above steps.

The present invention is not limited to this embodiment, and other substances and methods may be used as long as this object can be achieved.

For example, instead of Al, an Al alloy, or a metal other than Al, such as Cu, Ag, W, or Mo, or Ti, which is a reaction substance with Al, is replaced with a refractory metal such as W or Mo.
Noble metals, transition metals, and semiconductor materials may be used.

[0081]

As described above, since the metal of Ti is deposited in the contact hole while reacting with the underlying silicon substrate, diffusion of Ti or the like is actively caused and the coverage in the contact hole can be improved. Moreover, it is possible to solve the problem of junction leakage at the edge portion of the field oxide film.

Further, since the base material (Ti or the like) necessary for filling the high temperature Al is uniformly formed in the connection hole,
Since the high temperature Al to be embedded is uniformly formed, the high temperature Al to be embedded can be uniformly embedded.

Further, since Ti or the like having a stable thickness can be deposited in the connection hole, silicide such as Ti can be stably formed only in the connection hole.

The SITO X-silicide (for example, TiSi ₂ ) at the connecting portion with Al has an oxide having a barrier property against Al, works as a barrier metal, and can maintain a low resistance sheet resistance.

[Brief description of drawings]

FIG. 1 is a sectional view of a first half step of manufacturing a MOS transistor showing a first embodiment.

FIG. 2 is a cross-sectional view of a half process during manufacturing of a MOS transistor showing the first embodiment.

FIG. 3 is a sectional view of a MOS transistor manufacturing second half process showing the first embodiment.

FIG. 4 is a sectional view of a MOS transistor manufacturing second half process showing the second embodiment.

FIG. 5 is a cross-sectional view (No. 1) of the second half process of manufacturing a MOS transistor showing a third embodiment.

FIG. 6 is a second half process cross-sectional view of a MOS transistor manufacturing process showing the third embodiment (No. 2).

FIG. 7 is a sectional view of a MOS transistor manufacturing second half process showing the fourth embodiment.

FIG. 8 is a sectional view illustrating a mechanism of an embedding effect according to the present invention.

FIG. 9 is a sectional view of a first half step of manufacturing a MOS transistor showing a conventional example.

FIG. 10 is a sectional view of a MOS transistor manufacturing second half process showing a conventional example.

[Explanation of symbols]

1 Silicon Substrate 2 Field Oxide Film 3 Gate Electrode 4 Gate Oxide Film 5 LDD Diffusion Region 6 Ion Implantation (As or BF ₂ ) 7 Interlayer Film 8 Diffusion Layer 9 Oxide Film 10, 13 Ti 11,21 SITOX-TiSi ₂ 12 Al Wiring 14, 14a Silicon nitride film (SiN) 15 Connection hole 16 Co 17 CoSi ₂ 18 Sidewall

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location H01L 21/3205 21/90 D 7735-4M

Claims (7)

[Claims] 1. A method of embedding a wiring material in a connection hole formed by patterning an interlayer insulating film formed on the entire upper surface of a silicon substrate, wherein the interlayer insulating film is patterned to form a connection hole. And then forming a metal for forming a silicide in the connection hole,
A method of filling and forming a contact hole, comprising depositing at a temperature at which the silicon substrate and a metal for forming the silicide react with each other. 2. The method for forming a buried contact hole according to claim 1, wherein the metal for forming the silicide is a transition metal. 3. The method according to claim 1, wherein the transition metal is cobalt. 4. A method of embedding a wiring material in a connection hole formed by patterning an interlayer insulating film formed on the entire upper surface of a silicon substrate, wherein the interlayer insulating film is patterned to form a connection hole. And then forming a metal for forming a silicide in the connection hole,
Depositing at a temperature at which the silicon substrate reacts with a metal for forming the silicide, removing a metal that has not reacted with the silicon substrate, and stabilizing a reactant of the metal and the silicon substrate And a step of depositing a metal for forming the silicide in the contact hole at a temperature at which the silicon substrate and the metal for forming the silicide react with each other. A method for forming a buried contact hole, which comprises: 5. A method of embedding a wiring material in a connection hole formed by patterning an interlayer insulating film formed on the entire upper surface of a silicon substrate, wherein the connection hole is formed by patterning the interlayer insulating film. And then forming a thin oxide film in the contact hole, and depositing a metal for forming a silicide in the contact hole at a temperature at which the silicon substrate and the metal for forming the silicide react with each other. A method for forming a buried contact hole, which comprises the step of: 6. The silicon oxide film or the silicon oxynitride film is used as the oxide film, the thickness thereof is 10 nm or less, the metal for forming the silicide is titanium, and the temperature at which the metal is deposited in the connection hole. 5. The method for forming a contact hole embedding according to claim 4, wherein is deposited at 600 ° C. or higher. 7. A connection hole embedding formation method for embedding a wiring material in a connection hole formed by patterning an interlayer insulation film formed on the entire upper surface of a silicon substrate, wherein the connection hole is formed by patterning the interlayer insulation film. And then forming a silicon nitride film on the surface of the connection hole, and a metal for forming a silicide in the connection hole at a temperature at which the silicon substrate reacts with a metal for forming the silicide. A method of filling and forming a contact hole, comprising a step of depositing.