JPH05335902A - Pulse generator - Google Patents

Abstract

(57) [Abstract] [Purpose] A pulse generator for use in a clock control device that maintains the same signal as the clock immediately before the interruption of the reference clock supply, and a desired number of pulses in a fixed time without increasing the circuit scale. Is to be output at even intervals. The pulse generating means 2 generates a desired number of pulses every second predetermined time during a first predetermined time. That is, if the desired number is m and the quotient obtained by dividing the first predetermined time period by the second predetermined time period is n, then from the pulse generating means 2 m * is obtained during the first predetermined time period. n pulses are generated. The frequency divider 3 divides m × n number of pulses by n. That is, the frequency dividing means 3 outputs the input m × n number of pulses for every n pulses. Therefore,
The frequency dividing means 3 outputs a desired number m of pulses at equal intervals during the first predetermined time.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pulse generator for generating a desired number of pulses at regular intervals during a predetermined time, and more particularly to clock control for maintaining the same signal as the clock immediately before the interruption of the reference clock supply. The present invention relates to a pulse generator used in a device.

A network synchronizing device is required for a network synchronizing system for supplying a clock having the same frequency to a digital exchange, a synchronizing terminal equipment, etc. of a transmission network to exchange time slots, set a line, and perform demultiplexing. .. The network synchronizer uses a phase-locked loop (PLL) to synchronize a signal from a highly stable oscillator placed in its own station with a reference clock from a higher station, and to provide a stable clock in various stations. A device that distributes to devices. In particular, in a network synchronizer to which a digital type PLL is applied, the result of phase comparison between the input frequency and the output frequency is digitized, the phase difference data for a few seconds is averaged, and only the phase fluctuation of extremely low frequency is detected to detect the oscillation frequency. Are in control. As a result, the cutoff frequency of the jitter can be lowered, and since the phase comparison result is once converted into a digital value, this value can be stored in the memory. With this storage function, a stable clock can be supplied to each device in the station and lower stations even if the reference clock from the upper station is not supplied.

[0003]

2. Description of the Related Art Conventionally, a network synchronizer to which such a digital PLL is applied is prepared in advance according to a digitized phase comparison result immediately before the interruption when the supply of the reference clock from the upper station is interrupted. A suitable pulse pattern is selected from among the plurality of pulse patterns, and the selected pulse pattern is added to or removed from the fixed oscillator output pulse of the PLL, whereby the reference clock Even if the supply was cut off, the same clock as the clock just before the cut was maintained.

[0004]

However, it is necessary to prepare many kinds of pulse patterns in order to generate a clock that exactly matches the reference clock before the interruption.
There is a problem that the circuit scale of the device increases as the number of types of pulse patterns increases.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a pulse generator which outputs a desired number of pulses at a uniform interval in a fixed time without increasing the circuit scale. And

[0006]

In order to achieve the above object, the present invention provides a pulse generator for generating a desired number of pulses at equal intervals during a first predetermined time as shown in FIG. Will be provided. This pulse generating device measures a second predetermined time shorter than the first predetermined time and outputs an end signal each time the time ends, and the desired number is set, A quotient obtained by dividing the first predetermined time by the second predetermined time with the pulse generating means 2 for generating the desired number of pulses for each input of the end signal and the pulse generated by the pulse generating means 2. And a frequency dividing means 3 which divides the frequency by the value of.

[0007]

With the above configuration, in FIG. 1, the pulse generating means 2 generates the desired number of pulses every second predetermined time during the first predetermined time. That is, if the desired number is m and the quotient obtained by dividing the first predetermined time by the second predetermined time is n, the pulse generation means 2 calculates the first
M × n number of pulses are generated during the predetermined time period. Since the frequency dividing means 3 divides m × n number of pulses by n (sets the pulse frequency to 1 / n), eventually the input m × n.
Will be output for every n pulses. Therefore, the frequency dividing means 3 outputs a desired number m of pulses at equal intervals during the first predetermined time.

[0008]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 2 is a block diagram showing the configuration of the rate multiplier which is the embodiment of the present invention. The rate multiplier 20 is a pulse generator that generates a desired number of pulses of m at a predetermined time T ₁ at equal intervals. First, the down counter 21 has a number of pulses of m desired to be generated at a predetermined time T _1. Is input in parallel. Further, in the down counter 21, the timer 22 is connected to the LOAD terminal, and the clock signal (CLK) is input to the CLK terminal.

The clock signal (CLK) is also input to the timer 22, and the timer 22 counts the number of clock signals to measure the time and outputs a pulse every T ₂ time which is an integer fraction of the predetermined time T ₁ . Rise of down counter 21
Output to OAD terminal.

The down counter 21 loads a desired number m into the count value each time the rising edge of the pulse is input from the timer 22, and decrements the count value for each clock signal input thereafter. When the count value reaches 0, that value is held until the next load. Then, the down counter 21 outputs to the OR circuit 23 a pulse (borrow-out output) that falls at the rising timing of the pulse from the timer 22 and rises at the timing when the count value of the down counter 21 reaches zero.

The clock signal (CLK) is input to the other input terminal of the OR circuit 23, and the down counter 21
The clock signal is output to divider 24 while the borrow out output from is low. The frequency divider 24 divides the output pulse from the OR circuit 23 by n (n = T ₁ / T ₂ ) and outputs it (with the pulse frequency of 1 / n).

FIGS. 3 and 4 are timing charts showing signal forms in respective parts of the rate multiplier 20 configured as described above. FIG. 3A shows a clock signal (CLK), similarly (B) shows the output of the timer 22, and (C) shows the count value of the down counter 21,
(D) shows the output of the down counter 21, and (E) shows the output of the OR circuit 23.

That is, the timer 22 is, for example, every 11 rising edges of the clock pulse (corresponding to the elapse of T ₂ time).
The pulse that rises to (B) is output. The down counter 21 is loaded with a desired number m (for example, 3) at the rising timing of the output of the timer 22, and the loaded count value is decremented at each subsequent rising edge of the clock signal (C). The output of the down counter 21 falls at the rising timing of the output pulse of the timer 22 and rises at the timing when the count value of the down counter 21 reaches 0 (D). The OR circuit 23, to which the clock signal (A) and the output (D) of the down counter 21 are input, generates a desired number m of pulses every T ₂ time (E).

FIG. 4F corresponds to FIG. 3B and shows the output of the timer 22. FIG. 4G corresponds to FIG. 3E and shows the output of the OR circuit 23. In addition, FIG.
The output of the frequency divider 24 is shown.

That is, n for a predetermined time T ₁ (for example, 8)
The output of the timer 22 rises (F) every T ₂ time, which is one-half, and the desired number m (for example, 3) of pulses (falling edge) are generated from the OR circuit 23 every T ₂ time (G). ). The frequency divider 24 outputs n (for example, 8) pulses from among the pulses input from the OR circuit 23 (H). Therefore, the output of the frequency divider 24 is the predetermined time T
A desired number m of pulses generated at equal intervals in the _1.

As described above, the rate multiplier 20
Is a frequency 1 / T ₁
To a frequency of the clock signal, a pulse signal having an arbitrary frequency can be generated.

FIG. 5 is a block diagram showing a frequency controller using the rate multiplier 20. This frequency controller constitutes a part of a network synchronizer to which a digital PLL is applied. In the figure, those parts that are the same as those shown in FIG. 2 are designated by the same reference numerals, and a description thereof will be omitted.

The frequency control unit 51 is a digital PLL.
On the basis of the result of the phase comparison in ( ₁₎ , the number of insufficient pulses or the number of extra pulses is detected during the predetermined time T ₁ . That is, the frequency control unit 51 sends a polarity signal indicating pulse shortage or pulse surplus to the clock control unit 52,
Further, the number of deficient pulses or the number of extra pulses is sent to the down counter 21 of the rate multiplier 20 as a load value. As described above, the rate multiplier 20 outputs the load value pulses at equal intervals during the predetermined time T ₁ and sends them to the clock control unit 52.

The fixed oscillator 53 corresponds to an oscillator in a digital type PLL and generates the clock signal (CLK) shown in FIG. 2 and supplies it to each part of the rate multiplier 20 and also the clock control part 52. Also supply.

The clock controller 52 adds the output pulse from the rate multiplier 20 to the clock signal from the fixed oscillator 53 based on the polarity signal from the frequency controller 51 (increases clock teeth), or Exclude (clock missing) and output.

Thus, the clock signal output from the clock control unit 52 becomes a clock signal synchronized with the reference clock input to the PLL, and since the phase comparison result is a digital value, it can be held, so that the reference from the host station can be maintained. Even if the clock supply is cut off, the clock state immediately before the cutoff can be stably maintained.

[0022]

As described above, according to the present invention, by generating a predetermined number of pulses every second predetermined time and dividing the number of pulses, a desired number of pulses can be obtained within the first predetermined time. Can be generated at equal intervals. Moreover, the circuit scale of the device does not increase even if the desired number is within a predetermined range.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a block diagram showing a configuration of a rate multiplier.

FIG. 3 is a timing chart showing a signal form in each unit of the rate multiplier.

FIG. 4 is a timing chart showing a signal form in each unit of the rate multiplier.

FIG. 5 is a block diagram showing a frequency control device.

[Explanation of symbols]

 1 clocking means 2 pulse generating means 3 frequency dividing means

Claims (3)

[Claims] 1. A pulse generator that generates a desired number of pulses at equal intervals during a first predetermined time, and counts a second predetermined time shorter than the first predetermined time, and then ends the timing. Timing means (1) that outputs an end signal for each
A pulse generation means (2) for generating the desired number of pulses for each input of an end signal from the timekeeping means (1), and the pulse generation means (2) for generating the desired number of pulses. A pulse generator, which divides the generated pulse by a value of a quotient obtained by dividing the first predetermined time by the second predetermined time. 2. A clock generation means for generating a clock pulse of a predetermined frequency is further provided, wherein the pulse generation means (2) comprises a down counter and an OR circuit to which the clock generation means is connected, and the down counter has The desired number is set for each input of the end signal from the time counting means (1), and a low level signal is input to the OR circuit while the clock pulse from the clock generating means is input by the desired number. The pulse generator according to claim 1, wherein the pulse generator is configured to output. 3. The pulse generating means (2) sets, as the desired number, data obtained by converting a phase comparison result into a digital value, which is output from a digital type PLL, and outputs the frequency dividing means (3). 2. The pulse generator according to claim 1, wherein the pulse generator is used for frequency control of an output pulse of the digital type PLL.