JPH05335963A - D/a converter - Google Patents

Abstract

(57) [Summary] [Purpose] Does not require a high clock like PWM,
Further, the present invention provides a D / A conversion device that does not require high accuracy in the D / A conversion circuit. The digital input is converted into a digital signal having a high sampling frequency and a small number of bits by a digital filter 10 and a noise shaper 11, and the noise shaper 1
The output signal from 1 is converted into a corresponding 1-bit signal sequence by the decoder 12 and converted into an analog signal by the 1-bit D / A converter 13 column, and these analog signals are converted into the analog adder 1
Comprehensive analog output in 4. The output of the decoder 12 is such that the number of 1-bit signals corresponding to the output value of the noise shaper 11 circulates, and by eliminating the correlation between the specific 1-bit signal and the output value of the noise shaper 11, noise And reduce distortion.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a D / A (digital / analog) converter for converting a digital signal into an analog signal, and in particular, performs D / A conversion at a sampling frequency higher than the sampling frequency of a digital input signal. The present invention relates to an oversampling D / A conversion device.

[0002]

2. Description of the Related Art As one of D / A converters, a D / A converter using a noise shaper and PWM has been reported. A conventionally reported D / A converter of this system will be described with reference to FIG. For details on this technology, refer to "National Technical Report (Vol. 34, No. 2).
No., April 1988) pp. 40-45 ".

FIG. 7 is a block diagram showing an example of a conventional D / A converter. 10 is a digital filter (DF)
That is, the sampling frequency fs of the input digital signal is multiplied by n (n ≧ 2). Where n
= 64. 11 is a noise shaper (NS),
The word length of the digital signal output from the digital filter 10 is limited, and the frequency characteristic of noise is changed to a predetermined characteristic. Here, it is assumed that the noise shaper has a cubic characteristic, and the output Y with respect to the input X is represented by (Equation 1).

[0004]

[Equation 1]

The output Y is assumed to have an 11 (= p) level output. 70 is a pulse width modulation circuit (PWM)
Is converted into a 1-bit pulse signal having 11 pulse widths corresponding to the digital signal output from the noise shaper 11 and output as an analog signal. The D / A conversion device of FIG. 7 sets the sampling frequency of 64 fs and 11 levels by the digital filter 10 and the noise shaper 11, and then the PWM 7
When it is 0, it further converts into an analog signal by using at least 704 times (64 × 11) clock, and is a so-called oversampling type D / A converter which converts a digital signal into an analog signal at a higher sampling frequency. ing.

FIG. 8 shows the result obtained by computer simulation of the output signal spectrum of the D / A converter shown in FIG. For simplification, the signals from 0 to 2fs are shown here. As described above, although the digital signal of only 11 levels is converted into the analog signal, as shown in FIG.
In the signal band of / 2, a dynamic range (DR) of 120 dB or more can be obtained.

[0007]

However, in the configuration shown in FIG. 7, the PWM 70 requires a clock of at least 704 fs. For example, when the sampling frequency fs = 48 kHz widely used in digital audio, the clock becomes an extremely high clock of 704 fs = 33.792 MHz, and there is a practical problem such as a need for countermeasures against electromagnetic interference and electromagnetic interference.

When D / A conversion is performed by a method other than PWM, it is possible to operate with a clock lower than that for PWM. For example, a D / A conversion circuit using a resistor string may be used. However, for this purpose, there is a problem in that it is difficult to manufacture the D / A conversion circuit because the resistor array requires extremely high relative accuracy.

The present invention solves the above-mentioned conventional problems and does not require a high clock unlike PWM, and D
It is an object of the present invention to provide a D / A conversion device that does not require high accuracy in the / A conversion circuit.

[0010]

In order to achieve this object, the D / A converter of the present invention has the following configuration.

(1) A digital filter that multiplies the sampling frequency of an input digital signal by n times (n ≧ 2), and the output of the digital filter is input to change the word frequency limit and the noise frequency characteristic to a predetermined characteristic. A noise shaper, a decoder for receiving the output of the noise shaper and converting it into a 1-bit signal string corresponding to the input value, and a 1-bit D / A converter string for converting the output of the decoder into an analog signal , 1-bit D / A
An analog adder that integrates the outputs of the converter array is provided, and the output of the decoder is such that a number of 1-bit signals corresponding to the value of the output of the noise shaper circulates.

(2) The decoder outputs at least (p-1) 1-bit signal strings corresponding to the p-valued signals (p is an integer) output from the noise shaper. In this way, the allocation start position of the 1-bit signal sequence is cyclically allocated so that it is the position next to the final allocation position of the 1-bit signal sequence one sample data before.

(3) At least (p-1) 1-bit signal strings are output from the output of the decoder in correspondence with signals having p values (p is an integer) output from the noise shaper. In this way, the allocation start position of the 1-bit signal sequence is circulated by a predetermined number for each sample data.

(4) At least 2 (p-1) 1-bit signal strings are output from the output of the decoder corresponding to the p-valued signals (p is an integer) output from the noise shaper. Therefore, the allocation of the 1-bit signal is cyclic, and none of the signals of the 1-bit signal train is allocated continuously for two sample data.

[0015]

According to the present invention having the above-described structure, the output of the noise shaper is converted into a 1-bit signal string by the decoder,
By converting to an analog signal with the bit D / A converter string, the sampling frequency at the time of D / A conversion may be the same as the sampling frequency of the digital output of the noise shaper, and operation with a clock much lower than PWM Is possible. Further, the decoder allocates the output of the noise shaper so as to circulate to the plurality of 1-bit D / A converters, thereby eliminating the correlation between the output value of the noise shaper and the specific 1-bit D / A converter. .. As a result, even if the outputs between the 1-bit D / A converters have variations, it is possible to reduce the occurrence of distortion and noise in the signal band.

[0016]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a D / A converter according to the present invention. In FIG. 1, 10 is a digital filter (DF) and 11 is a noise shaper (NS), both of which have the same configurations and functions as those shown in FIG. Reference numeral 12 is a decoder (DEC), which corresponds to the digital signals output from the noise shaper 11 and includes m 1's.
It outputs a bit signal. 13 is 1 bit D /
A converter array (DAC) and a first D / A converter (D
AC-1) to the mth D / A converter (DAC-m) are all configured by m uniform 1-bit D / A converters. Reference numeral 14 is an analog adder, which integrates m analog signals output from the 1-bit D / A converter array 13,
Output as an analog signal. Reference numeral 15 denotes a D / A conversion circuit, which is a 1-bit D / A converter array 13 and an analog adder 1
4 and. The D / A converter of FIG. 1 uses a digital filter 10 and a noise shaper 11 to sample a digital input signal at sampling frequencies of 64 fs and 11 (= p).
After the level is set, the decoder 12 converts the signal into m 1-bit signals, and the D / A conversion circuit 15 converts the signal into an analog signal. It is a type D / A converter.

An example of the D / A conversion circuit 15 of FIG. 1 is shown in FIG. In FIG. 2, 13 is a 1-bit D / A converter array (DA
C) and 14 are analog adders, and 15 is a D / A conversion circuit, which correspond to FIG. Reference numeral 20 denotes an inverter, which inverts a 1-bit input signal and outputs it. 21,
Reference numeral 22 is a resistor, and 23 is an operational amplifier (operational amplifier). To explain the operation of FIG. 2, first, the non-inverting input terminal of the operational amplifier 23 is grounded, and the inverting input terminal is a virtual ground point. Further, the 1-bit input signal is all connected to the inverting input terminal of the operational amplifier 23 via the inverter 20 and the resistor 21, and further connected to the output terminal of the operational amplifier 23 via the resistor 22. That is, resistor 2
1 and 22 form a current adding circuit. Now D
The resistance value of the resistor 21 of AC-1 is R1, the resistance value of the resistor 21 of DAC-2 is R2, ..., The resistor 21 of DAC-m.
The analog output voltage Eo is calculated by the equation (2), where Rm is the resistance value of R and Rf is the resistance value of the resistor 22.

[0019]

[Equation 2]

Since the 1-bit D / A converter array 13 has a uniform structure, the resistance value of the resistor 21 is also R1 =.
R2 = ... = Rm, and the output of the operational amplifier 23, that is, the analog output, is a voltage value proportional to the number of signals in which the 1-bit input signal is "0" (that is, the output of the inverter 20 is "1"). Is output.

In an actual circuit, a 1-bit D / A converter array 1
It is not possible to manufacture resistor 3 of 3 perfectly uniformly and there is some relative error. In this case, as is clear from (Equation 2), a voltage value that depends not only on the number of 1-bit input signals that are "0" but also on the position is output.

An example of the decoder 12 of FIG. 1 is shown in FIG.
In FIG. 3, reference numeral 30 denotes a pointer, which outputs the remainder of the accumulated value of the input signal. Reference numeral 31 is a ROM (read-only memory), which outputs m-bit data corresponding to an address whose input signal is lower and output of the pointer 30 is upper. Here, m = 10 (= p-1). The operation of FIG. 3 will be described. First, the pointer 30 is shown in FIG.
11-level signals (0 to 10) output from the noise shaper 11 are accumulated, and a remainder of 10 is obtained and output. Therefore, there are 10 outputs, 0 to 9. Next, an address having a lower input signal and an upper output signal of the pointer 30 is input to the ROM 31 to obtain 10-bit data. This 10-bit data represents ten 1-bit signals. The relationship between the address (decimal number) and the data (binary number) at this time is shown in (Table 1).

[0023]

[Table 1]

Explaining (Table 1), the 10-bit data is "1" as indicated by the lower address, that is, the value of the input signal, and the sum of each bit is equal to the input signal. Also, the lower address, that is, the pointer 30
The output signal is shifted to the left by the number shown, and the overflowing digits are circulated so that they appear from the right. By defining the ROM 31 as in (Table 1), data is output as in (Table 2).

[0025]

[Table 2]

As can be seen from (Table 2), "1" indicated by the numerical value of the input signal is output so as to circulate 10-bit data.
It indicates that there is no correlation with a specific bit of the bit data. Therefore, even if there is a variation between the outputs of the 1-bit D / A converter array 13 to which the 10-bit data is connected, it is possible to reduce distortion and noise in the signal band.

In the D / A converter of FIG. 1, 1-bit D / A
FIG. 4 shows a result obtained by simulating the output signal spectrum when the output of the converter array 13 has a maximum variation of ± 0.1% as shown in (Table 3). For simplification, the signals from 0 to 2fs are shown here.

[0028]

[Table 3]

As shown in FIG. 8, the noise shaper 1
The output from 1 is 120d in the signal band from 0 to fs / 2
Although a dynamic range of B or more can be obtained, the dynamic range is about 118 dB in FIG. 4, and there is a variation of up to ± 0.1% in the output of the 1-bit D / A converter array 13, It can be seen that the performance deterioration is slight. On the other hand, FIG. 5 shows a result obtained by simulating the output signal spectrum when the output is such that the data does not circulate, for example, when the output of the pointer 30 is fixed to 0 regardless of the input. As can be seen from FIG. 5, noise is increased, harmonic distortion is generated, and the dynamic range is significantly deteriorated to about 84 dB as compared with FIG.

Further, here, the operation of the pointer 30 is such that the 11-level signals (0 to 10) outputted from the noise shaper 11 of FIG. 1 are accumulated and the remainder of 10 is obtained and outputted. As another embodiment, the operation of the pointer 30 may be such that the signals 0 to 9 are repeatedly output in order regardless of the output of the noise shaper 11. FIG. 6 shows the result of the simulation of the output signal spectrum in this case. As shown in FIG. 6, although there is an increase in noise as compared with FIG. 8 and FIG. 4, the harmonic distortion that occurred in the case of FIG. 5 is not seen, and compared with FIG. The dynamic range has also been improved. In particular, in this method, the operation of the pointer 30 need only repeatedly output the signals of 0 to 9 in order, and since the calculation of accumulation and remainder is unnecessary, the circuit scale of the pointer 30 can be reduced.

Next, still another embodiment of the present invention will be described. Generally, when the 1-bit D / A converter outputs "1", the output value is different when the immediately preceding data is "1" and when it is "0". This is because the previous value affects the output value at the data change point. In order to avoid this, the data immediately before "1" must be always "0", that is, "1" should not be output from the 1-bit D / A converter continuously for 2 sample data. Good.

By applying this principle to the D / A converter of FIG. 1, the D / A converter is constructed as follows. Since the digital filter 10 and the noise shaper 11 have the same configurations and operations as those described above, the description thereof will be omitted.

First, regarding the decoder 12, the operation of the pointer 30 of FIG. 3 is performed by accumulating the 11 (= p) level signals output from the noise shaper 11 and obtaining the remainder of 20 and outputting. Therefore, there are 20 kinds of outputs, 0 to 19. Next, the input signal is lower, the pointer 30
An address whose output signal is higher is input to the ROM 31 to obtain 20 (= 2 (p-1))-bit data. The 20-bit data represents 20 1-bit signals, and the relationship between the address (decimal number) and the data (binary number) at this time is shown in (Table 4), (Table 5) and (Table 6).

[0034]

[Table 4]

[0035]

[Table 5]

[0036]

[Table 6]

Explaining (Table 4), (Table 5) and (Table 6), the 20-bit data is "1" as indicated by the numerical value of the lower address, that is, the input signal, and the sum of each bit is the input signal. Is equal to. Further, the lower part of the address, that is, the output signal of the pointer 30, is shifted to the left as indicated by the numerical value, and the overflowed digits are circulated so as to appear from the right. ROM3 as shown in (Table 4), (Table 5), (Table 6)
By defining 1, data is output as shown in (Table 7).

[0038]

[Table 7]

As can be seen from (Table 7), "1" indicated by the numerical value of the input signal is output so as to circulate 20-bit data.
It indicates that there is no correlation with a specific bit of the bit data. Furthermore, since the maximum value of the input signal is 10, 20-bit data, that is, all 20 1-bit signals do not output "1" continuously for 2 sample data.

The 20-bit signal thus obtained is input to the 1-bit D / A converter array 13 and is converted into an analog output via the analog adder 14. At this time, 1 bit D / A
The converter array 13 is composed of m = 20 (= 2 (p-1)) 1-bit D / A converters.

With the above configuration, even if there is a variation between the outputs of the 1-bit D / A converter array 13 as described above, it is possible to reduce the occurrence of distortion and noise in the signal band, and further Since 1-bit data does not output "1" continuously for two data, the output of the 1-bit D / A converter array 13 is not affected by the immediately preceding data, and high-precision D / A conversion is possible. It will be.

The D / A converter is configured as described above. Although the noise shaper represented by (Equation 1) is used here, it is needless to say that different orders and characteristics may be used as long as they function as a noise shaper. Further, the configuration of the decoder 12 shown in FIG. 3 and the ROM data and the like in (Table 1) are examples for description, and needless to say are not limited to these. Further, the number m of output bits of the decoder 12 (that is, the number m of 1-bit D / A converters 13) for p outputs of the noise shaper 11 is set to (p-1) and 2 (p-1), respectively. As described above, since these are the minimum cases, m may be more than this depending on the circumstances such as the circuit configuration.

[0043]

As described above, in the D / A conversion device of the present invention, the sampling frequency at the time of D / A conversion may be the same as the sampling frequency of the digital output of the noise shaper, which is far higher than PWM. It has an excellent feature that it can operate with a low clock.

Further, since the decoder allocates the output of the noise shaper so as to circulate to the plurality of 1-bit D / A converters, the correlation between the output value of the noise shaper and a specific 1-bit D / A converter. 1 bit for each D /
Even if there are variations in the outputs between the A converters, it has an excellent feature that it is possible to reduce the generation of distortion and noise in the signal band.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a D / A conversion device according to the present invention.

FIG. 2 is a circuit diagram showing an example of a D / A conversion circuit 15 of FIG.

3 is a block diagram showing an example of a decoder 12 in FIG.

FIG. 4 is an output signal spectrum of the D / A conversion device of FIG. 1 obtained by computer simulation.

5 is an output signal spectrum in the D / A converter of FIG. 1 when the output of the pointer 30 is fixed to 0 regardless of the input.

FIG. 6 is an output signal spectrum in the D / A converter of FIG. 1 when the operation of the pointer 30 is such that signals 0 to 9 are repeatedly output in order regardless of the output of NS11.

FIG. 7 is a block diagram showing an example of a conventional D / A conversion device.

FIG. 8 is an output signal spectrum of the D / A converter of FIG. 7, obtained by computer simulation.

[Explanation of symbols]

 10 Digital Filter (DF) 11 Noise Shaper (NS) 12 Decoder (DEC) 13 1-bit D / A Converter Sequence (DAC) 14 Analog Adder 15 D / A Conversion Circuit 20 Inverter 21, 22 Resistor 23 Operational Amplifier (Operation) Amplifier) 30 Pointer 31 ROM (Read-only memory)

Claims (4)

[Claims] 1. A digital filter for multiplying a sampling frequency of an input digital signal by n times (n ≧ 2), and an output of the digital filter as an input, and changing a frequency characteristic of noise to a predetermined characteristic with word length limitation. A noise shaper, a decoder that inputs the output of the noise shaper, and converts the output of the decoder into a 1-bit signal string, and a 1-bit D / A converter string that converts the output of the decoder into an analog signal An analog adder that integrates the output of the 1-bit D / A converter array, and an output such that a number of 1-bit signals corresponding to the value of the output of the noise shaper circulates the output of the decoder. D / A converter. 2. The output of the decoder is adapted to output at least (p-1) 1-bit signal strings corresponding to p-valued signals (p is an integer) output from the noise shaper, 2. The D / A conversion device according to claim 1, wherein the allocation start position of the 1-bit signal string is cyclically allocated so that the allocation start position is next to the final allocation position of the 1-bit signal string one sample data before. .. 3. The decoder outputs at least (p-1) 1-bit signal strings corresponding to p-valued signals (p is an integer) output from the noise shaper. The D / A conversion device according to claim 1, wherein the allocation start position of the 1-bit signal sequence is cyclically moved by a predetermined number for each sample data. 4. The output of the decoder is adapted to output at least 2 (p-1) 1-bit signal strings corresponding to p-valued signals (p is an integer) output from the noise shaper. 2. The D / A conversion device according to claim 1, wherein the allocation of the 1-bit signal is cyclic, and none of the signals of the 1-bit signal sequence is allocated continuously with two sample data.