JPH0535530A - Address stop control circuit - Google Patents

Abstract

(57) [Summary] [Purpose] The address is stopped at the address you want to stop under the conditions determined by the execution / non-execution of multiple micro instructions specified by the firmware. A control memory 1 for storing firmware, an address register 2 for holding an address of a microinstruction being executed, an address comparator 6 for comparing data of a stop address register 3 for storing an address to be stopped, and an address register 2 and the condition comparators 7 and 8 that compare the data of the condition registers 4 and 5 that store the specified address, the match flip-flops 9 and 10 set by the condition comparators 7 and 8, and the address comparator 6 match. And the coincidence flip-flops 9 and 10 are detected.
The stop signal generation circuit 11 that generates the stop signal 13 according to the condition 1 and the clock control circuit 1 that stops the clock when the stop signal 13 is input and stops the address
2 and.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an address stop control circuit of an information processing device having a control memory and controlled by microinstructions.

[0002]

2. Description of the Related Art Conventionally, this kind of address stop control circuit has one control memory, one address register, one stop address register, and one address comparator, and when the address register and the stop address register match, The address was always stopped.

[0003]

When micro instructions are executed in a subroutine format at the time of firmware evaluation, failure analysis, etc., there arises a situation in which an address stop is desired at a certain set condition and at an address to be stopped. Come on.

In such a case, in the conventional address stop circuit configuration as described above, since the condition comparator and condition register are not provided, the condition cannot be set, and the address stored in the stop register is always used as the address stop. Was.

An object of the present invention is to provide an address stop control circuit that solves the above problems.

[0006]

In order to achieve the above object, in the address stop control circuit according to the first invention of the present application, a control memory for holding a micro instruction and an address of the micro instruction currently being executed are set. An address register for storing, a stop address register for holding an address of a micro instruction to be stopped, an address comparator for comparing data of the address register and the stop address register, and a plurality of condition registers for holding a plurality of addresses. , A plurality of condition comparators that compare the data in the address register and the condition register, a plurality of match flip-flops that are set when the plurality of condition comparators detect a match, and the address comparator A stop signal is detected and detected by the states of the plurality of coincidence flip-flops. A stop signal generating circuit for forming, as an input a stop signal from the stop signal generating circuit, and has a clock control circuit for controlling the stepping and stopping the clock.

An address stop control circuit according to a second invention of the present application is a plurality of condition registers which hold a plurality of designated addresses in the first invention, and a plurality of address registers which compare data of the condition registers. Instead of a condition comparator, a plurality of condition registers that hold the data of a plurality of specified general-purpose register (or accumulator) and a specified general-purpose register (or accumulator)
And a condition comparator for comparing the data in the condition register.

[0008]

According to the present invention, the address of the specified micro instruction or the data of the specified general register (or accumulator) is stored in the condition register and whether the micro instruction of the specified address is executed or not The address is stopped at the address at which the clock is to be stopped, on condition that the (or accumulator) takes a specified value.

[0009]

Embodiments of the present invention will now be described with reference to the drawings.

(First Embodiment) FIG. 1 is a block diagram showing a first embodiment of the present invention.

In FIG. 1, a control memory 1 holds micro instructions (formware).

The address register 2 stores the addresses of microinstructions currently being executed and outputs them to the address comparator 6 and the condition comparators 7 and 8.

The stop address register 3 stores the address of the specified micro instruction to be stopped and outputs it to the address comparator 6.

The condition registers 4 and 5 store the addresses of designated microinstructions, and these are stored in the condition comparators 7 and 8.
Is output to.

The address comparator 6 includes an address register 2
And the stop address register 3 are compared with each other, and if a match is detected, an output signal is transmitted to the stop signal generating circuit 11.

The condition comparators 7 and 8 include condition registers 4 and 5, respectively.
And the address register 2 are compared with each other, and if a match is detected, the match flip-flops 9 and 10 are set.

The coincidence flip-flops 9 and 10 are set when the condition comparators 7 and 8 detect coincidence, and transmit an output signal to the stop signal generating circuit 11.

The stop signal generating circuit 11 receives the signal from the address comparator 6, inputs the stop signal 1 to the clock control circuit 12 when the coincidence flip-flop 9 is set and the coincidence flip-flop 10 is not set.
3 is output.

Upon receiving the stop signal 13 from the stop signal generation circuit 11, the clock control circuit 12 stops the clock and stops the address.

FIG. 2 is a schematic flow chart showing one execution example of the microinstruction of this embodiment. In the figure, A to H indicate addresses of the general flow.

Execution starts at address A and branches to C or D at B. At D, either E or F is branched, and at H, either B is branched or the routine is terminated.

If an abnormal execution state occurs only when the address is executed as ABC-EG-G, the address must be stopped in this case.

Specifically, only when the address B branches to C and the address E branches to G,
It is necessary to stop the clock at the address G and stop the address.

The operation of FIG. 1 will be described using the schematic flow of FIG.

The control memory 1 holds firmware, which is a group of microinstructions for controlling the information processing apparatus, and the address register 2 holds the address of the microinstruction currently being executed.

The firmware stores the address G to be stopped in the stop address register 3, and the micro-instruction addresses C and F, which are the conditions for the address stop, in the condition registers 4 and 5, respectively. Further, the coincidence flip-flops 9 and 10 are reset as an initial state.

When a microinstruction whose address is C is executed, the address C is input to the address register 2,
The condition comparator 7 includes a condition register 4 and an address register 2.
When a match with is detected, the match flip-flop 9 is set.

If the micro instruction whose address is F is not executed before the address G is input to the address register 2, the condition comparator 8 detects a match between the condition register 5 and the address register 2. Never happen,
The coincidence flip-flop 10 is not set. .

Then, the address G is stored in the address register 2.
Is input, the address comparator 6 detects a match between the stop address register 3 and the address register 2 and sends an output signal to the stop signal generation circuit 11.

The stop signal generation circuit 11 uses the stop signal 1
An output signal of the address comparator 6, which is the generation condition of No. 3,
When the coincidence flip-flop 9 is set and the coincidence flip-flop 10 is not set, the stop signal 13 is generated and output.

The clock control circuit 12 which has received the stop signal 13 stops the clock and stops the address at the address G.

In this example, if the micro instruction at the address C is not executed, the coincidence flip-flop 9 is not set and the stop signal 13 of the stop signal generating circuit 11 is not set.
The stop signal 13 is not sent and the address stop is not performed because the condition for generation of is not satisfied.

When the F instruction is executed, the coincidence flip-flop 10 is set and the stop signal generation circuit 1
Since the condition for generating the stop signal 13 of 1 is not satisfied,
The stop signal 13 is not sent and the address is not stopped.

As described above, the stop signal generation circuit 11 generates the stop signal 13 at the address designated by the stop address register 3 only when the states of the coincidence flip-flops 9 and 10 satisfy all the generation conditions.

Therefore, when the target address stop is desired, that is, when the instruction at the address C is executed and the instruction at the address F is not executed, the address can be stopped at the address G.

(Second Embodiment) FIG. 2 is a block diagram showing a second embodiment of the present invention.

The structural difference of this embodiment from the invention of the first embodiment is as follows.

The general-purpose registers 33 and 34 are designated general-purpose registers.

The condition registers 24 and 25 store the data of the general purpose registers (or accumulators) 33 and 34 and output them to the condition comparators 27 and 28.

The condition comparators 27 and 28 are connected to the condition register 2
4 and general register 33 data, and condition register 2
5 and the data of the general-purpose register 34 are compared,
When they match, the matching flip-flops 29 and 30 are set respectively.

The general-purpose register 33 displays the value "D" of a certain data.
Consider that the general-purpose register 34 takes the value "a" and does not take the value "Db" of a certain data, and stops the address at the address "S" to be stopped.

It is realized by the following operation.

The firmware stores the address S to be stopped in the stop address register 23, and stores the data Da and Db as the condition of the address stop in the condition registers 24 and 25, respectively.

Further, the conditional flip-flops 29 and 30 are reset as an initial state.

If the general-purpose register 33 takes the value Da before the address S is input to the address register 22, the condition comparator 27 detects a match between the condition register 24 and the general-purpose register 33, The coincidence flip-flop 29 is set.

Similarly, before the address S is input to the address register 22, the general-purpose register 34 is set to Db.
If the value is not obtained, the condition comparator 28 does not detect a match between the condition register 25 and the general-purpose register 34, so that the match flip-flop 30 is not set.

The address S is the address register 2
When input to 2, the address comparator 26 detects a match between the stop register 23 and the address register 22 and sends an output signal to the stop signal generation circuit 31.

The stop signal generation circuit 31 uses the stop signal 3
5, the output signal of the address comparator 26, which is the generation condition of 5, and the fact that the coincidence flip-flop 29 is set and the coincidence flip-flop 30 is not set are detected, and the stop signal 35 is generated and output. .

The clock control circuit 32 uses the stop signal 3
5, the clock is stopped, and the address is stopped at the address S.

In this example, the general register 33 is Da.
If you do not take the value
9 is not set and the generation condition of the stop signal 35 of the stop signal generation circuit 31 is not satisfied, the stop signal 35
Is not generated and the address is not stopped.

Similarly, when the general-purpose register 34 has a value of Db, the coincidence flip-flop 30 is set and the stop signal 35 generation condition of the stop signal generation circuit 31 is not satisfied, so that the stop signal 35 is generated. No
Do not stop address.

As described above, the stop signal generation circuit 31 generates the stop signal 35 at the address designated by the stop address register 23 only when the states of the coincidence flip-flops 29 and 30 satisfy all the generation conditions.

Therefore, if the general purpose register 33 takes the value Da and the general purpose register 34 does not take the value Db under the condition that the desired address stop is desired, the address stop can be performed at the address S. .

[0054]

As described above, in the address stop circuit of the present invention, the coincidence flip-flop that holds whether or not the execution progress of the microinstruction meets the individual conditions specified by the firmware, and the state of the coincidence flip-flop. Thus, when the condition for generating the stop signal specified by the firmware is satisfied, the stop signal generating circuit for generating the stop signal can perform the address stop at the address where the clock stop is desired.

As a result, there is an effect that firmware evaluation and failure analysis can be easily performed.

[Brief description of drawings]

FIG. 1 is a block diagram showing an address stop control circuit according to a first embodiment of the present invention.

FIG. 2 is a diagram showing an example of a schematic flow of execution of a plurality of microinstructions in the embodiment of the present invention.

FIG. 3 is a block diagram of an address stop control circuit according to a second embodiment of the present invention.

[Explanation of symbols]

1 control memory 2 Address register 3 Stop address register 4 Condition register 5 Condition register 6 Address comparator 7 Conditional comparator 8 Conditional comparator 9 match flip-flops 10 match flip-flops 11 Stop signal generation circuit 12 Clock control circuit 13 General-purpose register 14 General-purpose register 21 Control memory 22 Address register 23 Stop Address Register 24 Condition Register 25 Condition Register 26 Address comparator 27 Conditional comparator 28 Conditional comparator 29 coincident flip-flops 30 match flip-flops 31 Stop signal generation circuit 32 clock control circuit 33 General-purpose register 34 General-purpose register 35 stop signal

Claims (2)

[Claims] 1. A control memory for holding microinstructions, an address register for storing an address of a microinstruction currently being executed, a stop address register for holding an address of a microinstruction to be stopped, the address register and the An address comparator for comparing data in the stop address register, a plurality of condition registers for holding a plurality of addresses, a plurality of condition comparators for comparing data in the address register and the condition register, and a plurality of condition comparators A plurality of match flip-flops that are set when a match is detected, a stop signal generation circuit that detects a match by the address comparator and that generates a stop signal according to the states of the plurality of match flip-flops, and the stop The stop signal from the signal generation circuit is used as input, and the clock Address stop control circuit; and a clock control circuit for controlling the stop. 2. A plurality of designated general-purpose resisters instead of the plurality of condition registers holding a plurality of designated addresses and the plurality of condition comparators for comparing the data of the condition registers according to claim 1. (Or accumulator)
An address stop control circuit comprising: a plurality of condition registers for holding the data of 1., a specified general-purpose register (or accumulator) and a condition comparator for comparing the data of the condition register.