JPH0535601B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to an FM demodulator suitable for use, for example, in demodulating a luminance signal recorded in FM with a video tape recorder (VTR).

Background technology and its problems For example, in a VTR, a 0-3MHz luminance signal is modulated with a 3.6-4.8MHz deviation.
recorded as an FM signal.

When performing FM demodulation of this signal, the conventional direct demodulation method generates an unnecessary component twice the carrier wave (approximately 8 MHz), and in order to separate this unnecessary component from the signal component below 3 MHz, an extremely precise method is required. A high-order low-pass filter, for example, 7th order or higher, is now required.

In addition, when attempting to configure this low-pass filter with an active filter and convert it into an IC, the level of unnecessary components at 8MHz is high and the level of signal components below 3MHz is low, so a large dynamic range of the filter is required. The configuration was extremely difficult.

OBJECTS OF THE INVENTION In view of these points, the present invention is intended to prevent unnecessary components twice as large as the carrier wave from being generated using a simple configuration.

Summary of the Invention The present invention provides a 1/4 period phase shifter that follows the phase of an input FM signal and outputs two signals having a 1/4 period phase difference from each other, and responds to the edges of these two signals. a pulse train generating means for generating a pulse train having uniform amplitude and pulse width and a frequency four times that of the FM signal, and a low-pass filter for extracting low frequency components from the output pulse train of the pulse train generating means, In the FM demodulator that demodulates the FM signal, the 1/4 period phase shift means includes a delay circuit that delays the FM signal by a predetermined delay time, and a delay circuit that delays the FM signal by a predetermined delay time. a first current source that operates for a predetermined time that is longer than the time;
a capacitor that charges the current of the first current source; and a capacitor that charges the electric charge charged in the capacitor by the first current source in response to an edge of the FM signal delayed by the delay circuit; Current source 2
a second current source discharging at twice the current value;
When it is detected that the charge charged in the capacitor by the current source is discharged by this second current source, the FM delayed by the delay circuit is detected.
The FM demodulator is characterized by comprising a phase shift means for outputting a signal whose phase is shifted by 1/4 period from the signal, and according to this, with a simple configuration, unnecessary components twice as large as the carrier wave can be removed. Never occurs.

Embodiment In FIG. 1, a reproduced FM luminance signal is supplied to input terminal 1. The signal from this input terminal 1 is supplied to a 1/4 period phase shifter 2, and two signals having a 1/4 period phase difference from each other are formed, for example, as shown in FIGS. 2A and 2B.

These signals are supplied to delay circuits 3A and 3B, respectively, and are delayed by a predetermined delay time as shown in FIG. 2C and D. These signals and the original signal are sent to balanced demodulators 4A and 4B, respectively.
demodulated signals as shown in FIG. 2E and F are obtained. These demodulated signals are supplied to adder 5 and added.

As a result, a signal having carrier wave 4 (approximately 16 MHz) as an unnecessary component is output from the adder circuit 5 to the output terminal 6, as shown in FIG. 2G.

This signal is then supplied to a low-pass filter (not shown) to remove unnecessary components and extract the signal component.In this case, the frequency of the unnecessary component is approximately 16MHz, which is sufficiently far from the signal component's 3MHz. Therefore, there is no need to increase the precision of the low-pass filter. Furthermore, when a high-precision low-pass filter is used, the high frequency characteristics of the signal can be expanded.

Furthermore, if an active filter is used after removing unnecessary components with a simple low-pass filter such as a CR passive filter, the dynamic range may be narrow and a good demodulated signal can be obtained.

Further, FIG. 3 shows another embodiment. In the figure, two signals from the 1/4 period phase shifter 2 (Figure 4A,
B) is supplied to a multiplier 7 to form a doubled signal as shown in FIG. 4C.

This signal is supplied to the delay circuit 3C and
The signal is delayed by a predetermined delay time as shown in FIG. This signal and the original doubled signal are supplied to the balanced demodulator 4C, and a signal having unnecessary components four times the carrier wave is outputted to the output terminal 6, as shown in FIG. 4E.

Therefore, the same effects as described above can be obtained in this circuit as well.

In addition, in the above-mentioned circuit, the 1/4 cycle phase transmitter 2 is configured as follows.

In FIG. 5, a signal from an input terminal 21 is supplied to a fixed delay circuit 22 such as a low-pass filter or a monostable multivibrator, and the delayed signal is sent to a first
It is taken out to the output terminal 23A of.

Further, a signal from the input terminal 21 is supplied to a control terminal of a constant current source 24a having a current value I, and when the signal is high, a current from the constant current source 24a is supplied to the capacitor 25a to charge it.

Further, the signal from the delay circuit 22 is supplied to the set terminal of a rising edge-triggered SR flip-flop 26a, and the signal from the input terminal 21 is supplied to the reset terminal of the flip-flop 26a.

The Q output signal from the flip-flop 26a is supplied to the control terminal of a constant current source 27a with a current value of 2I, and when the signal is high, the capacitor 25a is discharged by the current passing through the constant current source 27a.

The emitter of a transistor 28a is connected to the hot side of this capacitor 25a, the constant voltage source 29 of potential Vx is connected to the base of this transistor 28a, and the collector of this transistor 28a is connected to a power supply terminal of Vcc via a resistor 30a. be done.

Furthermore, the signal from the input terminal 21 is transmitted to the inverter 3.
1 and the phase is inverted. This phase-inverted signal is supplied to the control terminal of a constant current source 24b with a current value I, and when the signal is high, this constant current source 24b
The current from b is supplied to capacitor 25b and charged.

Further, the signal from the delay circuit 22 is supplied with phase inversion to the set terminal of the rising edge trigger type SR flip-flop 26b, and the signal from the inverter 31 is supplied to the reset terminal of the flip-flop 26b.

The Q output signal from the flip-flop 26b is supplied to the control terminal of a constant current source 27b with a current value of 2I, and when the signal is high, the capacitor 25b is discharged by the current passing through the constant current source 27b.

The emitter of a transistor 28b is connected to the hot side of this capacitor 25b, the constant voltage source 29 is connected to the base of this transistor 28b, and the collector of this transistor 28b is connected to a resistor 30b.
Connected to the Vcc power supply terminal via.

In the circuits so far, the input terminal 21 has a sixth
When a signal IN with a frequency f=f ₀ and a period T=T ₀ as shown in FIG.
As shown in FIG. B, for example, a signal V _D delayed by a delay time D=3/8T ₀ is taken out. Furthermore, a signal as shown in FIG. 6C is output from the flip-flop 26a.
Q ₁ is taken out.

Constant current source _24a ,
27a is driven to generate currents l ₁ and I ₂ as shown in FIGS. 6D and E, respectively. By charging and discharging with these currents I ₁ and I ₂ , the capacitor 25
The potential V _C1 on the hot side of a is changed as shown in FIG. 6F. Here, the lowest potential of the potential V _C1 is the potential V _BE lower than the potential Vx of the constant voltage source 29,
When the potential V _C1 is higher than this, the transistor 28
a is off, and if it attempts to fall even a little below this level, the transistor 28a turns on and the lowest potential is maintained.

Therefore, the potential V _R1 at the connection point between the collector of the transistor 28a and the resistor 30a becomes high at the rising edge of the input signal IN, and falls at the center of the high period of the delayed signal V _D , as shown in FIG. 6G. be changed.

In other words, the capacitor 25a is charged with the current I during the period when the input signal IN is high, and the charge corresponding to the length of the high period is accumulated.
It is discharged with a current of 2I from the rise of V _D and returned to the original potential at a time corresponding to 1/2 the length of the high period of the input signal IN from the rise of the delay signal V _D.
As a result, a time point delayed by 1/4 period from the rise of the delayed signal V _D is detected.

Similarly, the output signal of flip-flop 26b
Q ₂ becomes as shown in Fig. 6H, and the constant current source 24b,
27b has currents I ₃ and I ₄ as shown in FIG. 6 I and J.
is caused to flow, and the potential on the hot side of the capacitor 25b
V _C2 is changed as shown in FIG. 6K, and a connection point between the collector of the transistor 28b and the resistor 30b is connected with a delay of 1/4 period from the fall of the delayed signal V _D as shown in FIG. 6L. A potential V _R2 having a fall at a time point corresponding to the time point is formed.

In FIG. 5, the potential V _R1 is supplied to the set terminal of the rising edge trigger type SR flip-flop 32 with phase inversion, and the potential V _R2 is supplied to the reset terminal with phase inversion.

As a result, a signal whose phase is shifted by 1/4 period from the delayed signal V _D is outputted to the Q output of the flip-flop 32 as shown in FIG. 6M, and taken out to the output terminal 23B.

Furthermore, in this circuit, the frequency f of the input signal
When f is high and f>f ₀ , the signals at each part become as shown in FIGS. 7A to 7G and M. Ranked 6th
Corresponding to the figure, H to L are omitted.

In this case from the end of charging with current I ₁ the current I ₂
The potential V _C1 is held until the start of discharge.

The condition of this circuit is that there is an interval X between the fall and rise of the potential V _C1 . From this, T-D=T/4+X Assuming X=0, T=4/3D fmax3/4D For example, D3/8T ₀ , T=1/2T ₀ f max = 2f ₀ .

Further, when the frequency f of the input signal is low and f< _f0 , the signals at each part become as shown in FIGS. 8A to 8G and M. The ranking corresponds to FIG. 6, and H to L are omitted.

In this case, the condition is that there is an interval _{Y between the end of charging by current I 1 and the time when potential V C1 reaches the} lowest potential by discharging by current I 2, so that T/2-D+Y=T /4 When Y=0, T=4D f min=1/4D For example, when D=3/8T ₀ , T=3/2T ₀ f min=2/3f ₀ .

In other words, the operating frequency range is 1/4D<f<3/4D, which is three times the frequency range. Here D=
If 3/8T ₀ , then 2/3f ₀ <f<2f ₀ .

Therefore, when used in the above-mentioned FM demodulator, f is
If it exceeds 2f ₀ , no output will be obtained, but for example
In demodulating the FM luminance signal, it is less than this,
Conventionally, at frequencies higher than this, noise was generated due to the aliasing phenomenon, but this possibility is eliminated.
Furthermore, when f is lower than 2/3f ₀ , a pulse is generated, and the phase shift is simply no longer a 1/4 period. For example, if = f1/2f _0, the period will be 3/16. In this case, twice as many unnecessary signals are generated during demodulation, but such low frequencies are almost no longer generated in the FM luminance signal due to pre-emphasis, so there is no practical problem.

In this way, a signal whose phase is shifted by 1/4 period is formed. In this case, the phase-shifted signal is formed by detecting the length of 1/2 of the high period and 1/2 of the low period of the input signal, so that the phase shift signal is instantaneously accurate to 1/4 period. A phase shift is performed, and an accurate phase shift that always follows the input phase can be performed.

Effects of the Invention According to the present invention, it has become possible to eliminate the generation of unnecessary components twice as large as the carrier wave in FM demodulation with a simple configuration.

[Brief explanation of drawings]

Fig. 1 is a block diagram of an example of the present invention, Fig. 2 is a diagram for explaining the same, Fig. 3 is a block diagram of another example, and Fig. 4 is a block diagram of an example of the present invention.
The figure is for explanation, Figures 5 to 8 are 1/4
FIG. 3 is a diagram for explaining a periodic phase shifter. 1...Input terminal, 2 is 1/4 period phase shifter, 3A,
3B and 3C are delay circuits, 4A, 4B and 4C are balanced demodulators, 5 is an adder, 6 is an output terminal, and 7 is a multiplier.

Claims (1)

[Claims] 1. 1/4 period phase shifting means that follows the phase of the input FM signal and outputs two signals having mutually different 1/4 period phases, and responds to the edges of these two signals. a pulse train generating means for generating a pulse train having uniform amplitude and pulse width and a frequency four times that of the FM signal, and a low-pass filter for extracting low frequency components from the output pulse train of the pulse train generating means, In an FM demodulator that demodulates the FM signal, the 1/4 period phase shift means includes a delay circuit that delays the FM signal by a predetermined delay time; a first current source that operates for a predetermined time longer than time; a capacitor that charges the current of the first current source; a second current source that discharges the charge charged in the capacitor by the source at a current value twice that of the first current source; and phase shifting means for outputting a signal phase-shifted by 1/4 period from the FM signal delayed by the delay circuit when detecting discharge by the current source No. 2. FM demodulator.