JPH0536832A - Parallel placement method of logic cells - Google Patents

Abstract

(57) [Abstract] [Purpose] An object of the present invention is to perform a layout improvement process of a plurality of logic cells initially arranged on a semiconductor integrated circuit at high speed and efficiently. [Structure] The layout target area 1 is divided into a plurality of grids by cut lines (dotted lines in the figure). The number of cuts (number in parentheses) for each cut line and the pin dispersion value (number in lattice) for each grid are calculated. The parallel processing area 6 which is a rectangular area having an arbitrary shape including a plurality of cut lines including the cut lines showing the maximum number of cuts (9) and the arbitrary shape including a plurality of grids including the lattice showing the maximum pin dispersion value (10) A parallel processing area 7 which is a rectangular area is set. A method for reducing the number of cuts is used for the area 6, and a method for equalizing the pin distribution values is used for the area 7, and the improvement of the logic cell arrangement in each of the areas 6 and 7 is processed in parallel.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a parallel layout processing method of logic cells in a layout design of a semiconductor integrated circuit.

[0002]

2. Description of the Related Art The number of transistors mounted on a ULSI is increasing at a rate of several times every year due to the improvement of the degree of integration due to the progress of ULSI manufacturing technology, and a megagate class LSI can be realized within a few years. Although it is expected that it will be, there is a strong demand for production in a short period of time. Therefore, the layout CAD must process a large amount of data at high speed.

Up to now, various methods have been proposed for automatic placement, but in most cases, a single CPU is used to perform sequential processing, so that the calculation speed is limited. Multi-CP to increase the calculation speed
An arrangement processing method has also been proposed in which U performs parallel processing to reduce the calculation time.

As a conventional parallel arrangement processing method, a chip is divided into a plurality of rectangular areas by vertical and horizontal lines, each rectangular area is allocated to a processor which is a processing device, and a logical cell is arranged in each rectangular area for each processor. There are ways to improve the condition (J. Rose, W. snelgrove, and Z. Vranesic, "
Parallel Simulated Annealing, "IEEEtrans.Computer A
ided Design, Vol.CAD-7, No.3, Mar.1988, pp.387-396.)
..

However, according to this method, the arrangement state is changed so that only one evaluation item is improved in all the rectangular areas, and therefore the arrangement state is changed also in the rectangular areas which need not be improved. In addition, since the rectangular area of the same shape is set without considering the arrangement state in the rectangular area, the processor allocated to the rectangular area that does not need to be improved may not actually operate, and the parallel effect can be achieved. I'm lowering it.

On the other hand, in the placement of cells, there is a set of cells that should be placed near to some extent in consideration of connection information, timing, etc. A set may be specified.

However, in the conventional parallel arrangement processing method, since all the parallel divided areas are set in a rectangular shape having a constant shape, a set of cells, which should be arranged in the vicinity, is distributed to a plurality of processors. In some cases, it was divided and processed.

In this case, in order to arrange the cells in the set so as to satisfy the arrangement condition, the positions of the cells belonging to the set must be considered among the processors. That is, outside the current rectangle formed by the cells that belong to the set, there is a method of not moving the cells that belong to the set, or when moving the cells that belong to another processor and are connected to the cell. It was necessary to satisfy the conditions for placement, such as by not moving the existing cells at the same time. As a result, the degree of freedom in cell placement is reduced, and the improvement effect of placement is also reduced.

[0009]

As described above, in the conventional parallel arrangement processing method, a rectangular area that does not need to be improved is processed and the effect of parallel operation of processors is reduced. was there.

Further, since a rectangular shape having a constant shape is set in all the parallel division areas, a set of cells which should be arranged in the vicinity is divided into a plurality of processors, and the set is set so that the arrangement condition is satisfied. In order to arrange the cells in the inside, the arrangement positions of the cells belonging to the set must be considered among the processors. Therefore, there is a problem in that the degree of freedom in arranging cells is reduced and the effect of improving the arrangement is also reduced.

In order to solve the above problems, the first
Of the present invention sets a rectangular area of an arbitrary shape for each of several evaluation items as a parallel processing area, and uses an improved method according to each parallel processing area, thereby enabling high-speed and effective parallel placement processing of logic cells. Is intended to do.

The second aspect of the present invention takes into consideration the cell placement conditions when processing in parallel, and assigns a set of cells to be placed in the vicinity to one processor with an arbitrary aspect ratio ( By setting a rectangular area having a rectangular aspect ratio) at an arbitrary position, it is possible to increase the degree of freedom of cell arrangement and obtain an arrangement result at high speed and effectively.

[0013]

In order to solve the above-mentioned problems, a first invention is to divide a layout target area composed of a plurality of logic cells initially arranged on a semiconductor integrated circuit into a plurality of grids, The evaluation values of several evaluation items that represent the arrangement state of each of the grids are obtained for each grid, and a rectangular area of arbitrary shape consisting of multiple grids that requires improvement of the evaluation values of the same evaluation item is set as the parallel processing area. , It is characterized in that the improvement method of the logic cell in each parallel processing area is processed in parallel for all the parallel processing areas by using the improvement method according to the parallel processing area for each evaluation item.

According to the second aspect of the invention, the movement range of the cells in the cell set to be arranged in the vicinity is restricted in the layout target area consisting of a plurality of logic cells initially arranged on the semiconductor integrated circuit. It is characterized by setting a rectangular area including the maximum limit range as a parallel processing area, allocating a plurality of parallel processing areas to different processors, and repeating parallel arrangement.

[0015]

According to the first aspect of the invention, the layout target area in which logic cells are initially arranged is divided into a plurality of grids by cut lines. An evaluation value such as the number of cuts for each cut line, a pin dispersion value for each grid, or a value for overlapping cells is calculated for each grid. A rectangular area of arbitrary shape made up of a plurality of grids that require improvement of the same evaluation value is set as a parallel processing area. By using the improved method according to the parallel processing area for each evaluation value, the placement processing in all the parallel processing areas is performed in parallel.

According to a second aspect of the invention, in the layout target area, a rectangular area including a maximum limit range in which a moving range of cells in a cell set to be arranged in the vicinity is restricted is set as a parallel processing area. .. The plurality of parallel processing areas that have been set are assigned to different processors, and the parallel placement processing is repeated.

[0017]

BEST MODE FOR CARRYING OUT THE INVENTION First Embodiment An embodiment of the parallel arrangement processing method of the first invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing a processing flow in an embodiment of the first invention.

FIG. 2 is a plan view of a semiconductor chip showing the pattern of the gate array used in this embodiment. In the present embodiment, a case will be described in which the layout improvement is performed on the semiconductor chip 3 including the layout target area 1 in which the logic cells are initially arranged and the I / O area 2 arranged around the layout target area 1.

First, as shown in FIG. 3, virtual cut lines 4 are set in advance in both horizontal and vertical directions for the entire layout target area 1 and divided into a plurality of lattices 5 (S1).
Next, the evaluation values such as the pin distribution, the cut distribution, and the overlap between cells are calculated for each grid 5 in the entire layout target area 1 (S2).

Here, the pin distribution is a dispersion value of the number of pins (terminals) in the lattice, the cut distribution is the number of cuts for each cut line, and the overlap between cells is an allowable cell for facilitating the movement of cells during improvement. It is the value of the overlap between each other.

Based on these evaluation values, it is evaluated which part of the layout target area 1 is bad for which evaluation item as shown in FIG. Here, the number in parentheses indicates the number of cuts for each cut line, and the number in the grid indicates the number of pins for each grid.

Based on this evaluation, the layout target area 1
Is divided into two parallel processing regions 6 and 7 along the grid boundary as shown in FIG. 5 (S3). Here, the parallel processing area 6
Is a rectangular area of an arbitrary shape including a horizontal cut line indicating the maximum number of cuts (9), and the parallel processing area 7 is a rectangular area of an arbitrary shape including a grid indicating the maximum value (10) of the pin distribution.

The parallel processing areas 6 and 7 are not limited to this example, and may be rectangular areas of any shape including a horizontal cut line indicating the maximum number of cuts or a grid indicating the maximum value of the pin distribution. It is a thing. However, these parallel processing areas 6 and 7 must not intersect.

Next, the parallel processing areas 6 and 7 are respectively assigned to two processors, and the optimum arrangement method for each area is determined for each processor (S4).
5). Here, it is determined that the parallel processing area 6 executes the layout improving processing for reducing the maximum number of cuts, and the parallel processing area 7 executes the layout improving processing for equalizing the pin distribution values.

Further, the determined layout method is executed, and the layout is improved for each parallel processing area until the evaluation items of interest are converged or a predetermined number of cells are moved (S6). 7).

When the above processing is completed for all the parallel processing areas 6 and 7, the entire layout target area 1 is evaluated again and the convergence judgment is performed. If the convergence is not recognized, it is divided into a plurality of parallel processing areas in the same manner as described above until the convergence, and the determination and execution of the placement improvement processing are repeated for each processor (S2 to 8).

Another embodiment of the first invention will be described below.

Similar to the above embodiment, as shown in FIG. 3, a virtual cut line 4 is set in the horizontal and vertical directions in advance for the entire layout target area 1 and divided into a plurality of lattices 5 (S1). Next, the evaluation values such as the pin distribution, the cut distribution, and the overlap between cells are calculated for each grid 5 in the entire layout target area 1 (S2).

In this embodiment, consider an example in which the same evaluation value is bad over the entire layout target area 1. For example, in FIG. 6A, an example in which the cut distribution value is bad is shown in FIG.
(B) shows an example in which the pin dispersion value is bad. The numbers in parentheses in Fig. 6 (a) are the number of cuts on each cut line, and Fig. 6 (b).
The numbers in the grid indicate the number of pins for each grid.

First, a layout improvement process for improving the evaluation value is determined. In the example of FIG. 6A, the cut distribution equalizing process is selected as the arrangement improving process. This process is a process of reducing the number of cuts by moving a cell connected to a virtual wiring crossing a vertical cut line showing the maximum number of cuts (9) to the opposite side of the cut line.

At this time, since the number of cuts other than those on the vertical cut line is not considered, the range of the three parallel processing areas 8 as shown in FIG. Therefore, a rectangular area as shown in the figure is set as an area in which the effect of this processing is enhanced (S3).

In the example of FIG. 6B, the pin distribution equalizing process is selected as the placement improving process. This process is a process of setting a rectangular area including a pin box (predetermined minimum range of a plurality of grids, for example, 2 × 2) and moving cells from a grid with a large number of pins to a grid with a small number of pins. is there.

At this time, since the cell is not moved to the outside of the rectangular area, the optimum range of moving the cell is the range of the four parallel processing areas 9 as shown in FIG. 7B. Therefore, a rectangular area as shown in the figure is set as an area in which the effect of this processing is enhanced (S3).

Next, the parallel processing areas 8 and 9 set in FIG. 7A or 7B are assigned to three or four processors, respectively, until the evaluation items of interest are converged or determined. The arrangement improving process is executed until the specified number of cell movements are performed (S4 to 7).

When the above processing is completed for all areas, the entire layout target area 1 is evaluated again and a convergence judgment is made (S8). When the convergence is not recognized, the processing is divided into a plurality of parallel processing areas in the same manner as described above until the convergence, and the arrangement improvement processing is determined and executed for each processor repeatedly (S2 to 8).

According to the experiment, when the same cut distribution equalizing process is applied, the case where the improvement process is performed by the conventional method and the case where the improvement process is performed as shown in FIG. The number of cuts decreased by 7% and the maximum number of cuts decreased by 13%.

Second Invention In the present embodiment, when the layout target area 1 of the gate array shown in FIG. 2 is provided with an initial layout, layout improvement processing is performed in parallel to determine a cell layout position. A case will be described.

In the present embodiment, the case where the maximum range in the vertical direction, the horizontal direction, and the (vertical + horizontal) direction is designated as the constraint condition of the set of cells to be arranged in the vicinity will be described. To do. That is, in order that the length of the minimum rectangle formed by the cells belonging to each set in the horizontal direction does not exceed the maximum range as a constraint condition, the length in the vertical direction similarly exceeds the maximum range as a constraint condition. Need to be placed so that there is no.

The same applies when the (horizontal + vertical) length is set as a constraint condition. The present embodiment is also applied to the case where the maximum range in each of the vertical and horizontal directions is not specified and the range in which the cells belonging to the set are arranged as the absolute coordinates on the layout target area 1.

First Embodiment FIG. 8 is a diagram showing a processing flow in the first embodiment of the second invention.

First, the centers of gravity 108 to 111 of the rectangles 104 to 107 formed by the set of cells to be arranged in the vicinity are determined from the given arrangement state as shown in FIG. 9A. The maximum limit positions 112 to 115 are determined in the vertical and horizontal directions centering on the obtained coordinates of the center of gravity, respectively, based on the constraint conditions in the vertical and horizontal directions of each set (S11, S1).
2).

Next, in order to process general cells (cells other than the cell set to be arranged in the vicinity) as well, rectangles 116 to 119 which include the limit position at a minimum are overlapped as parallel arrangement areas. Set so that it does not become (S13),
Assign to each processor. When the parallel area is smaller than the number of processors, areas 120 to 122 that do not overlap the area set above are newly set and assigned to the processors. The parallel arrangement is improved for the area until convergence is achieved for each processor (S14).

Further, in order to improve the general cell, the layout target area 1 is divided into rectangles of a constant shape as shown in FIG. 9B as in the conventional method, and parallel improvement is performed (S1).
5). At this time, as shown in FIG. 9B, a set of cells 104 to 107 to be arranged in the vicinity is a plurality of rectangular regions 123.
There is a case where the cells are divided into ~ 128, but cells having a designation to be arranged in the vicinity are the rectangular areas 123 ~.
The movement is performed so as not to exceed 128, and the movement is repeated until convergence is obtained.

Finally, the convergence judgment is performed on the entire chip, and the above processing is repeated until the convergence is recognized (S1).
6).

Here, an example in which the size difference between the sets of cells to be arranged in the vicinity is small will be described with reference to the first embodiment. As shown in FIG. 10A, in the case where an arrangement such that there is no difference in the size of sets to be arranged in the vicinity is given, each set 12 can be processed according to the conventional parallel processing method.
Even if the partial regions for parallel processing are set in consideration of the rectangles 9 to 134, the region becomes the rectangle 135 having a constant shape, so that it is difficult for all the sets to fit in one region.

According to the present invention, in order to consider the aspect ratio and position of the rectangle of each set based on the processing flow shown in FIG. 8, the rectangle 1 having an arbitrary shape as shown in FIG.
It is possible to set 36 to 147 as parallel regions and allocate each set to one processor. As a result, it is possible to perform parallel processing so that there is no great difference in the amount of information processed by each processor.

Second Embodiment A second embodiment of the second invention will be described below.

First, as a parallel area, a rectangle 148 having a constant shape is set in the layout target area 1 as shown in FIG. At this time, as shown in the figure, when the set of cells to be arranged in the vicinity is divided into a plurality of parallel regions by the parallel region boundaries 149 to 151, the constraint condition of the set range is maximized. The boundary position of the maximum limit range that satisfies the above condition is calculated.

Next, as shown in FIG. 11B, the boundary positions 152 to 154 where the boundaries 149 to 151 of the area are calculated.
The areas are shifted and set, the respective areas are assigned to the respective processors, and the parallel arrangement processing is performed.

Then, the above process is repeated until the entire chip is converged.

[0052]

As described above, according to the parallel layout processing method of the first invention, a rectangular area of an arbitrary shape consisting of a plurality of grids requiring improvement of each evaluation item is set as a parallel processing area, and each parallel processing area is set. Parallel processing is performed by an improved method according to the processing area. Therefore, the parallel effect is high, and the logic cell placement processing time can be shortened.

Further, according to the parallel arrangement processing method of the second invention, the parallel processing area is determined based on the state in which the set of cells is arranged and the constraint condition for the arrangement of the set of cells. The degree of freedom in arranging cells is increased, and it is possible to set a parallel area having a high improvement effect.

[0054]

[Detailed Description of Drawings]

[0055]

FIG. 1 is a flowchart showing a processing procedure of an embodiment relating to a parallel arrangement processing method of the first invention.

[0056]

FIG. 2 is a plan view of a semiconductor chip showing a pattern of a gate array used in an example.

[0057]

FIG. 3 is a plan view of a layout target area in which a grid is set.

[0058]

FIG. 4 is a plan view of a layout target area to which each evaluation value is added.

[0059]

FIG. 5 is a plan view of a layout target area divided into parallel processing areas.

[0060]

FIG. 6 is a plan view of a layout target area having the same overall poor evaluation value.

[0061]

FIG. 7 is a plan view of a layout target area divided into parallel processing areas.

[0062]

FIG. 8 is a flowchart showing an arrangement processing procedure according to the first embodiment of the second invention.

[0063]

FIG. 9 is a diagram showing a parallel area in the first embodiment of the second invention.

[0064]

FIG. 10 is a diagram showing a parallel area in the case where there is no difference in cell set size in the first embodiment.

[0065]

FIG. 11 is a diagram showing a parallel region in a second embodiment of the second invention.

[0066]

[Explanation of symbols]

1 Layout Target Area 2 I / O Area 3 Semiconductor Chip 4 Cut Line 5 Lattice 6-9 Parallel Processing Area 104-107, 129-134 Rectangular Formed by Cell Set 108-111 Rectangular Center of Gravity 112-115 Maximum Limit Range 116- 119 Rectangle including limit arrangement position of set 120 to 122 Parallel region not including cell set 123 to 128 Set rectangle 135 of each parallel region 135, 148 Constant shape rectangle 136 to 147 Arbitrary shape parallel region 149 to 151 Parallel region Boundary 152-154 Boundary of maximum limit range

─────────────────────────────────────────────────── ───

[Procedure amendment]

[Submission date] January 6, 1992

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be amended] Detailed explanation of the invention

[Correction method] Change

[Correction content]

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a parallel layout processing method of logic cells in a layout design of a semiconductor integrated circuit.

[0002]

2. Description of the Related Art The number of transistors mounted on a ULSI is increasing at a rate of several times every year due to the improvement of the degree of integration due to the progress of ULSI manufacturing technology, and a megagate class LSI can be realized within a few years. Although it is expected that it will be, there is a strong demand for production in a short period of time. Therefore, the layout CAD must process a large amount of data at high speed.

Up to now, various methods have been proposed for automatic placement, but in most cases, a single CPU is used to perform sequential processing, so that the calculation speed is limited. Multi-CP to increase the calculation speed
An arrangement processing method has also been proposed in which U performs parallel processing to reduce the calculation time.

As a conventional parallel arrangement processing method, a chip is divided into a plurality of rectangular areas by vertical and horizontal lines, each rectangular area is allocated to a processor which is a processing device, and a logical cell is arranged in each rectangular area for each processor. There are ways to improve the condition (J. Rose, W. snelgrove, and Z. Vranesic, "
Parallel Simulated Annealing, "IEEEtrans.Computer A
ided Design, Vol.CAD-7, No.3, Mar.1988, pp.387-396.)
..

However, according to this method, the arrangement state is changed so that only one evaluation item is improved in all the rectangular areas, and therefore the arrangement state is changed also in the rectangular areas which need not be improved. In addition, since the rectangular area of the same shape is set without considering the arrangement state in the rectangular area, the processor allocated to the rectangular area that does not need to be improved may not actually operate, and the parallel effect can be achieved. I'm lowering it.

On the other hand, in the placement of cells, there is a set of cells that should be placed near to some extent in consideration of connection information, timing, etc. A set may be specified.

However, in the conventional parallel arrangement processing method, since all the parallel divided areas are set in a rectangular shape having a constant shape, a set of cells, which should be arranged in the vicinity, is distributed to a plurality of processors. In some cases, it was divided and processed.

In this case, in order to arrange the cells in the set so as to satisfy the arrangement condition, the positions of the cells belonging to the set must be considered among the processors. That is, outside the current rectangle formed by the cells that belong to the set, there is a method of not moving the cells that belong to the set, or when moving the cells that belong to another processor and are connected to the cell. It was necessary to satisfy the conditions for placement, such as by not moving the existing cells at the same time. As a result, the degree of freedom in cell placement is reduced, and the improvement effect of placement is also reduced.

[0009]

As described above, in the conventional parallel arrangement processing method, a rectangular area that does not need to be improved is processed and the effect of parallel operation of processors is reduced. was there.

Further, since a rectangular shape having a constant shape is set in all the parallel division areas, a set of cells which should be arranged in the vicinity is divided into a plurality of processors, and the set is set so that the arrangement condition is satisfied. In order to arrange the cells in the inside, the arrangement positions of the cells belonging to the set must be considered among the processors. Therefore, there is a problem in that the degree of freedom in arranging cells is reduced and the effect of improving the arrangement is also reduced.

In order to solve the above problems, the first
Of the present invention sets a rectangular area of an arbitrary shape for each of several evaluation items as a parallel processing area, and uses an improved method according to each parallel processing area, thereby enabling high-speed and effective parallel placement processing of logic cells. Is intended to do.

The second aspect of the present invention takes into consideration the cell placement conditions when processing in parallel, and assigns a set of cells to be placed in the vicinity to one processor with an arbitrary aspect ratio ( By setting a rectangular area having a rectangular aspect ratio) at an arbitrary position, it is possible to increase the degree of freedom of cell arrangement and obtain an arrangement result at high speed and effectively.

[0013]

In order to solve the above-mentioned problems, a first invention is to divide a layout target area composed of a plurality of logic cells initially arranged on a semiconductor integrated circuit into a plurality of grids, The evaluation values of several evaluation items that represent the arrangement state of each of the grids are obtained for each grid, and a rectangular area of arbitrary shape consisting of multiple grids that requires improvement of the evaluation values of the same evaluation item is set as the parallel processing area. , It is characterized in that the improvement method of the logic cell in each parallel processing area is processed in parallel for all the parallel processing areas by using the improvement method according to the parallel processing area for each evaluation item.

According to the second aspect of the invention, the movement range of the cells in the cell set to be arranged in the vicinity is restricted in the layout target area consisting of a plurality of logic cells initially arranged on the semiconductor integrated circuit. It is characterized by setting a rectangular area including the maximum limit range as a parallel processing area, allocating a plurality of parallel processing areas to different processors, and repeating parallel arrangement.

[0015]

According to the first aspect of the invention, the layout target area in which logic cells are initially arranged is divided into a plurality of grids by cut lines. An evaluation value such as the number of cuts for each cut line, a pin dispersion value for each grid, or a value for overlapping cells is calculated for each grid. A rectangular area of arbitrary shape made up of a plurality of grids that require improvement of the same evaluation value is set as a parallel processing area. By using the improved method according to the parallel processing area for each evaluation value, the placement processing in all the parallel processing areas is performed in parallel.

According to a second aspect of the invention, in the layout target area, a rectangular area including a maximum limit range in which a moving range of cells in a cell set to be arranged in the vicinity is restricted is set as a parallel processing area. .. The plurality of parallel processing areas that have been set are assigned to different processors, and the parallel placement processing is repeated.

[0017]

BEST MODE FOR CARRYING OUT THE INVENTION First Embodiment An embodiment of the parallel arrangement processing method of the first invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing a processing flow in an embodiment of the first invention.

FIG. 2 is a plan view of a semiconductor chip showing the pattern of the gate array used in this embodiment. In the present embodiment, a case will be described in which the layout improvement is performed on the semiconductor chip 3 including the layout target area 1 in which the logic cells are initially arranged and the I / O area 2 arranged around the layout target area 1.

First, as shown in FIG. 3, virtual cut lines 4 are set in advance in both horizontal and vertical directions for the entire layout target area 1 and divided into a plurality of lattices 5 (S1).
Next, the evaluation values such as the pin distribution, the cut distribution, and the overlap between cells are calculated for each grid 5 in the entire layout target area 1 (S2).

Here, the pin distribution is a dispersion value of the number of pins (terminals) in the lattice, the cut distribution is the number of cuts for each cut line, and the overlap between cells is an allowable cell for facilitating the movement of cells during improvement. It is the value of the overlap between each other.

Based on these evaluation values, it is evaluated which part of the layout target area 1 is bad for which evaluation item as shown in FIG. Here, the number in parentheses indicates the number of cuts for each cut line, and the number in the grid indicates the number of pins for each grid.

Based on this evaluation, the layout target area 1
Is divided into two parallel processing regions 6 and 7 along the grid boundary as shown in FIG. 5 (S3). Here, the parallel processing area 6
Is a rectangular area of an arbitrary shape including a horizontal cut line indicating the maximum number of cuts (9), and the parallel processing area 7 is a rectangular area of an arbitrary shape including a grid indicating the maximum value (10) of the pin distribution.

The parallel processing areas 6 and 7 are not limited to this example, and may be rectangular areas of any shape including a horizontal cut line indicating the maximum number of cuts or a grid indicating the maximum value of the pin distribution. It is a thing. However, these parallel processing areas 6 and 7 must not intersect.

Next, the parallel processing areas 6 and 7 are respectively assigned to two processors, and the optimum arrangement method for each area is determined for each processor (S4).
5). Here, it is determined that the parallel processing area 6 executes the layout improving processing for reducing the maximum number of cuts, and the parallel processing area 7 executes the layout improving processing for equalizing the pin distribution values.

Further, the determined layout method is executed, and the layout is improved for each parallel processing area until the evaluation items of interest are converged or a predetermined number of cells are moved (S6). 7).

When the above processing is completed for all the parallel processing areas 6 and 7, the entire layout target area 1 is evaluated again and the convergence judgment is performed. If the convergence is not recognized, it is divided into a plurality of parallel processing areas in the same manner as described above until the convergence, and the determination and execution of the placement improvement processing are repeated for each processor (S2 to 8).

Another embodiment of the first invention will be described below.

Similar to the above embodiment, as shown in FIG. 3, a virtual cut line 4 is set in the horizontal and vertical directions in advance for the entire layout target area 1 and divided into a plurality of lattices 5 (S1). Next, the evaluation values such as the pin distribution, the cut distribution, and the overlap between cells are calculated for each grid 5 in the entire layout target area 1 (S2).

In this embodiment, consider an example in which the same evaluation value is bad over the entire layout target area 1. For example, in FIG. 6A, an example in which the cut distribution value is bad is shown in FIG.
(B) shows an example in which the pin dispersion value is bad. The numbers in parentheses in Fig. 6 (a) are the number of cuts on each cut line, and Fig. 6 (b).
The numbers in the grid indicate the number of pins for each grid.

First, a layout improvement process for improving the evaluation value is determined. In the example of FIG. 6A, the cut distribution equalizing process is selected as the arrangement improving process. This process is a process of reducing the number of cuts by moving a cell connected to a virtual wiring crossing a vertical cut line showing the maximum number of cuts (9) to the opposite side of the cut line.

At this time, since the number of cuts other than those on the vertical cut line is not considered, the range of the three parallel processing areas 8 as shown in FIG. Therefore, a rectangular area as shown in the figure is set as an area in which the effect of this processing is enhanced (S3).

In the example of FIG. 6B, the pin distribution equalizing process is selected as the placement improving process. This process is a process of setting a rectangular area including a pin box (predetermined minimum range of a plurality of grids, for example, 2 × 2) and moving cells from a grid with a large number of pins to a grid with a small number of pins. is there.

At this time, since the cell is not moved to the outside of the rectangular area, the optimum range of moving the cell is the range of the four parallel processing areas 9 as shown in FIG. 7B. Therefore, a rectangular area as shown in the figure is set as an area in which the effect of this processing is enhanced (S3).

Next, the parallel processing areas 8 and 9 set in FIG. 7A or 7B are assigned to three or four processors, respectively, until the evaluation items of interest are converged or determined. The arrangement improving process is executed until the specified number of cell movements are performed (S4 to 7).

When the above processing is completed for all areas, the entire layout target area 1 is evaluated again and a convergence judgment is made (S8). When the convergence is not recognized, the processing is divided into a plurality of parallel processing areas in the same manner as described above until the convergence, and the arrangement improvement processing is determined and executed for each processor repeatedly (S2 to 8).

According to the experiment, when the same cut distribution equalizing process is applied, the case where the improvement process is performed by the conventional method and the case where the improvement process is performed as shown in FIG. The number of cuts decreased by 7% and the maximum number of cuts decreased by 13%.

Second Invention In the present embodiment, when the layout target area 1 of the gate array shown in FIG. 2 is provided with an initial layout, layout improvement processing is performed in parallel to determine a cell layout position. A case will be described.

In the present embodiment, the case where the maximum range in the vertical direction, the horizontal direction, and the (vertical + horizontal) direction is designated as the constraint condition of the set of cells to be arranged in the vicinity will be described. To do. That is, in order that the length of the minimum rectangle formed by the cells belonging to each set in the horizontal direction does not exceed the maximum range as a constraint condition, the length in the vertical direction similarly exceeds the maximum range as a constraint condition. Need to be placed so that there is no.

The same applies when the (horizontal + vertical) length is set as a constraint condition. The present embodiment is also applied to the case where the maximum range in each of the vertical and horizontal directions is not specified and the range in which the cells belonging to the set are arranged as the absolute coordinates on the layout target area 1.

First Embodiment FIG. 8 is a diagram showing a processing flow in the first embodiment of the second invention.

First, the centers of gravity 108 to 111 of the rectangles 104 to 107 formed by the set of cells to be arranged in the vicinity are determined from the given arrangement state as shown in FIG. 9A. The maximum limit positions 112 to 115 are determined in the vertical and horizontal directions centering on the obtained coordinates of the center of gravity, respectively, based on the constraint conditions in the vertical and horizontal directions of each set (S11, S1).
2).

Next, in order to process general cells (cells other than the cell set to be arranged in the vicinity) as well, rectangles 116 to 119 which include the limit position at a minimum are overlapped as parallel arrangement areas. Set so that it does not become (S13),
Assign to each processor. When the parallel area is smaller than the number of processors, areas 120 to 122 that do not overlap the area set above are newly set and assigned to the processors. The parallel arrangement is improved for the area until convergence is achieved for each processor (S14).

Further, in order to improve the general cell, the layout target area 1 is divided into rectangles of a constant shape as shown in FIG. 9B as in the conventional method, and parallel improvement is performed (S1).
5). At this time, as shown in FIG. 9B, a set of cells 104 to 107 to be arranged in the vicinity is a plurality of rectangular regions 123.
There is a case where the cells are divided into ~ 128, but cells having a designation to be arranged in the vicinity are the rectangular areas 123 ~.
The movement is performed so as not to exceed 128, and the movement is repeated until convergence is obtained.

Finally, the convergence judgment is performed on the entire chip, and the above processing is repeated until the convergence is recognized (S1).
6).

Here, an example in which the size difference between the sets of cells to be arranged in the vicinity is small will be described with reference to the first embodiment. As shown in FIG. 10A, in the case where an arrangement such that there is no difference in the size of sets to be arranged in the vicinity is given, each set 12 can be processed according to the conventional parallel processing method.
Even if the partial regions for parallel processing are set in consideration of the rectangles 9 to 134, the region becomes the rectangle 135 having a constant shape, so that it is difficult for all the sets to fit in one region.

According to the present invention, in order to consider the aspect ratio and position of the rectangle of each set based on the processing flow shown in FIG. 8, the rectangle 1 having an arbitrary shape as shown in FIG.
It is possible to set 36 to 147 as parallel regions and allocate each set to one processor. As a result, it is possible to perform parallel processing so that there is no great difference in the amount of information processed by each processor.

Second Embodiment A second embodiment of the second invention will be described below.

First, as a parallel area, a rectangle 148 having a constant shape is set in the layout target area 1 as shown in FIG. At this time, as shown in the figure, when the set of cells to be arranged in the vicinity is divided into a plurality of parallel regions by the parallel region boundaries 149 to 151, the constraint condition of the set range is maximized. The boundary position of the maximum limit range that satisfies the above condition is calculated.

Next, as shown in FIG. 11B, the boundary positions 152 to 154 where the boundaries 149 to 151 of the area are calculated.
The areas are shifted and set, the respective areas are assigned to the respective processors, and the parallel arrangement processing is performed.

Then, the above process is repeated until the entire chip is converged.

[0052]

As described above, according to the parallel layout processing method of the first invention, a rectangular area of an arbitrary shape consisting of a plurality of grids requiring improvement of each evaluation item is set as a parallel processing area, and each parallel processing area is set. Parallel processing is performed by an improved method according to the processing area. Therefore, the parallel effect is high, and the logic cell placement processing time can be shortened.

Further, according to the parallel arrangement processing method of the second invention, the parallel processing area is determined based on the state in which the set of cells is arranged and the constraint condition for the arrangement of the set of cells. The degree of freedom in arranging cells is increased, and it is possible to set a parallel area having a high improvement effect.

[Procedure Amendment 2]

[Document name to be amended] Statement

[Name of item to be corrected] Brief explanation of the drawing

[Correction method] Change

[Correction content]

[Brief description of drawings]

FIG. 1 is a flowchart showing a processing procedure of an embodiment relating to a parallel arrangement processing method of the first invention.

FIG. 2 is a plan view of a semiconductor chip showing a pattern of a gate array used in an example.

FIG. 3 is a plan view of a layout target area in which a grid is set.

FIG. 4 is a plan view of a layout target area to which each evaluation value is added.

FIG. 5 is a plan view of a layout target area divided into parallel processing areas.

FIG. 6 is a plan view of a layout target area having the same overall poor evaluation value.

FIG. 7 is a plan view of a layout target area divided into parallel processing areas.

FIG. 8 is a flowchart showing an arrangement processing procedure according to the first embodiment of the second invention.

FIG. 9 is a diagram showing a parallel area in the first embodiment of the second invention.

FIG. 10 is a diagram showing a parallel area in the case where there is no difference in cell set size in the first embodiment.

FIG. 11 is a diagram showing a parallel region in a second embodiment of the second invention.

[Explanation of Codes] 1 Layout target area 2 I / O area 3 Semiconductor chip 4 Cut line 5 Lattice 6-9 Parallel processing area 104-107, 129-134 Rectangle formed by cell set 108-111 Rectangle centroid 112-115 Maximum limit range 116 to 119 Rectangle including limit arrangement position of set 120 to 122 Parallel region not including cell set 123 to 128 Set rectangle of each parallel region 135, 148 Constant shape rectangle 136 to 147 Arbitrary shape parallel region 149 〜 151 Boundary for parallel area 152 〜 154 Boundary for maximum limit range

Claims (2)

[Claims] 1. A layout target area composed of a plurality of logic cells initially arranged on a semiconductor integrated circuit is divided into a plurality of grids, and respective evaluation values of a plurality of evaluation items representing the arrangement state of the logic cells are divided into respective grids. Obtained for each grid, set a rectangular area of arbitrary shape consisting of multiple grids that require improvement of the evaluation value in the same evaluation item as the parallel processing area,
A parallel arrangement of logic cells characterized by processing the arrangement of logic cells in each parallel processing area in parallel for all parallel processing areas by using an improved method according to the parallel processing area for each evaluation item. Processing method. 2. A maximum limit range in which a movement range of cells in a cell set to be arranged in the vicinity is constrained in a layout target area composed of a plurality of logic cells initially arranged on a semiconductor integrated circuit. A parallel arrangement processing method of logic cells, characterized in that a rectangular area is set as a parallel processing area, a plurality of parallel processing areas are allocated to different processors, and parallel arrangement is repeated.