JPH0541362A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH0541362A JPH0541362A JP19626591A JP19626591A JPH0541362A JP H0541362 A JPH0541362 A JP H0541362A JP 19626591 A JP19626591 A JP 19626591A JP 19626591 A JP19626591 A JP 19626591A JP H0541362 A JPH0541362 A JP H0541362A
- Authority
- JP
- Japan
- Prior art keywords
- film
- electrode
- polycrystalline silicon
- refractory metal
- polycide
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Landscapes
- Electrodes Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
(57)【要約】
【目的】 ポリサイドなどの積層構造による電極,配線
を有する半導体装置に関し,ある程度の膜厚を持ちつ
つ,後工程での平坦化の要求も満たす積層構造の電極,
配線構造を提供することを目的とする。
【構成】 半導体基板1上に多結晶シリコン膜3と高融
点金属シリサイド膜4を順次積層する工程と, 高融点金
属シリサイド膜4及び多結晶シリコン膜3を電極形状に
パターニングする工程と, パターニングされた高融点金
属シリサイド膜4及び多結晶シリコン膜3を熱処理し
て, 断面が凸型のポリサイド電極2を形成する工程とを
含むように構成する。
(57) [Abstract] [Purpose] Regarding a semiconductor device having electrodes and wirings having a laminated structure such as polycide, an electrode having a laminated structure which has a certain film thickness and satisfies the requirement of planarization in a later step,
An object is to provide a wiring structure. [Structure] A step of sequentially stacking a polycrystalline silicon film 3 and a refractory metal silicide film 4 on a semiconductor substrate 1, a step of patterning the refractory metal silicide film 4 and the polycrystalline silicon film 3 into an electrode shape, and patterning The refractory metal silicide film 4 and the polycrystalline silicon film 3 are heat-treated to form a polycide electrode 2 having a convex cross section.
Description
【0001】[0001]
【産業上の利用分野】本発明は,半導体集積回路装置の
カバー膜の構造とその製造方法に関する。近年の半導体
装置の高集積化,微細化にともない,半導体装置におけ
る処理スピードを高速化する為,配線遅延などをなくす
必要があり,配線抵抗を極力下げることが要求されてい
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of a cover film of a semiconductor integrated circuit device and a manufacturing method thereof. With the recent trend toward higher integration and miniaturization of semiconductor devices, it is necessary to eliminate wiring delays in order to increase the processing speed in semiconductor devices, and it is required to reduce wiring resistance as much as possible.
【0002】この為,従来の多結晶シリコン膜の配線に
代わって,配線抵抗が低くできるポリサイド構造の配線
が一般的に使用されるようになっている。Therefore, in place of the conventional polycrystalline silicon film wiring, a polycide structure wiring, which can reduce the wiring resistance, is generally used.
【0003】[0003]
【従来の技術】図3は従来例の説明図である。図におい
て,13はシリコン(Si)基板, 14はフィールド二酸化シリ
コン(SiO2)膜, 15はゲートSiO2膜, 16は多結晶シリコン
(ポリSi) 膜, 17はタングステンシリサイド(WSi2)膜,
18はポリサイドゲート電極, 19はソース・ドレイン拡散
層である。2. Description of the Related Art FIG. 3 is an explanatory view of a conventional example. In the figure, 13 is a silicon (Si) substrate, 14 is a field silicon dioxide (SiO 2 ) film, 15 is a gate SiO 2 film, and 16 is polycrystalline silicon.
(Poly-Si) film, 17 is a tungsten silicide (WSi 2 ) film,
18 is a polycide gate electrode, and 19 is a source / drain diffusion layer.
【0004】従来の積層構造の電極,配線は,図3に示
すように,単にポリSi膜16とWSi2膜17等のシリサイド材
料の積層によって形成しており,熱処理によってポリサ
イド電極18を形成する時にも, 特に,熱ストレスによる
断面形状の変形などは考慮していなかった。As shown in FIG. 3, electrodes and wirings of a conventional laminated structure are simply formed by laminating a silicide material such as a poly-Si film 16 and a WSi 2 film 17, and a polycide electrode 18 is formed by heat treatment. Even at this time, in particular, deformation of the cross-sectional shape due to heat stress was not considered.
【0005】ところが,近年の半導体装置の高集積化,
微細化にともない,電極,配線材料を薄膜化しないと後
工程での平坦化に対して厳しくなってきている。However, high integration of semiconductor devices in recent years,
Along with the miniaturization, if the electrode and wiring materials are not thinned, it will become difficult to flatten in the subsequent process.
【0006】[0006]
【発明が解決しようとする課題】従って,電極や配線の
抵抗を下げるために,或る程度の厚さが必要であるとい
う要求と,後工程での平坦化を考えて膜厚を薄くしたい
という要求があり,トレードオフ(相反する)関係とな
っている。Therefore, in order to reduce the resistance of electrodes and wirings, it is necessary to have a certain thickness, and it is desired to reduce the film thickness in consideration of flattening in the subsequent process. There are demands and there is a trade-off (conflicting) relationship.
【0007】本発明は,上記問題を解決する為,ある程
度の膜厚を持ちつつ,後工程での平坦化の要求も満たす
ためアスペクト比を小さくした積層構造の電極,配線構
造を提供することを目的とする。In order to solve the above problems, the present invention provides an electrode / wiring structure having a laminated structure having a small film thickness and a small aspect ratio in order to satisfy the requirement of flattening in a subsequent process. To aim.
【0008】[0008]
【課題を解決するための手段】図1は本発明の原理説明
図である。図において,1は半導体基板,2は断面が凸
型のポリサイド電極,3はポリSi膜,4は高融点金属シ
リサイド膜である。FIG. 1 illustrates the principle of the present invention. In the figure, 1 is a semiconductor substrate, 2 is a polycide electrode having a convex cross section, 3 is a poly-Si film, and 4 is a refractory metal silicide film.
【0009】図1に示すように,配線構造の断面は凸型
に湾曲している。湾曲の程度は,積層構造を形成する際
の成長条件,膜厚,及び,後工程での熱処理条件,酸化
条件などにより最適化することができる。As shown in FIG. 1, the wiring structure has a convexly curved cross section. The degree of curvature can be optimized depending on the growth conditions and film thickness when forming the laminated structure, and the heat treatment conditions and oxidation conditions in the subsequent process.
【0010】即ち,本発明の目的は,半導体基板1上に
断面が凸型のポリサイド電極2を形成する半導体装置の
製造方法であって,図1(a)に示すように,該半導体
基板1上に多結晶シリコン膜3と高融点金属シリサイド
膜4を順次積層する工程と,図1(b)に示すように,
該高融点金属シリサイド膜4,及び,該多結晶シリコン
膜3を電極形状にパターニングする工程と,図1(c)
に示すように,パターニングされた該高融点金属シリサ
イド膜4,及び,該多結晶シリコン膜3を熱処理して,
断面が凸型のポリサイド電極2を形成する工程とを含む
ことにより達成される。That is, an object of the present invention is to provide a method of manufacturing a semiconductor device in which a polycide electrode 2 having a convex cross section is formed on a semiconductor substrate 1. As shown in FIG. As shown in FIG. 1B, a step of sequentially laminating the polycrystalline silicon film 3 and the refractory metal silicide film 4 on the upper surface,
A step of patterning the refractory metal silicide film 4 and the polycrystalline silicon film 3 into an electrode shape, and FIG.
As shown in FIG. 3, the patterned refractory metal silicide film 4 and the polycrystalline silicon film 3 are heat-treated,
And the step of forming a polycide electrode 2 having a convex cross section.
【0011】[0011]
【作用】本発明では,積層電極のパターニング後,熱処
理によって,ポリサイド構造の電極,配線の断面構造が
凸型に湾曲するので,ポリサイドの膜厚がある程度厚く
ても,後工程での平坦化に対して,非常に有利な形状と
なっている。According to the present invention, the cross-sectional structure of the electrodes and wirings of the polycide structure is convexly curved by heat treatment after patterning the laminated electrodes. Therefore, even if the polycide film is thick to some extent, it can be flattened in a later step. In contrast, it has a very advantageous shape.
【0012】[0012]
【実施例】図2は本発明の一実施例の工程順模式断面図
である。図において5はSi基板,6はフィールドSiO
2膜,7はゲートSiO2膜,8はポリSi膜,9はWSi2膜, 1
0は断面が凸型のポリサイド電極, 11はソース・ドレイ
ン拡散層, 12はカバーPSG 膜である。FIG. 2 is a schematic sectional view in order of the steps of an embodiment of the present invention. In the figure, 5 is a Si substrate, 6 is a field SiO
2 film, 7 is a gate SiO 2 film, 8 is a poly-Si film, 9 is a WSi 2 film, 1
0 is a polycide electrode with a convex cross section, 11 is a source / drain diffusion layer, and 12 is a cover PSG film.
【0013】本発明の一実施例について,図2により工
程順に説明する。図2(a)に示すように,通常の方法
で 150Åの厚さのゲートSiO2膜7まで形成されたSi基板
5上に, ポリSi膜8をCVD法により,基板温度 620
℃, シラン(SiH4)ガス 150 sccm をプロセスガスとして
用いて, 真空度 0.2Torrで500 Åの厚さに被覆する。An embodiment of the present invention will be described in the order of steps with reference to FIG. As shown in FIG. 2 (a), a poly-Si film 8 is formed on the Si substrate 5 on which a gate SiO 2 film 7 having a thickness of 150 Å is formed by a normal method by a CVD method at a substrate temperature of 620
Silica (SiH 4 ) gas of 150 sccm was used as a process gas at a temperature of 500 ° C and a vacuum of 0.2 Torr to coat a thickness of 500 Å.
【0014】続いて, SiH4 ガスを 400 sccm,六弗化タ
ングステン(WF6) ガスを 10 sccmの二元系のプロセスガ
スを用い, 基板温度 360℃, 真空度 350mTorr の条件
で, ポリSi膜8上にWSi2膜9を 300 Åの厚さに積層す
る。Then, using a binary process gas of 400 sccm of SiH 4 gas and 10 sccm of tungsten hexafluoride (WF6) gas, a poly-Si film 8 was formed under the conditions of a substrate temperature of 360 ° C. and a vacuum degree of 350 mTorr. A WSi 2 film 9 is laminated on top of it to a thickness of 300 Å.
【0015】次に, 図2(b)に示すように,レジスト
膜をマスクとして,RIE法による異方性エッチングに
より,WSi2膜9を塩素(Cl2) ガス60sccm, 真空度5mTor
r,μ波出力2kW,RF出力70Wの条件で,続いて,ポ
リSi膜8を酸素(O2)ガス10sccm, 真空度5mTorr, μ波
出力2kW,RF出力70Wの条件でパターニングし,電
極形状を形成する。Next , as shown in FIG. 2 (b), the WSi 2 film 9 is anisotropically etched by the RIE method using the resist film as a mask to etch the WSi 2 film 9 with chlorine (Cl 2 ) gas at 60 sccm and a vacuum degree of 5 mTor.
Electrode shape was obtained by patterning the poly-Si film 8 under conditions of r, μ wave output 2 kW and RF output 70 W, then oxygen (O 2) gas 10 sccm, vacuum degree 5 mTorr, μ wave output 2 kW, RF output 70 W. Form.
【0016】続いて,図2(c)に示すように,窒素(N
2)ガス 雰囲気中,850 ℃で60分間の熱処理を行い,断
面が凸型のポリサイド電極10を形成してゲート電極とす
る。その後, 通常の方法により, 図2(d)に示すよう
に,イオン注入法により,砒素イオン (As+ ) を加速電
圧40 keV, ドーズ量4x1015/cm2の条件で注入し,850 ℃
で20分の活性化アニールを行いソース・ドレイン拡散層
11を形成する。Then, as shown in FIG. 2 (c), nitrogen (N
2) Heat treatment at 850 ° C for 60 minutes in a gas atmosphere to form a polycide electrode 10 with a convex cross section to form a gate electrode. Then, as shown in Fig. 2 (d), arsenic ions (As + ) were implanted by an ordinary method under the conditions of an accelerating voltage of 40 keV and a dose of 4x10 15 / cm 2 at 850 ° C.
Source / drain diffused layer
Forming 11.
【0017】図2(e)に示すようにカバーPSG膜12
を 4,000Åの厚さに被覆する。As shown in FIG. 2E, the cover PSG film 12
To a thickness of 4,000Å.
【0018】[0018]
【発明の効果】この結果, ゲート電極の膜厚が多少厚く
ても, その断面が凸型(蒲鉾型) のため,抵抗が低く,
しかも, アスペクト比率が小さく,カバーPSG膜12に
対して, 被覆段差による障害の起こらないゲート電極が
形成でき, 高集積半導体デバイスの開発に寄与するとこ
ろが大きい。As a result, even if the film thickness of the gate electrode is slightly thick, the resistance is low because the cross section is convex (kamaboko).
Moreover, the aspect ratio is small, and a gate electrode can be formed on the cover PSG film 12 that does not cause any obstacle due to the step difference of the coating, which greatly contributes to the development of highly integrated semiconductor devices.
【図面の簡単な説明】[Brief description of drawings]
【図1】 本発明の原理説明図FIG. 1 is an explanatory view of the principle of the present invention.
【図2】 本発明の一実施例の工程順模式断面図2A to 2C are schematic cross-sectional views in order of the processes of an embodiment of the present invention.
【図3】 従来例の説明図FIG. 3 is an explanatory diagram of a conventional example.
1 半導体基板 2 断面が凸型のポリサイド電極 3 ポリSi膜 4 高融点金属シリサイド膜 5 Si基板 6 フィールドSiO2膜 7 ゲートSiO2膜 8 ポリSi膜 9 WSi2膜 10 断面が凸型のポリサイド電極 11 ソース・ドレイン拡散層 12 カバーPSG 膜DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Polycide electrode having a convex cross section 3 Poly Si film 4 Refractory metal silicide film 5 Si substrate 6 Field SiO 2 film 7 Gate SiO 2 film 8 Poly Si film 9 WSi 2 film 10 Polycide electrode having a convex cross section 11 Source / drain diffusion layer 12 Cover PSG film
Claims (1)
イド電極(2) を形成する半導体装置の製造方法であっ
て, 該半導体基板(1) 上に多結晶シリコン膜(3) と高融点金
属シリサイド膜(4) を順次積層する工程と, 該高融点金属シリサイド膜(4) 及び,該多結晶シリコン
膜(3)を電極形状にパターニングする工程と, パターニングされた該高融点金属シリサイド膜(4) 及
び,該多結晶シリコン膜(3) を熱処理して, 断面が凸型
のポリサイド電極(2) を形成する工程とを含むことを特
徴とする半導体装置の製造方法。1. A method of manufacturing a semiconductor device, wherein a polycide electrode (2) having a convex cross section is formed on a semiconductor substrate (1), comprising: a polycrystalline silicon film (3) on the semiconductor substrate (1); A step of sequentially depositing a refractory metal silicide film (4), a step of patterning the refractory metal silicide film (4) and the polycrystalline silicon film (3) into an electrode shape, and the patterned refractory metal A method of manufacturing a semiconductor device, comprising a step of heat-treating the silicide film (4) and the polycrystalline silicon film (3) to form a polycide electrode (2) having a convex cross section.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19626591A JPH0541362A (en) | 1991-08-06 | 1991-08-06 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19626591A JPH0541362A (en) | 1991-08-06 | 1991-08-06 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0541362A true JPH0541362A (en) | 1993-02-19 |
Family
ID=16354934
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19626591A Withdrawn JPH0541362A (en) | 1991-08-06 | 1991-08-06 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0541362A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006032410A (en) * | 2004-07-12 | 2006-02-02 | Matsushita Electric Ind Co Ltd | Semiconductor device and manufacturing method thereof |
| JP2008166361A (en) * | 2006-12-27 | 2008-07-17 | Sony Corp | Semiconductor element, solid-state imaging device, and imaging device |
| WO2011158400A1 (en) * | 2010-06-17 | 2011-12-22 | パナソニック株式会社 | Semiconductor device and method for manufacturing same |
-
1991
- 1991-08-06 JP JP19626591A patent/JPH0541362A/en not_active Withdrawn
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006032410A (en) * | 2004-07-12 | 2006-02-02 | Matsushita Electric Ind Co Ltd | Semiconductor device and manufacturing method thereof |
| US7973367B2 (en) | 2004-07-12 | 2011-07-05 | Panasonic Corporation | Semiconductor device and manufacturing method thereof |
| US8242567B2 (en) | 2004-07-12 | 2012-08-14 | Panasonic Corporation | Semiconductor device and manufacturing method thereof |
| JP2008166361A (en) * | 2006-12-27 | 2008-07-17 | Sony Corp | Semiconductor element, solid-state imaging device, and imaging device |
| WO2011158400A1 (en) * | 2010-06-17 | 2011-12-22 | パナソニック株式会社 | Semiconductor device and method for manufacturing same |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A300 | Withdrawal of application because of no request for examination |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 19981112 |