JPH0544829B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a new chip-on-chip structure in an LSI.

ICs are becoming smaller and more highly integrated, such as LSI and VLSI, because higher integration has the advantage of improved operating characteristics such as high-speed operation.

However, there is a limit to miniaturization, and the resulting drop in chip yield has become noticeable. Therefore, if a chip (hereinafter referred to as a semiconductor chip is simply referred to as a chip) is made larger with higher integration and a large number of fine elements are formed, the chip yield will drop significantly. In order to prevent this drop in yield and further promote higher integration, there are currently mounting structures in which multiple relatively small chips are housed in a package to increase the degree of integration. A structure has been devised in which the package cages are stacked three-dimensionally.

On the other hand, in terms of devices, an SOI structure is being considered in which a semiconductor layer is formed on an insulating film using laser annealing, an element is created on the semiconductor layer, and these are stacked to create a three-dimensional structure. The SOI structure is currently considered to be the most highly integrated and high-performance structure, but there are many unresolved problems with these three-dimensional devices, and they have not yet been put into practical use or mass-produced. It is.

However, the higher the integration, the higher the performance, so there is currently a demand for high integration and miniaturization as much as possible using mounting technology that allows easy fabrication.

[Prior Art] FIG. 5 shows the above-mentioned relatively small chip, e.g.
This shows an example of a structure in which multiple chips of approximately 10 mm square and 200 μm thick are housed in a package. In this example, two chips 1 are mounted in a package 2, and wires are bonded from each chip to the package. This is an example in which wiring is performed, and such a structure is currently the most easily practical highly integrated mounting structure.

[Problems to be solved by the invention] However, the structure shown in Figure 5 is almost similar to the conventional structure in which two packages each carrying one chip are combined, and the mounting area is slightly smaller. However, there is not much difference from the conventional structure in which two packages are arranged in parallel. That is, the package becomes larger and the structure cannot be said to be highly integrated or highly dense.

In addition, the structure in which packages are stacked three-dimensionally as explained in the "Industrial Application Field" above is different from the conventional one.
The structure is simply a stack of package cages each carrying individual chips, and there needs to be a gap between them, so it cannot be said that this is highly integrated or highly dense. Not too much.

On the other hand, a structure in which only chips are stacked three-dimensionally is being considered, but this is a structure in which through-holes are provided inside or on the periphery of the chips, and these through-holes connect the chips one above the other.
Forming through holes in a 300 μm thick chip substrate is extremely difficult from a device perspective, and is far from practical use.

The present invention proposes a semiconductor device that can be easily manufactured using current device technology and has a structure that allows for high integration and high density.

[Means for solving the problem] The problem is that a plurality of semiconductor chips are bonded and stacked together, and the size of the semiconductor chip that is stacked on the upper layer is miniaturized, and wiring is placed around the surface of the semiconductor chip. The problem is solved by a semiconductor device in which the plurality of semiconductor chips are exposed, the side surfaces of the plurality of semiconductor chips are shaped like steps, and wirings are provided in the stepped portions to connect the upper and lower surface wirings of the exposed semiconductor chips. Ru.

For example, the adhesive for bonding the semiconductor chip may be an organic resin, the surface wiring of the exposed semiconductor chip may be polycrystalline silicon, and the wiring connecting the upper and lower surfaces of the semiconductor chip may be aluminum, or A semiconductor device having the above structure is constructed using an aluminum alloy.

[Function] That is, in the present invention, a plurality of semiconductor chips are bonded and stacked using an adhesive. In addition, the semiconductor chips are made smaller toward the upper layer, and the surface wiring is exposed on all four sides or on two sides of the chip, so that the side surfaces of the plurality of chips are shaped like steps, and the surface wiring of the plurality of semiconductor chips is interconnected in the stepped portion. Provide wiring to connect between the two.

Such a structure is formed by depositing or sputtering one side of the stepped surface facing the electrode material, and then exposing it to light in the same manner to form wiring on the stepped surface without the risk of disconnection. be able to.

Therefore, the semiconductor device according to the present invention can be extremely densely packed, the package can be made smaller, and the degree of integration can be improved.

[Examples] Hereinafter, examples will be described in detail with reference to the drawings.

FIG. 1 shows a sectional view of a ceramic package type semiconductor device as an embodiment of the semiconductor device according to the present invention.
A, 3b, 3c are stacked, and the lower layer chip 3
The chip a is the largest, the chip 3c in the upper layer is the smallest, and the chip 3b in the middle is intermediate in size.

Chip 3c and chip 3b are bonded together with epoxy resin 4, and similarly chip 3b and chip 3a are bonded together.
Both are glued together with epoxy resin 4. Since this bonding can be done at room temperature, there is no need to worry about changing the IC characteristics within the chip, which is extremely convenient.

In this way, the sides are shaped like zigzag steps, but the cover insulating film is removed to expose the wiring on the chip surface that protrudes from the chip adhered to the upper layer, and the wiring on the chip surface can be connected to the top and bottom. The wires 5 are connected at the stepped side surfaces. Such a connection can be easily formed as described later.

The three-layer chips thus laminated are adhered to a ceramic package 10 with epoxy resin 6, and the lower chip 3a and the package are bonded and connected with wire 11.

With such a structure, even if a plurality of chips are stacked, the package will not become very large, allowing for extremely high integration and density. For example, if the three chips above are stacked, the thickness will be 0.5
mm x 3 = approximately 1.5 mm. Therefore, even if 10 chips are stacked, the thickness is at most 0.5 mm x 10 chips = 5 mm. Here, the thickness of 0.5 mm is the thickness of the chip, which is 0.2 to 0.3 mm, plus the adhesive resin.

FIG. 2 shows a partial perspective view of a plurality of stacked chips, in which 7 is wiring on the exposed surface of the chip made of polycrystalline silicon, and 5 is vertical connection wiring on the side surface of the chip made of aluminum. In this way, the wiring material exposed on the chip surface and the upper and lower connection wiring materials on the side surface of the chip are made of different materials.
This is because the side wiring can be patterned independently of the wiring on the chip surface.

Next, to explain the wiring method on the side of the chip, first, the insulating cover film was removed to expose the polycrystalline silicon wiring 7 on the chip surface, and all the required number of such chips were bonded with epoxy resin 4. After that, place the side surface facing the evaporation material and make a film with a thickness of 1 μm.
Aluminum of about m is vapor-deposited. Next, a resist film is applied thereon and exposed to light to form a resist film pattern 12 (see FIG. 3). In this case as well, the side surfaces of the plurality of chips are opposed to the mask and the light source. FIG. 3 shows the evaporation direction and the exposure direction for forming upper and lower connection wiring on a plurality of chips, and the arrows indicate the directions. Next, using the resist film pattern as a mask, excess aluminum is removed by etching with phosphoric acid (polycrystalline silicon is not etched), and the connection wiring on the side surface is finished.

At this time, the polycrystalline silicon wiring 7 provided on the chip surface is formed finely, but a sufficient area margin is taken on the side surface, and the aluminum wiring 5 to be created is wide and has a wide gap, for example, 100 μm in width.
m, a wiring pattern with a gap of about 1 mm is formed. In this way, a pattern with no risk of wire breakage can be formed even on a step-like surface with many irregularities as described above. Therefore, the present invention has a mounting structure that can be easily implemented.

Next, FIG. 4 shows a sectional view of a plastic mold type semiconductor device as another embodiment of the present invention, in which 13 is a lead frame, 14
is a mold (indicated by a dotted line), and such a mold type is of course possible.

Note that in the semiconductor device having the structure according to the present invention, elements and circuits that generate a large amount of heat are constructed in the bottom layer chip and the top layer chip to improve heat dissipation. For example, in a memory IC, peripheral circuits that generate a large amount of heat are provided in the bottom layer chip and the top layer chip.

[Effects of the Invention] As is clear from the above explanation, according to the present invention, LSIs and VLSIs with extremely highly integrated packaging structures can be realized.
is obtained, which is highly effective in improving circuit performance.

[Brief explanation of drawings]

1 and 4 are cross-sectional views of a semiconductor device according to the present invention, FIG. 2 is a partial perspective view thereof, and FIG. 3 is a method of forming the same, showing the evaporation direction and exposure direction for forming upper and lower connection wirings. FIG. 5 is a perspective view of a conventional highly integrated semiconductor device. In the figure, 1 is a conventional package, 2 is a conventional chip, 3a, 3b, 3c are stacked chips,
4 is an epoxy resin for bonding between stacked chips, 5 is an upper and lower connection wiring made of aluminum, 6 is an epoxy resin for bonding the chips to a package, 7 is a polycrystalline silicon wiring on the surface of the chip, 10 is a package , 11 is a wire, 12 is a resist film pattern 13 is a lead frame, 14
indicates a mold.

Claims (1)

[Scope of Claims] 1 A plurality of semiconductor chips are sequentially bonded and stacked, and the semiconductor chips stacked in the upper layer are made smaller in size, and wiring is exposed around the surface of the semiconductor chip, and the plurality of semiconductor chips are 1. A semiconductor device characterized in that a side surface of a semiconductor chip is shaped like a step, and a wire connecting upper and lower surfaces of the exposed surface wire of the semiconductor chip is provided in the step-like portion. 2. The adhesive for bonding the semiconductor chip is an organic resin, the surface wiring of the exposed semiconductor chip is polycrystalline silicon, and the wiring connecting the upper and lower surfaces of the semiconductor chip is aluminum or aluminum. The semiconductor device according to claim 1, characterized in that the semiconductor device is made of an alloy.