JPH0544851B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a high voltage circuit having an output stage of CMOS configuration.

[Prior art and its problems]

Conventionally, a circuit as shown in FIG. 2 is known as a high voltage circuit having an output stage of a CMOS configuration. In FIG. 2, 20 is a control signal input terminal, 21 is a high voltage power supply terminal, 22 is a reference potential application terminal, 23 is a high voltage output terminal, 24 is a high voltage capacitor, 25 is a resistor, and 26 is a high voltage PMOS transistor. , 27 are high voltage NMOS transistors. This PMOS transistor 26 and NMOS transistor 27 constitute a high voltage inverter.

In the high voltage circuit configured as described above, considering the case where the input signal to the input terminal 20 is periodic, the voltage is determined by the capacitor 24 and the resistor 25.
The CR time constant needs to be sufficiently larger than the period of the signal input to the input terminal 20. Therefore, the capacitance value of the capacitor 24 and the resistance value of the resistor 25 must be selected in accordance with the input signal. On the other hand, if the input signal is not periodic, for example direct current, and has little change, and the time between signal change points is long, the charge stored in the capacitor 24 will be discharged, so the PMOS transistor 2
6 is turned off regardless of the input signal to the control signal input terminal 20, causing a malfunction of the high voltage CMOS inverter composed of MOS transistors 26 and 27.

Conventional high-voltage circuits with CMOS-configured output stages have the disadvantage of malfunctioning in response to non-periodic signals with little variation, and in the case of input capacitance and resistance values in response to periodic signals. It has the disadvantage that selection must be made in accordance with the signal.

Therefore, the inventor of the present invention has proposed a circuit as shown in FIG. 3 as a high-voltage circuit that improves upon such drawbacks. This circuit is a high-voltage integrated circuit with an output stage in a CMOS configuration, in which an N-well is formed on a P-type substrate, a PMOS high-voltage transistor is fabricated in the N-well, and a high-voltage NMOS transistor is fabricated in the P-type substrate region. It is a circuit.

This high voltage circuit includes an output stage with a CMOS configuration consisting of a PMOS transistor 1 and an NMOS transistor 2, a bistable element 3 consisting of two sets of inverters and having an output that is logically the same as the input, and a high voltage capacitor 4. We are prepared. capacitor 4
One end of the capacitor 4 is connected to the control signal input terminal 5, and the other end of the capacitor 4 is connected to the input terminal 6 of the bistable element 3. Output terminal 7 of bistable element 3 is PMOS
Connected to the gate of transistor 1. The control signal input terminal 5 is also connected to the gate of the NMOS transistor 2.

The bistable element 3 is composed of a high voltage PMOS transistor 8, a high voltage PMOS transistor 9, and two resistors 10 and 11. The input terminal 6 of the bistable element is connected to the gate of the PMOS transistor 8, and the output terminal 7 is connected to the PMOS transistor 8. They are connected to the drains of transistors 9, respectively. Also, the gate of PMOS transistor 8 is connected to the drain of PMOS transistor 9, and the gate of PMOS transistor 9 is connected to
Connected to the drain of PMOS transistor 8. The sources of these MOS transistors 8 and 9 are connected to a high voltage terminal 12, and the drains are connected to a voltage application terminal 13 via resistors 10 and 11, respectively.

The high voltage power supply terminal 12 is further connected to the source of the PMOS transistor 1, the connection point between the drain of the PMOS transistor 1 and the drain of the NMOS transistor 2 is connected to the high voltage output terminal 14, and the source of the NMOS transistor 2 is connected to the reference It is connected to the potential application terminal 15.

A voltage of, for example, 200V is applied to the high voltage power supply terminal 12, and a voltage of, for example, 0V is applied to the reference potential application terminal 15.
voltage is applied. A signal of, for example, 10V is input to the control signal input terminal 5, and a voltage of, for example, 190V is input to the voltage application terminal 13, which is lower than the voltage of 200V at the high voltage power supply terminal 12 by the amplitude voltage of the input signal at the control signal input terminal 5. A voltage is applied.

In this high voltage circuit, the control signal input terminal 5
When a 10V input signal is applied to the NMOS transistor 2, the state immediately changes from off to on. On the other hand, the input signal is transmitted to the input terminal 6 of the bistable element 3 via the high voltage capacitor 4. This turns off the PMOS transistor 8 and turns on the PMOS transistor 9. As a result, the input signal is latched, and a signal in phase with the latched signal is output to the output terminal 7 of the bistable element 3. This signal is
It is applied to the gate of the PMOS transistor 1, which turns off the transistor 1 and the voltage at the output terminal 14 of the high voltage circuit becomes 0V.

Conversely, when the input signal is no longer applied to the control signal input terminal 5, the NMOS transistor 2 is turned off.
On the other hand, the state of bistable element 3 is reversed and the PMOS
Transistor 1 turns on and high voltage output terminal 1
4 outputs a voltage of 200V.

According to such a high voltage circuit, the bistable element 3
The input signal to the control signal input terminal 5 is latched by the latched input signal, and the PMOS transistor 1 is turned on and off by the latched input signal. Even if the capacitor 4 is discharged during this period, the CMOS inverter can operate normally as long as it has a capacitance value that can invert the bistable element 3. Furthermore, even if the input signal is periodic, the capacitance value of the high voltage capacitor 4 only needs to have a capacitance value necessary for inverting the state of the bistable element 3, regardless of the input signal. , it becomes unnecessary to select the CR time constant in accordance with the input signal as in the high voltage circuit shown in FIG.

However, in the high voltage circuit shown in FIG. 3, the NMOS transistor is turned on and off for the time required for the bistable element to latch the input signal to the control signal input terminal, that is, for the state of the bistable element to be inverted.
There is a delay in turning off and turning on the PMOS transistor. Therefore, the NMOS transistor changes from OFF to ON immediately by the input signal to the control signal input terminal 5, but the PMOS transistor changes from ON to OFF with a delay of the state inversion time of the bistable element. Therefore, during this period, both transistors of the CMOS inverter made up of PMOS transistor 1 and NMOS transistor 2 are turned on. Therefore, although the high voltage circuit shown in FIG. 3 has improved the drawbacks of the high voltage circuit shown in FIG. 1, it has a new drawback in that the power consumption is larger than that of an ideal CMOS circuit.

[Purpose of the invention]

An object of the present invention is to provide a high voltage circuit including a bistable element that operates with low power consumption by eliminating the period in which both the load transistor and the drive transistor of the high voltage output section are on. .

[Structure of the invention]

The present invention provides a high voltage circuit having an output stage of a complementary circuit including a load transistor and a drive transistor, in which a capacitor and an input terminal are connected between a control signal input terminal of the complementary circuit and a gate of the load transistor. comprising a series circuit with a bistable element having logically the same output, one terminal of the capacitor being connected to the control signal input terminal;
The output terminal of the bistable element is connected to the gate of the load transistor, and further a delay circuit is provided between the control signal input terminal and the gate of the drive transistor to provide a delay equal to the state inversion time of the bistable element. It is characterized by being prepared.

〔Example〕

FIG. 1 is a circuit diagram showing one embodiment of the present invention. This high voltage circuit is the high voltage circuit shown in FIG. 3 in which a CR delay circuit 16 is provided between the control signal input terminal 5 and the gate of the NMOS transistor 2, and the other configuration is the same as that shown in FIG. Since the circuits are exactly the same, the same elements are given the same numbers. This delay circuit 16 provides a time delay equal to the state inversion time of the bistable element 3, and in this embodiment, two capacitors 17,
18 and one resistor 19. The control signal input terminal 5 is connected to one end of a capacitor 17 and a resistor 19, and the other end of the resistor 19 is connected to one end of a capacitor 18.
The other end is connected to the other end of the capacitor 18. One end of the capacitor 18 is connected to the gate of the NMOS transistor 2, and the other end of the capacitor 18 is connected to the reference potential application terminal 15.

By providing this delay circuit 16,
The time when PMOS transistor 1 changes state and
It becomes possible to match the time when the state of the NMOS transistor 2 changes. Therefore, during the state reversal of bistable element 3, PMOS transistor 1
This can prevent both the NMOS transistor 2 and the NMOS transistor 2 from turning on. Therefore, the output stage of the high voltage circuit shown in FIG. 1 can perform ideal CMOS operation.

In the above embodiments, a CMOS circuit with an N-well structure has been explained as an example, but a CMOS circuit with a P-well structure has been described.
It is clear that the present invention can be similarly implemented with a CMOS circuit. Furthermore, regarding the delay circuit, the present invention can be implemented using not only the CR delay circuit shown in FIG. 1 but also a delay circuit having a configuration similar to that of the bistable element 3 in FIG. 1.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to obtain a high voltage circuit without ineffective power consumption in the high voltage output stage.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an example of a high voltage circuit according to the present invention, FIG. 2 is a diagram showing a conventional high voltage circuit, and FIG. 3 is a diagram showing a high voltage circuit improved from the circuit in FIG. 2. 1, 8, 9, 26...High voltage PMOS transistor, 2,27...High voltage NMOS transistor,
3... Bistable element, 4, 24... High voltage capacitor, 5, 20... Control signal input terminal, 6... Input terminal of bistable element, 7... Output terminal of bistable element, 10, 11, 19,25...Resistance, 12,2
1... High voltage power supply terminal, 13... Voltage application terminal,
14, 23...High voltage output terminal, 15, 22...
Reference potential application terminal, 16... Delay circuit, 17, 1
8... Capacitor.

Claims (1)

[Claims] 1. In a high voltage circuit having an output stage of a complementary circuit consisting of a load transistor and a drive transistor, a capacitor is connected between the control signal input terminal of the complementary circuit and the gate of the load transistor, and the output stage is connected logically to the input. a series circuit with a bistable element having the same output, one terminal of the capacitor being connected to the control signal input terminal, an output terminal of the bistable element being connected to the gate of the load transistor; A high voltage circuit comprising a delay circuit that provides a delay equal to the state inversion time of the bistable element between a control signal input terminal and the gate of the drive transistor.