JPH054747B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a video disc player that plays back a video signal from a video disc having a recording track on which the video signal is recorded. The present invention relates to a synchronous control device that serves to achieve the desired results.

BACKGROUND ART AND PROBLEMS A video signal is rotated on a video disk on which a spiral recording track is recorded, for example, in the form of an array of pits, and an optical reading means is made to follow the recording track. In a video disc player that obtains a read signal by using The synchronization control to make the video disc a predetermined one is performed by controlling the motor that rotates the video disc around the rotation shaft to control the rotation of the video disc. The motor that rotates this video disk is usually a DC servo motor.
It is called a spindle motor (hereinafter, the motor that rotationally drives the video disk will be referred to as a spindle motor).

When a reproduced video signal obtained by such a videodisc player is supplied to a monitor receiver that is externally synchronized from the perspective of the videodisc player to obtain a reproduced image, it is necessary to It is necessary to synchronize the vertical and horizontal synchronization signals in the reproduced video signal, ie, the reproduced vertical and horizontal synchronization signals, to external vertical and horizontal synchronization signals, respectively, such as the vertical and horizontal synchronization signals that operate the monitor receiver. In such a case, in a conventional video disc player, the phase difference between the external vertical synchronization signal and the reproduced vertical synchronization signal is first detected, and the spindle motor is activated based on the detected phase difference. As a result of this control, vertical phase servo control is performed so that the phase difference between the external vertical synchronization signal and the reproduced vertical synchronization signal is maintained at zero or a predetermined relatively small phase difference. Then, while the phase difference between the external vertical sync signal and the reproduced vertical sync signal is maintained at zero or a predetermined relatively small phase difference, the phase difference between the external horizontal sync signal and the reproduced horizontal sync signal is The comparison output controls the spindle motor and switches to a horizontal phase servo control so that the external horizontal synchronization signal and the reproduced horizontal synchronization signal are in the same phase. In this way, the vertical phase servo control state and the horizontal phase servo control state are taken sequentially, and in the horizontal phase servo control state, the reproduced vertical and horizontal synchronization signals are synchronized with the external vertical and horizontal synchronization signals. .

However, such conventional video discs
For external synchronization control in a player, the servo control state for the spindle motor must be changed, and the steady phase difference between the external vertical synchronization signal and the reproduced vertical synchronization signal must be reduced to zero. Or to a predetermined relatively small phase difference,
Therefore, a synchronization control device in a video disc player that performs external synchronization control must be equipped with various auxiliary circuits for these switching operations or steady phase difference maintenance operations. This has the disadvantage that it ends up having a complicated configuration.

Purpose of the Invention In view of the above, the present invention has a relatively simple configuration when obtaining a read signal from a video disk and reproducing the video signal from the obtained read signal. The horizontal synchronization signal can be reliably synchronized with external vertical and horizontal synchronization signals. An object of the present invention is to provide a synchronization control device for a video disc player.

Summary of the Invention A synchronization control device for a video disc player according to the present invention includes a synchronization separation unit that generates a playback vertical synchronization signal and a playback horizontal synchronization signal obtained from a read signal from a rotationally driven video disc, and an external horizontal synchronization unit. a phase comparison section that compares the phase of the signal and the reproduced horizontal synchronization signal; a pulse generation section; and a pulse generation section that causes the pulse generation section to send out a pulse signal according to the phase difference between the external vertical synchronization signal and the reproduction vertical synchronization signal. The pulse control section is supplied with the output and pulse signal of the above-mentioned phase comparison section, and controls the rotation of the video disk based on the output of the phase comparison section, and also controls the rotation of the video disk based on the pulse signal. and a drive control section that moves a stable point of control based on the output of the phase comparison section with respect to the motion,
The reproduced horizontal synchronizing signal and the reproduced vertical synchronizing signal are synchronized with the external horizontal synchronizing signal and the external vertical synchronizing signal, respectively. By doing this, it is possible to switch from the vertical phase servo control state to the horizontal phase servo control state regarding the rotation control of the video disk, which is done in the conventional synchronization control device, and to change the external vertical synchronization signal and playback vertical There is no need to strictly maintain a steady phase difference with the synchronization signal, and the configuration is therefore simplified.

Embodiments Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows an example of a synchronization control device for a video disc player according to the present invention. An example of this is a video disc that plays back video and audio signals from a video disc on which a modulated audio signal is recorded together with a modulated video signal.
This is an example applied to a player, in which a signal recorded on a rotationally driven video disk is read by a pickup 1, which is an optical reading means or the like, and a read signal Sr is obtained from the pickup 1. The read signal Sr is amplified to a predetermined level by an amplifier circuit 2, further shaped into a predetermined waveform by a waveform shaping circuit 3, and then supplied to a filter circuit 4. The filter circuit 4 separates the modulated audio signal Sa and the modulated video signal _Sv from the waveform-shaped output of the read signal Sr and derives them separately. The modulated audio signal Sa and the modulated video signal _Sv are respectively supplied to an audio demodulation circuit 5 and a video demodulation circuit 6 and demodulated, and a reproduced audio signal SA is obtained from the audio demodulation circuit 5. A reproduced video signal SV is obtained from the circuit 6 and is led out to terminals 7 and 8, respectively.

The reproduced video signal SV is also passed through the synchronization separation circuit 9
The vertical synchronization signal and horizontal synchronization signal in the reproduced video signal SV, that is, the reproduced vertical synchronization signal _Fv and the reproduced horizontal synchronization signal are also supplied from the synchronization separation circuit 9.
F _H is obtained.

On the other hand, an external horizontal synchronizing signal F _HO is supplied from the terminal 10, and this external horizontal synchronizing signal F _HO and the reproduced horizontal synchronizing signal F _H obtained from the synchronization separation circuit 9 are supplied to the phase comparison circuit 11 for phase comparison. Ru. A comparison output
3 and the adder circuit 14 to the drive control circuit 15. The drive control circuit 15 controls the rotation of the spindle motor 16 according to the comparison output X, thereby controlling the rotation of the video disk, _so that the comparison output It is made so that it is obtained when the signal F _H is in the same phase. That is, the drive control circuit 15 controls the rotation of the spindle motor 16 in accordance with the comparison output X from the phase comparison circuit 11.
Servo control is performed to synchronize the reproduction horizontal synchronization signal _FH with the external horizontal synchronization signal _FHO .

Further, an external vertical synchronizing signal _FVO is supplied from the terminal 17, and this external vertical synchronizing signal _FVO , together with the reproduced vertical synchronizing signal _FV from the synchronization separation circuit 9,
It is supplied to the pulse control section 18. Pulse control section 1
8 is external vertical synchronization signal F _VO and reproduction vertical synchronization signal
The phase difference between the two control signals Q ₁ and Q ₂ is generated according to the detected phase difference, and is supplied to the pulse generation circuit 19 _. Pulse generation circuit 1
9 generates a pulse signal P 1 having a polarity determined by the control signal Q ₁ from the pulse control unit 18 and a frequency fp determined by the control signal Q ₂ from _the pulse control unit 18; is supplied to the drive control circuit 15 via the addition circuit 14, and
A pulse signal P ₂ having a constant polarity synchronized with the pulse signal P ₁ is generated and supplied to the control terminal of the switch 12 .

When the pulse signal P ₂ is supplied to the control end of the switch 12, the switch 12 is turned off, and the comparison output X from the phase comparison circuit 11 just before this is held by the capacitor 13. Therefore, at this time, the pulse signal P ₁ is superimposed on the comparison output X held in the capacitor 13 and supplied to the drive control circuit 15 . The drive control circuit 15 changes the rotation of the spindle motor 16 every time the pulse signal _P1 is supplied.
If P ₁ is positive polarity, the playback horizontal sync signal
F _H causes a phase shift in the leading direction of the phase amount corresponding to the period of the external horizontal synchronization signal F _HO , that is, one horizontal period (hereinafter, the horizontal period is referred to as H), and the pulse signal P ₁ has a negative polarity. If so, control is performed so that the reproduced horizontal synchronizing signal F _H causes a phase shift in the delay direction by a phase amount corresponding to 1H. Then, when the supply of the pulse signal P ₁ to the drive control circuit 15 ends, at the same time, the supply of the pulse signal P ₂ to the control end of the switch 12 also ends, and the switch 12 is turned on, and the spindle motor 16 is turned on.
A servo control state is entered in which the rotation of is controlled according to the comparison output X from the phase comparator circuit 11.
Therefore, the stable point in the servo control, where the rotation of the spindle motor 16 is controlled based on the comparison output X, is moved every time the pulse signal _P1 is supplied to the drive control circuit 15. Therefore, for each pulse signal P ₁ , the phase of the reproduced horizontal synchronization signal F _H with respect to the external horizontal synchronization signal F _HO shifts in the leading direction or lags by a phase amount equivalent to 1H. It turns out.

The pulse control unit 18 that causes the pulse generation circuit 19 to generate such a pulse signal is configured such that, for example, the reproduced vertical synchronization signal _FV is compared with the external vertical synchronization signal _FVO .
When the phase is delayed by a phase amount equal to or more than 0.5H, the control signal Q ₁ is set so that the polarity of the pulse signal P ₁ is positive, and the control signal Q ₂
Assume that the frequency fp of the pulse signal _P1 is set to a predetermined value. In addition, when the reproduced vertical synchronization signal F _V is in a phase leading by a phase amount equivalent to 0.5H or more compared to the external vertical synchronization signal F _VO , the control signal Q ₁ is
The polarity of the pulse signal P ₁ is set to be negative, and the control signal Q ₂ is set to set the frequency fp of the pulse signal P ₁ to a predetermined value. Further, when the phase difference between the reproduced vertical synchronization signal F _V and the external vertical synchronization signal F _VO is smaller than the phase amount corresponding to 0.5H, the control signals Q ₁ and Q ₂ are pulsed to the pulse generation circuit 19. Signals P ₁ and P ₂ shall not be transmitted.

Then, the reproduced vertical synchronization signal F _V is delayed in phase by more than a phase amount equivalent to 0.5H compared to the external vertical synchronization signal F _{V O} , and the pulse signal P ₁ is generated with positive polarity and is generated at the same time. When supplied to the drive control circuit 15 with the switch 12 turned off by the pulse signal _P2 , the phase of the reproduced horizontal synchronization signal _FH changes by _1H for each pulse signal P1.
It is shifted in the direction of progress. Along with this,
The reproduced vertical synchronization signal F _V causes a phase lead,
The phase difference between the reproduced vertical synchronization signal _FV and the external vertical synchronization signal _FVO is reduced. Then, when the phase difference between the two becomes smaller than the phase amount equivalent to 0.5H,
This is detected by the pulse control section 18, and the pulse signals _P1 and _P2 are no longer obtained, resulting in a servo control state in which the comparison output X from the phase comparison circuit 11 is supplied to the drive control circuit 15 via the switch 12. As a result, the reproduced horizontal synchronizing signal F _H is synchronized with the external horizontal synchronizing signal F _HO and the synchronization state _is maintained. It is synchronized with the synchronization signal _FVO , and the synchronized state is maintained.

In addition, the reproduced vertical synchronization signal F _V is in a phase lead of more than the phase amount equivalent to 0.5H compared to the external vertical synchronization signal F _VO , and the pulse signal P ₁ is generated with negative polarity and is generated at the same time. When supplied to the drive control circuit 15 with the switch 12 turned off by the pulse signal _P2 , the phase of the reproduced horizontal synchronizing signal _FH is shifted in the delay direction by 1H for each pulse signal _P1 . It will be done. Along with this, the reproduced vertical synchronizing signal F _V gradually lags in phase, and the phase difference between the reproduced vertical synchronizing signal F _V and the external vertical synchronizing signal F _VO decreases. Then, when the phase difference between the two becomes smaller than the phase amount equivalent to 0.5H,
Similarly to the above, this is detected by the pulse control section 18, and the pulse signals _P1 and _P2 are no longer obtained, and as a result, the comparison output X from the phase comparison circuit 11 is supplied to the drive control circuit 15 via the switch 12. The reproduction horizontal synchronization signal F _H is in a servo control state with respect to the external horizontal synchronization signal F HO, and the reproduction vertical synchronization signal F _V is in a synchronization state with respect to the external vertical synchronization signal F _{VO .}
The synchronization state will be maintained.

Of course, if the phase difference between the reproduced vertical synchronization signal F _V and the external vertical synchronization signal F _VO is smaller than the phase amount corresponding to 0.5H from the beginning, the pulse signals P ₁ and P ₂ from the pulse generation circuit 19 are Therefore, a servo control state is maintained in which the comparison output X from the phase comparison circuit 11 is supplied to the drive control circuit 15 via the switch 12, and the reproduced horizontal synchronization signal F _H
The extended playback vertical synchronization signal F _V is the external horizontal synchronization signal
It is synchronized with _FHO and external vertical synchronization signal _FVO , respectively.

Note that in the example shown in _FIG . The signal is supplied to the drive control circuit 15, thereby controlling the speed of the spindle motor 16.

As described above, according _to the synchronization control device for a video disc player according to the present invention shown in _{FIG .} A state in which each of them is synchronized with the horizontal synchronization signal _FHO is reliably maintained.

Next, the details of the above-mentioned pulse control section 18 that controls the pulse signals P ₁ and P ₂ will be described by way of example. FIG. 2 shows a specific example of the pulse control section 18 .

In the example of FIG. 2, an external vertical synchronization signal _FVO is supplied to terminal 31. Here, the external vertical synchronization signal F _VO is 2 as shown in FIG. 3A.
It is a frame synchronization signal that arrives every vertical period (hereinafter, vertical period is referred to as V), and each synchronization signal F _VO is
It is said to have a width equivalent to 3H. In Fig. 3, a certain synchronization signal
Time T ₁ when a period equivalent to 0.5H has elapsed from the leading edge of F _VO , and time T ₂ when a period equivalent to 1/5 of 1V has elapsed.
and 1V have elapsed, and furthermore, _a time point _T4 is shown which is about 1/5 of 1V before the leading edge of the next synchronizing signal _FVO , and also from the leading edge of the next synchronizing signal _FVO . Time point _T5 is shown in front by a period corresponding to 0.5H. Further, the terminal 32 is supplied with a reproduced vertical synchronization signal _FV . This playback vertical sync signal
F _V is also a frame synchronization signal and is 3H in normal condition.
It is assumed that the width is equivalent to . The synchronizing signal _FVO and the synchronizing signal _FV are supplied to the set terminal S and the reset terminal R of a set/reset flip-flop (hereinafter referred to as "set/reset-FF") 33, respectively.
The FF 33 is set at the leading edge of the synchronizing signal _FVO and reset at the leading edge of the synchronizing signal _FV that arrives thereafter,
At its output end, there is a signal U ₀ that takes a high level h during the period from the leading edge of the synchronizing signal F _VO to the leading edge of the synchronizing signal F _V that arrives thereafter, and takes a low level l during the other periods.
occurs.

The signal U ₀ from the set/reset-FF 33 is supplied to the enable terminal EN of the counter 34, and the counter 34 operates during the period when the signal U ₀ takes the high level h.
Counting is performed based on the clock pulse CL supplied to the clock terminal C. Then, the count output N ₀ at each count of the counter 34
is five digital comparators 35, 36, 37,
It is supplied to one input end of each of 38 and 39. At the other input terminal of each of the digital comparators 35 to 39, the count in the counter 34 is
_{The count values N 1} , N ₂ , _{N 3 ,} N _{4 and N5} is
are supplied respectively, and the digital comparators 35~
39, the count output _N0 from the counter 34 is compared with each of the count values _N1 to _N5 . The output signals U ₁ , U ₂ , U ₃ , U ₄ and U ₅ of these digital comparators 35 to 39 are as follows:
When N ₀ is N ₁ or more, N ₀ is N ₂ or more, N ₀ is N ₃ or more, N ₀ is N ₄ or more, and N ₀ is N ₅ or more, it is “1”, and otherwise it is “0”. ” becomes.

The output signals U ₁ and U ₂ are sent to the exclusive OR circuit 40, the output signals U ₂ and U ₃ are sent to the exclusive OR circuit 41, and the output signal U ₃ is sent to the exclusive OR circuit 40.
_U4 is supplied to the exclusive OR circuit 42, and output signals _U4 and _U5 are supplied to the exclusive OR circuit 43, respectively. At the output terminal, a signal U ₆ that becomes “0” or “1”,
U ₇ , U ₈ and U ₉ are obtained respectively. Additionally, signal U ₆
and U ₇ are sent to the OR circuit 44, signals U ₇ and U ₈ are sent to the OR circuit 45, signals U ₆ and U ₉ are sent to the OR circuit 46,
are supplied with OR circuits 44, 45 and 46, respectively.
Signals U ₁₀ , U ₁₁ and U ₁₂ which are “0” or “1” are obtained at the output terminals of each of them, respectively, and the signal U ₁₀ is guided to the output terminal 47.

Further, a control signal q 1 that changes the frequency fp of the pulse signal P ₁ generated from the pulse generation circuit 19 to a relatively high frequency fh, and a control signal q ₂ that changes the frequency fp of the pulse signal P ₁ to a relatively low frequency _fl . , respectively, are provided with control signal sources 48 and 49 that generate the control signal q ₁ and the signal U ₁₁ , and the control signal q ₁ and the signal U 11 are supplied to the AND circuit 50, and the control signal q 2 and the signal U ₁₂ are supplied to the AND circuit 51. Ru. The AND circuit 50 derives a control signal q ₁ to its output terminal when the signal U ₁₁ is “1”,
Further, the AND circuit 51 derives the control signal q ₂ at its output terminal when the signal U ₁₂ is "1". The control signals q ₁ and q ₂ obtained at the output terminals of these AND circuits 50 and 51 are passed through an OR circuit 52 to an output terminal 5.
3 is derived.

For example, as shown in FIG. 3B, the reproduction vertical synchronization signal F _V has a leading edge time T at
the state arriving to be located between T ₂ and T ₃ ,
In other words, the reproduced vertical synchronization signal F _v is the external vertical synchronization signal.
In a state where the phase is delayed by a much larger phase amount than the phase amount equivalent to 0.5H compared to the signal _FVO , the external vertical synchronization signal is output from the set/reset FF33 as shown in FIG. A signal that takes a high level h for a period t from the leading edge of F _VO to time T
U ₀ is obtained and the counter 34 is counted during this period t. Then, the count output N ₀ is larger than the count values N ₁ and N ₂ and smaller than N ₃ to _{N 5} , so that the output signals U ₁ and U ₂ are “1”.
Therefore, the output signals U ₃ to _{U 5} become “0”. As a result, among the signals _U6 to _U9 , only _U7 becomes "1" and the others become "0". Therefore, the signals U ₁₀ to _{U 12}
Among them, U ₁₀ and U ₁₁ become “1”, U ₁₂ becomes “0”, and a “1” signal is output from the output terminal 47.
U ₁₀ is sent out as the control signal Q ₁ of the pulse controller 18, and the control signal q ₁ from the control signal source 48 is
is sent out from the output terminal 53 as the control signal Q ₂ of the pulse control section 18, and both are supplied to the pulse generation circuit 19. When these “1” signal U ₁₀ and control signal q ₁ are supplied, a pulse signal P 1 having positive polarity and a relatively high frequency fh is obtained from the pulse generation circuit 19, and furthermore, a pulse signal P ₁ having a positive polarity and a relatively high frequency fh is obtained.
A pulse signal P ₂ synchronized with P ₁ is obtained.

In addition, a state in which the leading edge time point T of the reproduced vertical synchronizing signal F _V is located between time points T ₁ and T ₂ , that is, the reproduced vertical synchronizing signal F _{V is} 0.5 In a state where the phase is delayed by a phase amount that is larger than the phase amount corresponding to H, but not much larger, the count output N ₀ is greater than the count value N ₁ and N ₂
~N will be smaller than ₅ . As a result, only _U6 among the signals _U6 to _U9 becomes "1" and the others become "0".
Therefore, among the signals _U10 to _U12 , _U10 and _U12 become "1" and _U11 becomes "0", and the output terminal 4
A signal U ₁₀ of “1” from 7 is sent out as a control signal Q ₁ , and a control signal q ₂ from a control signal source 49 is sent out as a control signal Q 1 .
is sent out from the output terminal 53 as a control signal Q ₂ and both are supplied to the pulse generation circuit 19 .
When these “1” signal U ₁₀ and control signal q ₂ are supplied, a pulse signal P ₁ having a positive polarity and a relatively low frequency fl is obtained from the pulse generation circuit 19, and furthermore, a pulse signal P ₁ having a positive polarity and a relatively low frequency fl is obtained. A pulse signal _P2 synchronized with is obtained.

Similarly, time T of the leading edge of the reproduced vertical synchronization signal F _V is between time T ₃ and T ₄ or between time T ₄ and
_T5 , that is, the reproduced vertical synchronization signal _FV is in an advanced phase with respect to the external vertical synchronization signal _FVO by a much larger phase amount than the phase amount equivalent to 0.5H, or In a state where the phase amount is greater than, but not much larger than, the phase amount corresponding to 0.5H, the signals U ₁₀ to _{U 12} are, respectively,
Only U ₁₁ becomes "1" and U ₁₀ and U ₁₂ become "0", or only signal U ₁₂ becomes "1"
U ₁₀ and U ₁₁ become "0", and the "0" signal U ₁₀ is sent out from the output terminal 47 as the control signal Q ₁ ,
Further, the control signal q ₁ or the control signal q ₂ is sent out from the output terminal 53 as the control signal Q ₂ ,
Both are supplied to the pulse generation circuit 19. These “0” signal U ₁₀ and control signal q ₁ , or
When the “0” signal U ₁₀ and the control signal q ₂ are supplied, the pulse generation circuit 19 generates a pulse signal P ₁ having a negative polarity and a relatively high frequency fh, or a negative polarity and a relatively low frequency fh. A pulse signal P ₁ with a frequency fl is obtained, and furthermore, such a pulse signal
A pulse signal P ₂ synchronized with P ₁ is obtained.

Furthermore, the time T of the leading edge of the reproduced vertical synchronization signal F _V
is between the leading edge of the external vertical synchronization signal F _VO and the time T ₁ ,
Alternatively, the state located between time T ₅ and the leading edge of the next external vertical synchronization signal F _VO , i.e., the phase difference between the reproduced vertical synchronization signal F _V and the external vertical synchronization signal F _VO
In a state where the phase amount is smaller than 0.5H,
The count output _N0 is smaller than or larger than any of the count values _N1 to _N5 , and therefore the output signals _U1 to _U5 are all "0" or all are "1". As a result, signal U ₆
- U ₉ all become "0", and all signals U ₁₀ - _{U 12} also become "0". Therefore, the signal U ₁₀ of "0" is sent from the output terminal 47, but neither the control signals q ₁ nor q ₂ are sent from the output terminal 53. That is, the control signal _Q2 cannot be obtained from the pulse control section 18, and in this case, the pulse generation circuit 1
Neither pulse signal P ₁ nor P ₂ can be obtained from 9.

Effects of the Invention As is clear from the above description, according to the synchronization control device for a video disc player according to the present invention, the synchronization control device for a video disc player according to the present invention has the following functions that were necessary in the conventional synchronization control device.
In spindle motor servo control, switching from a servo control state based on vertical synchronization signal phase detection to a servo control state based on horizontal synchronization signal phase detection, and external vertical synchronization signal and reproduction vertical synchronization It is possible to reliably synchronize the reproduced vertical and horizontal synchronizing signals with the external vertical and horizontal synchronizing signals, respectively, without having to strictly maintain the steady phase difference between the signals at a predetermined value. Furthermore, since there is no need to switch the servo control state or maintain a steady phase difference between the external vertical synchronization signal and the reproduced vertical synchronization signal as described above, the circuit configuration can be simplified accordingly. Note that the pulse generation circuit, pulse control section, etc. can be easily integrated into an integrated circuit, and by integrating these into an integrated circuit, there is an advantage that the circuit configuration can be further simplified.

[Brief explanation of the drawing]

FIG. 1 is a block connection diagram showing an example of a synchronization control device for a video disc player according to the present invention;
FIG. 2 is a configuration diagram showing an example of a pulse control section used in a synchronization control device for a video disc player according to the present invention, and FIG. 3 is provided for explanation of an example of the pulse control section shown in FIG. 2. FIG. In the figure, 1 is a pickup, 4 is a filter circuit,
6 is a video demodulation circuit, 9 is a synchronization separation circuit, 10 is a terminal to which an external horizontal synchronization signal is supplied, 11 is a phase comparison circuit, 12 is a switch, 14 is an addition circuit, 1
5 is a drive control circuit, 16 is a spindle motor,
17 is a terminal to which an external vertical synchronization signal is supplied; 18
1 is a pulse control section, and 19 is a pulse generation circuit.

Claims (1)

[Claims] 1. A synchronization separator that generates a reproduced vertical synchronizing signal and a reproduced horizontal synchronizing signal obtained from a read signal from a rotationally driven video disk, and a phase comparator that compares the phases of the external horizontal synchronizing signal and the reproduced horizontal synchronizing signal. , a pulse generator, a pulse controller that detects a phase difference between an external vertical synchronization signal and the reproduced vertical synchronization signal, and causes the pulse generator to send out a pulse signal according to the detected phase difference; The output of the phase comparison section and the pulse signal are supplied, and the rotation of the video disk is controlled based on the output of the phase comparison section, and the rotation of the video disk is controlled based on the pulse signal. a drive control section for moving a stable point of control based on the output of the phase comparison section for synchronizing the reproduction horizontal synchronization signal and the reproduction vertical synchronization signal with the external horizontal synchronization signal and the external vertical synchronization signal, respectively. A synchronization control device for video disc players.