JPH0547775A - Manufacture of semiconductor device - Google Patents

Abstract

(57) [Summary] [Object] The present invention relates to a method for manufacturing a semiconductor device, and an object thereof is to provide a method for manufacturing a semiconductor device capable of realizing a high-speed device in which a carrier transit time is shortened. [Structure] An oxidation resistant film 5 is formed only in a region along a side wall of the silicon oxide film 3, oxidation is performed using this film 5 as a mask, and then the film 5 is selectively removed to have a width equal to that of the film 5. Ions are implanted into the exposed silicon region having the width of 1 by using the oxide films 3 and 6 as masks.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a manufacturing method capable of speeding up a semiconductor device such as a lateral bipolar transistor using an SOI substrate.

[0002]

2. Description of the Related Art A lateral bipolar transistor using an SOI substrate has the effect of reducing the parasitic capacitance by using the SOI substrate and, in addition, the base-collector area can be reduced, so that the junction capacitance between the base and collector is reduced. Is a semiconductor device capable of reducing In the conventional manufacturing method of the lateral bipolar transistor, the base, collector and emitter openings are formed by the photolithography technique.

[0003]

Since the base width formed by photolithography used in the conventional method for manufacturing a bipolar transistor is determined by the minimum size that can be formed by the photolithography technique, it is generally 0. It becomes about 3 to 0.5 μm. This base width is remarkably wider than the base width of a normal vertical bipolar transistor, which is about 0.1 μm at the maximum, and therefore the base transit time of the carrier becomes long. It was not possible to realize a high-speed lateral bipolar transistor by the method.

It is an object of the present invention to provide a method of manufacturing a semiconductor device which can realize a high speed device by shortening the carrier transit time.

[0005]

According to a method of manufacturing a semiconductor device of the present invention, a silicon oxide film having a predetermined shape is formed in advance on a part of exposed silicon on a surface of a substrate, and the remaining exposed oxide film is left. After thinly oxidizing the silicon surface of the pad oxide film to form a pad oxide film, an oxidation resistant film is formed only on the region along the sidewall of the previously formed silicon oxide film on the pad oxide film. Oxidation is performed by using the oxidizable film as a mask to further oxidize the silicon in the region of the pad oxide film, and then only the oxidation resistant film is selectively removed, and the pad oxide film underneath is removed. The method is characterized by including the step of exposing silicon in a region having a width equal to the width of the oxidation resistant film and implanting ions in this region.

In the method of the present invention, the width of a region, such as the base region of a lateral bipolar transistor, in which carrier transit time is a problem is limited by the minimum dimension of the technical constraint of photolithography using a mask. It is decided by self-alignment, not by the This principle will be described with reference to FIG. In FIG. 1 (a),
1 is a silicon oxide substrate, 2 is a silicon oxide substrate 1
The upper silicon constitutes the active region in the lateral bipolar transistor. A silicon oxide film 3 having a predetermined shape is formed in advance on a portion of the exposed silicon in the active region, and a thin pad oxide film 4 is formed on the remaining exposed silicon surface. According to the method of the present invention, the oxidation-resistant film 5 having the width W is formed only on the pad oxide film 4 along the side wall of the previously formed silicon oxide film 3. Next, as shown in FIG. 1B, oxidation is performed using this film 5 as a mask to further oxidize the silicon in the exposed pad oxide film region to form a thick oxide film 6, and The oxidation resistant film 5 and the pad oxide film under this film are selectively removed in order to obtain the oxidation resistant film 5.
Expose a region of silicon having a width equal to the width W of. If a dopant is ion-implanted into the silicon in the exposed region using the remaining oxide films 3 and 6 as a mask,
An ion implantation region having a width equal to the width W of the oxidation resistant film 5 is formed.

Suitable as the oxidation resistant film is a silicon nitride film (Si _x N _y ) or a silicon oxynitride film (Si _x O _y N _z ).
Is. These act as effective masks when further oxidizing the silicon in the region of the pad oxide and prevent oxidation of the silicon underlying the oxidation resistant film. The silicon nitride film and the silicon oxynitride film can be deposited by CVD on the entire surface of the oxide film 3 and the pad oxide film 4 formed in advance, as shown by 5 in FIG. By performing anisotropic etching by etching, the oxidation resistant film 5 is removed only in the direction perpendicular to the substrate, and as shown in FIG. 2 (b), the silicon oxide film 3 formed in advance is removed. The oxidation resistant film 5 having the width W can be left only in the region along the side wall. This width W can be set to 0.1 μm or less, preferably about 0.05 μm.
Thus, the oxidation resistant film can act as an effective mask during the oxidation operation to prevent the oxidation of the underlying silicon, and only in the regions along the sidewalls of the previously formed silicon oxide film. Any film can be used as long as it can be formed by an appropriate method and can be selectively and easily removed later.

When the base region of the lateral bipolar transistor is to be formed, an electrode for extracting the base is formed on the ion-implanted silicon region after removing the oxidation resistant film and the pad oxide film thereunder. This electrode can be easily formed, for example, by depositing polysilicon. Specifically, after ion implantation,
By depositing polysilicon on the entire surface by the CVD method and injecting an appropriate impurity such as boron in order to reduce the resistance, and then patterning to remove unnecessary polysilicon, a base extraction electrode can be manufactured. ..

Although it is desirable that the emitter section and the base extraction electrode are not in contact with each other, in reality, some of them may be in contact with each other. In that case, if the base extraction electrode is made of polysilicon, the emitter-base junction may not be a junction between single crystal silicons, and a tunnel leak current may flow to cause a decrease in current gain. This problem can be solved by making the emitter-base junction be a junction of single crystal silicon without contacting the single crystal silicon and polysilicon.

In order to prevent contact between single crystal silicon and polysilicon, for example, a silicon epitaxial growth technique can be used as a method for forming the base extraction electrode. The use of the epitaxial growth technique is convenient because it is possible to simultaneously dope the dopant for lowering the resistance of the electrode. Although the epitaxial layer of silicon is actually formed only on the single crystal silicon forming the base contact region, and polysilicon is formed elsewhere (see FIG. 5), the emitter-base junction is not formed. Is sufficient for joining single crystal silicons to each other. The formed silicon layer is
Patterning is performed to remove a portion other than the base extraction electrode. Furthermore, by using selective epitaxial growth, a silicon single crystal can be selectively grown only on the single crystal silicon, and silicon is not deposited on the oxide film.
Subsequent patterning can be omitted.

Another method of preventing contact between single crystal silicon and polysilicon is to prior to ion implanting the base dopant and before removing the oxidation resistant film and underlying pad oxide film, the emitter section. After the dopant of the emitter is ion-implanted into the silicon under the pad oxide film that constitutes the pad oxide film using the silicon oxide film and the oxidation resistant film on the side wall as a mask, the width of the oxidation resistant film is narrowed, and then the pad oxide film is formed. This is a method of oxidizing the underlying silicon. According to this method, the pre-made emitter part and the base lead-out electrode, which will be made later, are separated by the narrowed width of the oxidation resistant film, and the emitter-base junction is made of single crystal silicon. Will be joined.

The method of narrowing the width of the oxidation resistant film can be appropriately selected according to the material of this film. For example, when the film is a silicon nitride film, it can be narrowed by about 50 nm by etching with hot phosphoric acid.

[0013]

In the method of the present invention, the oxidation resistant film formed only in the region along the side wall of the silicon oxide film can prevent the oxidation of the silicon thereunder and oxidize the silicon in other regions. And its removal enables the exposure of unoxidized silicon regions of comparable width. Since this oxidation resistant film can be formed by self-alignment without using photolithography, an unoxidized silicon region having a width sufficiently narrower than the width of the unoxidized silicon region formed by photolithography is formed. Then, by ion-implanting into this region, an ion-implanted region having a sufficiently narrow width equivalent to the width of the oxidation resistant film is obtained.

The silicon electrode formed in this ion-implanted region serves as a base lead-out electrode of the lateral bipolar transistor. When the silicon electrode is formed by epitaxial growth or the direct contact between the base extraction electrode and the emitter is eliminated, the emitter-base junction can be made of single crystal silicon, and the base extraction electrode is polysilicon. It is possible to improve the current gain by suppressing the occurrence of the tunnel leak current that occurs in the above.

[0015]

The present invention will be further described with reference to the following examples. Example 1 An example in which the method of the present invention is applied to the manufacture of an npn-bipolar transistor will be shown. As shown in FIG. 3A, the silicon of the SOI substrate was oxidized except for the active region. In this figure, 11 is silicon in the active region and 12 and 13 are silicon oxides. This active region is n-type with a carrier concentration of 10 ¹⁷ / cm
³ , the film thickness was 0.15 μm. 20 silicon oxide on the entire surface
Then, a silicon oxide film 14 having a predetermined shape is formed on a part of the silicon and the silicon oxide adjacent to the silicon oxide, as shown in FIG. 3 (b). Then, the exposed silicon in the active region was thinly oxidized to form a pad oxide film 15 having a thickness of 10 nm.

As shown in FIG. 3C, a 100 nm thick silicon nitride film 16 was deposited on the entire surface by the CVD method. This silicon nitride film 16 is anisotropically removed only in a direction perpendicular to the substrate by reactive ion etching,
As shown in (d), the oxidation resistant film 17 is left along the side wall of the silicon oxide film. Next, arsenic as an emitter dopant was implanted over the entire surface at an acceleration energy of 200 keV and a dose of 1 × 10 ¹⁶ / cm ² . Under this implantation condition, arsenic is used as the silicon layer and the silicon nitride film 17 under the 200 nm thick silicon oxide film 14.
It is not implanted in the underlying silicon layer. Next, using the silicon nitride film 17 as a mask, the exposed pad oxide film 15
Is further oxidized to form an oxide film 18 with a thickness of 100 nm (Fig. 4
(A)).

The silicon nitride film 17 was selectively removed with hot phosphoric acid, and the pad oxide film therebelow was removed by wet etching to expose silicon. And boron
1 × 10 ¹³ / cm ^{2 was} injected at an acceleration energy of ²⁰ keV. As a result, a base having a width of about 100 nm was formed. Next, deposit 200 nm of polysilicon on the entire surface and
1 × 10 ¹⁶ / cm ^{2 was} injected with an acceleration energy of keV to reduce the resistance. By patterning, only the polysilicon of the electrode 19 for drawing out the base was left (FIG. 4B).

Next, phosphorus is implanted at a dose of 1 × 10 ¹⁶ / cm ² with an acceleration energy of 200 keV, leaving a resist for patterning the electrode 19 for extracting the base, and annealed to lower the collector contact region 20 to a low resistance. (Fig. 4 (c)). Finally, as shown in FIG. 4D, the collector contact region 20 and the emitter contact region 21 are opened, and metal 22, 23, 24 is formed on these openings and the base extraction electrode 19.
To form an npn-lateral bipolar transistor. Example 2 Following the same procedure as in Example 1, a silicon nitride film having a thickness of 50 nm was deposited on the silicon oxide film and the pad oxide film by a CVD method, and this was processed by reactive ion etching.
A silicon nitride film with a width of 50 nm was left only on the sidewall region of the silicon oxide film with a thickness of 200 nm.

Arsenic is ion-implanted by using the silicon nitride film and the silicon oxide film as a mask (acceleration energy
120keV, dose 1 × 10 ¹⁶ / cm ² ). Next, using the silicon nitride film as a mask, the exposed pad oxide film was further oxidized to a film thickness of 100 nm. The silicon nitride film was removed with hot phosphoric acid, and the pad oxide film underneath was removed to expose silicon with a width of 50 nm. Next, boron as a base dopant was ion-implanted using the silicon oxide film as a mask (acceleration energy 20 keV, dose 1 × 10 ¹³ / cm 3).
² ).

After annealing at 800 ° C. for 20 minutes in a nitrogen atmosphere, boron-doped silicon epitaxial growth was performed. Single crystal silicon was grown only on the exposed silicon crystals, and polysilicon was deposited on the other parts. The base extraction electrode was formed by patterning. As shown in FIG. 5, in the base extraction electrode 31 thus formed, only the portion 32 formed by growing on the silicon in the base region is a single crystal, and the other portion formed by depositing on the oxide film. Is actually polysilicon, but there is no problem in making the emitter-base junction a junction between single crystals.

Next, metal for the emitter, collector and base was formed in the same manner as in Example 1 to complete the npn-lateral bipolar transistor. In this transistor, the base width is 50 nm. Also, the junction between the base extraction electrode and the emitter was a junction between single crystal silicons, and the current gain was about 100, similar to the case of a normal vertical bipolar transistor. Example 3 A 100-nm-thick silicon nitride film was blanket deposited according to the same procedure as in Example 1, and then anisotropically removed by reactive ion etching to form a sidewall region of a 200-nm-thick silicon oxide film. Only the silicon nitride film with a width of 100 nm was left as an oxidation resistant film. Then, using the silicon nitride film and the silicon oxide film as a mask, arsenic was ion-implanted (acceleration energy 120 keV, dose 1 × 10 ¹⁶ / cm ² ).

Next, the silicon nitride film was isotropically etched with hot phosphoric acid to narrow the width of the silicon nitride film to 50 nm. Using the remaining silicon nitride film as a mask, the exposed pad oxide film was further oxidized to a film thickness of 100 nm. After removing the silicon nitride film and the underlying pad oxide film, boron is ion-implanted as a base dopant into the exposed silicon region with a width of 50 nm using the silicon oxide film as a mask (acceleration energy 20 keV, dose 1 × 10 ¹³ / cm 3). ² ) and then about 50
A nm wide base was formed. Then, in the same manner as in Example 1, a boron-doped polysilicon base extraction electrode was formed.

As shown in FIG. 6, the base lead-out electrode 41 and the emitter portion 42 thus formed are separated by the width of the silicon nitride film narrowed before the ion implantation of the base dopant. Since there is no contact, even if the base extraction electrode is made of polysilicon, carrier recombination disappears and tunnel leakage current does not flow.

Then, metal for the emitter, collector and base was formed in the same manner as in Example 1 to complete the npn-lateral bipolar transistor. The current gain is approximately
It was 100.

[0025]

As described above, the base width formed by photolithography is generally 0.3 to 0.5 μm.
In contrast, according to the method of the present invention, it is 0.05 to 0.
A sufficiently narrow base width of about 1 μm can be obtained by self-alignment. Running time τ of minority carriers in the base
_B, if the base width and W _B, represented by the following equation.

[0026]

[Equation 1]

As is clear from this equation, if the base width can be set to, for example, 0.1 μm by the method of the present invention, the base running time can be shortened from 1/9 to 1/25 as compared with the conventional case. , A lateral SO that reduces parasitic capacitance
A high speed device can be realized in combination with the features of the I bipolar transistor. If the emitter-base junction is made of single crystal silicon, it is possible to suppress the occurrence of tunnel leakage current and improve the current gain. The current gain of can be obtained.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of the method of the present invention.

FIG. 2 is a diagram illustrating a method of forming an oxidation resistant film.

FIG. 3 is a diagram illustrating the first half of the procedure of the first embodiment.

FIG. 4 is a diagram for inventing the latter half of the procedure of the first embodiment.

FIG. 5 is a diagram illustrating a base extraction electrode of Example 2;

FIG. 6 is a diagram illustrating a base extraction electrode of Example 3;

[Explanation of symbols]

 1 ... Silicon oxide substrate 2 ... Silicon 3 ... Silicon oxide film 4 ... Pad oxide film 5 ... Oxidation resistant film 6 ... Silicon oxide film

Claims (6)

[Claims] 1. A silicon oxide film (3) having a predetermined shape is previously formed on a part of the exposed silicon (2) on the substrate surface, and the remaining exposed silicon surface is thinly oxidized. After the pad oxide film (4) is formed, the oxidation resistant film (5) is formed only on the pad oxide film (4) along the sidewall of the previously formed silicon oxide film (3). Then, oxidation is performed using the oxidation resistant film (5) as a mask to further oxidize the silicon in the region of the pad oxide film (4), and then only the oxidation resistant film (5) is selectively removed. And further removing the pad oxide film (4) thereunder to expose silicon in a region having a width (W) equivalent to that of the oxidation resistant film, and implanting ions in this region. A method for manufacturing a semiconductor device, comprising: 2. The method according to claim 1, wherein the oxidation resistant film (5) is a silicon nitride film or a silicon oxynitride film. 3. The method according to claim 1, further comprising the step of forming the ion-implanted region as a base region of a lateral bipolar transistor, and forming an electrode for extracting a base on the base region. 4. The method according to claim 3, wherein the base extraction electrode is formed by depositing polysilicon. 5. The method according to claim 3, wherein the base extraction electrode is formed by epitaxial growth of silicon. 6. An emitter dopant is ion-implanted into silicon under the pad oxide film (4) by using the silicon oxide film (3) and an oxidation resistant film (5) formed along a side wall thereof as a mask. The method according to claim 3, wherein the width of the oxidation resistant film (5) is then narrowed and then the silicon under the pad oxide film (4) is oxidized.