JPH0548108A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

PURPOSE:To improve the driving capacity of a semiconductor device by respectively providing a pair of facing gate electrodes on the upper and lower surfaces of a channel area and, at the same time, the third gate electrode facing the pair of gate electrodes so that the third gate electrode can be buried in a semiconductor crystal layer. CONSTITUTION:The first gate electrode 11 is formed on a supporting substrate 10 composed of, for example, a silicon wafer. After coating the surfaces of the substrate 10 and electrode 11 with a gate insulating layer 12, a single-crystal silicon semiconductor layer 13 is formed on the substrate 10 and the second gate electrode 16 buried in the layer 13 is formed in the layer 13, with the electrode 16 being coated with a gate insulating layer. Then the third gate electrode 18 is formed in a buried state on the layer 13 with a gate insulating layer 17 in between. In other words, two pairs of facing gate electrodes 11 and 16 and 16 and 18 are provided on both surfaces of the single-crystal semiconductor layer 13. Therefore, the driving capacity of the semiconductor device can be improved.

Description

Detailed Description of the Invention

[0001]

The present invention relates to a so-called SOI (silicon
on insulator) structure MISFET (metal-insula-tor-semico
nductor field-effect transistor).

[0002]

2. Description of the Related Art SOI technology for forming a semiconductor device on a thin single crystal semiconductor layer formed on an insulating layer is effective for reducing the source / drain parasitic capacitance of MISFET and preventing latch-up in CMOS FET, for example. In addition, MI is being miniaturized as the density of semiconductor integrated circuits increases.
It is expected as a powerful means to solve the problem of short channel effect in SFET. FIG. 7 is a schematic cross-sectional view showing the structure of a MISFET formed on an SOI substrate. For example, on a supporting substrate 1 made of a silicon wafer, an insulating layer 2 made of SiO ₂ is used, and a thickness made of silicon is formed. A single crystal semiconductor layer 3 having a thickness of 120 nm is formed. This single crystal semiconductor layer 3
A gate electrode 5 is formed on the channel region demarcated by the gate insulating layer 4 and source / drain regions 6 are formed on both sides of the channel region.

Since the base of the single crystal semiconductor layer 3 is the insulating layer 2, the parasitic capacitance of the source / drain region 6 is extremely small, and the depletion layer is prevented from extending from the drain side, so that the short channel effect is obtained. Hard to happen. Furthermore, since the single crystal semiconductor layer 3 is usually separated into islands on the insulating layer 2 for each region where each MISFET is formed, element isolation is complete, and latch-up in CMOS-structured MISFETs is completed. The phenomenon is prevented.

[0004]

However, according to the conventional SOI technology, the MISF having a sufficient driving capability is required for increasing the parasitic resistance of the source / drain regions accompanying the thinning.
It is difficult to make ET. Therefore, this driving capability problem is due to the miniaturization of SOI-structured MISFETs.
It is an important obstacle to high integration.

An object of the present invention is to provide a method capable of improving the drive capability of a MISFET having an SOI structure in order to solve the above conventional problems.

[0006]

The above object is to provide a semiconductor layer supported by a supporting substrate having one insulating surface,
A channel region defined in the semiconductor layer, a pair of gate electrodes provided on both sides of the channel region so as to face each other with the semiconductor layer interposed therebetween, and the pair of gate electrodes buried in the channel region. A third gate electrode provided opposite to the gate electrode, and a source and drain region formed on both sides of the channel region inside the semiconductor layer, and a conductivity for connecting the pair of gate electrodes and the third gate electrode. Or a semiconductor device according to the present invention characterized by comprising a layer, or a recess is formed in a predetermined region defined on one surface of the support substrate, and the surface of the support substrate on which the recess is formed is insulative. Forming a first conductive layer selectively filling the recess on the support substrate having the insulative surface, forming a first insulating layer covering the first conductive layer, Covered by first insulating layer And another surface of the semiconductor substrate bonded to the support substrate by bonding the support substrate and the semiconductor substrate with the surface of the support substrate having the first conductive layer in close contact with the one surface of the semiconductor substrate. Forming a second recess having a bottom located at a predetermined depth from the other surface, forming a second insulating layer covering the inner surface of the second recess,
A second recess that selectively fills the second recess covered with the insulating layer of
A third insulating layer that selectively covers the second conductive layer and exposes the other surface of the semiconductor substrate around the second recess. Forming a single crystal semiconductor layer covering the other surface of the semiconductor substrate exposed on and around the insulating layer, and forming a third conductive layer corresponding to the second conductive layer on the single crystal semiconductor layer. An impurity of a predetermined conductivity type is ion-implanted into the single crystal semiconductor layer and the semiconductor substrate using the third conductive layer as a mask,
This is achieved by a method for manufacturing a semiconductor device according to the present invention, which includes various steps of forming a conductive layer connecting the third conductive layer and the first and second conductive layers.

[0007]

[Operation] A so-called dual-gate MISFET in which the driving capability is enhanced by providing two gate electrodes facing each other on both sides of the semiconductor layer by utilizing the SOI structure.
Has been proposed (F. Balestra, et al., IEEE, EDL-
8, pp.410-412, 1987). In this method, double the current is obtained by forming inversion layers on both surfaces of the semiconductor layer.

According to the present invention, as shown in FIG. 1, by further providing another gate electrode in the central portion of the semiconductor layer to this double gate structure, the double current structure has a double current. To get That is, a first gate electrode 11 is formed on a support substrate 10 made of, for example, a silicon wafer, the surfaces of the support substrate 10 and the gate electrode 11 are covered with a gate insulating layer 12, and then the support substrate 10 is made of, for example, silicon. A single crystal semiconductor layer 13 is formed. A second gate electrode 16 embedded in the single crystal semiconductor layer 13 via a gate insulating layer 14 is formed. A third gate electrode 18 is formed on the single crystal semiconductor layer 13 with a gate insulating layer 17 interposed therebetween. The facing surfaces of the gate electrodes 11 and 16 and the facing surfaces of the gate electrodes 16 and 18, and the single crystal semiconductor layer 13 between these pairs respectively configure a MISFET having a double gate structure.

[0009]

2 to 6 show a MISF having the structure shown in FIG.
FIG. 6 is a process explanatory diagram of an example of producing an ET. In this embodiment, n
A channel MISFET will be described as an example, but it goes without saying that the same process can be applied to the production of a p-channel MISFET.
The corresponding parts in FIGS. 2 to 6 and FIG. 1 are designated by the same reference numerals.

Referring to FIG. 2 (a), a groove having a predetermined gate length (L) is formed in a supporting substrate 10 made of an n-type silicon wafer.
20, Generally, after forming the recess, the supporting substrate 10 and the groove are formed.
An insulating layer 21 that covers 20 is formed. As the insulating layer 21, the surface of the supporting substrate 10 in which the groove 20 is formed is thermally oxidized to have a thickness of about 20 nm.
SiO ₂ may be formed.

Next, as shown in FIG. 2B, a gate electrode formed by burying, for example, polycrystalline silicon in the groove 20.
Forming 11. The gate electrode 11 is formed by depositing a polycrystalline silicon layer on the supporting substrate 10 on which the insulating layer 21 is formed by using the CVD (Chemical Vapor Deposition) method and then forming a planarization layer made of a thermal oxide film. Then, a known method of etching back the polycrystalline silicon layer until the insulating layer 21 is exposed around the groove 20 may be used. In order to reduce the resistance of the gate electrode 11, an n-type impurity such as arsenic (As) is ion-implanted as needed.

Next, as shown in FIG. 2C, a gate insulating layer 12 having a thickness of about 20 nm is formed to cover the gate electrode 11. The gate insulating layer 12 may be formed by thermally oxidizing the supporting substrate 10 by heat-treating it at 750 ° C. for 12 minutes in a wet oxidizing atmosphere. In this heat treatment, at the same time, thermal oxidation of the surface of the supporting substrate 10 also progresses, and the flatness of the surface is maintained. Further, in the heat treatment step, the ion-implanted impurities diffuse.

Next, as shown in FIG. 3D, the support substrate 10 is bonded to the p-type silicon wafer 22, for example, through the gate insulating layer 12. Such joining of two silicon wafers is well known in the art (eg, K. Mitani, et al., Jpn.
J. Appl. Phys., 30 , No. 4 (1991) pp.615-622). Then, the silicon wafer 22 is polished to have a thickness of about 200 nm.

Then, as shown in FIG. 3E, a groove 24 having the same gate length (L) as the groove 20 is formed in the silicon wafer 22 thinned as described above. The depth of the groove 24 is set so that the silicon wafer 22 having a thickness of about 50 nm remains between the bottom of the groove 24 and the gate insulating layer 12. After that, the insulating layer 14 that covers the inner surfaces of the silicon wafer 22 and the groove 24 is formed. As the insulating layer 14, the surface of the silicon wafer 22 in which the groove 24 is formed may be thermally oxidized to form SiO ₂ having a thickness of about 20 nm.

Next, as shown in FIG. 3 (f), a gate electrode formed by burying, for example, polycrystalline silicon in the groove 24.
Forming 16. The gate electrode 16 may be formed by using a method similar to that of the gate electrode 11, and ion implantation of an n-type impurity for reducing the resistance is performed. After that, the surfaces of the silicon wafer 22 and the gate electrode 16 are thermally oxidized to form an insulating layer.
Forming 25. The thermal oxidation conditions are set, for example, at 750 ° C. for 40 minutes in the wet oxidation atmosphere of the supporting substrate 10 so that the insulating layer 25 on the silicon wafer 22 has a thickness of about 30 nm. The gate electrode 16 made of polycrystalline silicon is
Since it is oxidized deeper than the single crystal silicon wafer 22, the thickness of the insulating layer 25 on the gate electrode 16 is about 50 nm.
In the heat treatment process, the ion-implanted n-type impurities diffuse.

Next, as shown in FIG. 3 (g), the insulating layer 25 is etched back until the surface of the silicon wafer 22 is exposed. As a result, the thickness of the insulating layer 25 on the gate electrode 16 becomes about 20 nm. In this way, the gate electrode 16 is in a state of being surrounded by the gate insulating layer 14 and the insulating layer 25.

Next, as shown in FIG. 4H, a p-type silicon layer 26 having a thickness of about 50 nm is epitaxially grown on the silicon wafer 22 and the gate electrode 16. The growth of the silicon layer 26 may be performed using a well-known vapor phase growth method or liquid phase growth method. Alternatively, polycrystalline silicon may be deposited on the silicon wafer 22 and the gate electrode 16 and single crystallized by laser beam annealing. In either method, since the silicon wafer 22 serves as a growth nucleus, a single crystal layer grows on the insulating layer 25 as well.

Next, as shown in FIG. 4I, a gate insulating layer 17 and a gate electrode 18 having a thickness of about 20 nm are formed on the silicon layer 26. These may be formed in the same manner as in the manufacture of a normal MISFET. For example, after the surface of the silicon layer 26 is thermally oxidized to form the gate insulating layer 17, the gate insulating layer 17 is formed.
It suffices to deposit a polycrystalline silicon layer on top and etch them all at once to pattern the gate electrode 18 having the gate length (L).

Next, using the gate electrode 18 as a mask, as shown in FIG. 4 (j), n-type impurities are ion-implanted into the silicon layer 26 and the silicon wafer 22 to a depth reaching the gate insulating layer 12. In this way, the n-type source / drain region 28 is formed, and the silicon layer 26 between the gate electrodes 18 and 16 becomes the channel region.
A SFET and a MISFET having a double gate structure in which the silicon wafer 22 between the gate electrodes 16 and 11 serves as a channel region are formed.

Next, these gate electrodes 11, 16 and 18 are electrically connected. First, as shown in FIG. 4 (k), the gate electrode 16 is set so that its width is shorter than the others by a certain length. This is to prevent the contact for connecting the electrodes 11 and 18 from directly contacting the electrode 16. Next, a contact hole 31 for connecting the gate electrodes 16 and 18 is first formed using a photomask 30 as shown in FIG.

Then, as shown in FIG. 5 (m), the CV is formed on the entire surface.
The SiO ₂ film 32 is formed by the D method. The silicon layer 26 is anisotropically etched and left as a sidewall 33 in the contact hole 31 as shown in FIG. Similarly,
As shown in FIG. 5 (o), a contact hole 34 for connecting the gate electrodes 11 and 18 is formed, and a sidewall 35 made of SiO ₂ is formed therein.

After the above, an aluminum film, for example, is deposited on the entire surface and patterned to form a conductive layer 36 for connecting the gate electrodes 11, 16 and 18 as shown in FIG. 6 (p).
To form a structure according to the present invention in which two MISFETs having a double gate structure are stacked.

[0023]

According to the present invention, it is possible to fabricate a MISFET having a larger driving capacity than the conventional one without increasing the area occupied by the device, and the high density and high performance achieved by using the semiconductor layer of the SOI structure. There is an effect of promoting the practical application of the semiconductor integrated circuit.

[Brief description of drawings]

FIG. 1 is an explanatory view of the principle structure of the present invention.

FIG. 2 is a process explanatory view of the embodiment of the present invention (No. 1)

FIG. 3 is a process explanatory diagram of the embodiment of the present invention (No. 2)

FIG. 4 is a process explanatory diagram of the embodiment of the present invention (No. 3)

FIG. 5 is a process explanatory view of the embodiment of the present invention (No. 4)

FIG. 6 is an explanatory process diagram (5) of the embodiment of the present invention.

[Figure 7] Illustration of problems in conventional SOI structure MISFETs

[Explanation of symbols]

1, 10 Support substrate 2, 21, 25 Insulating layer 3 Single crystal semiconductor layer 4, 12, 14, 17 Gate insulating layer 5, 11, 16, 18 Gate electrode 6, 28 Source / drain region 13 Single crystal semiconductor layer 20, 24 Groove 22 Silicon wafer 26 Silicon layer 30 Photomask 31, 34 Contact hole 32 SiO ₂ film 33, 35 Sidewall 36 Conductive layer

Claims (2)

[Claims] 1. A semiconductor layer supported by a supporting substrate having an insulating surface, a channel region defined by the semiconductor layer, and a semiconductor layer sandwiched between the semiconductor layer and the channel region facing each other on both sides of the channel region. A pair of gate electrodes provided, and a third gate electrode that is provided so as to be buried in the channel region so as to face the pair of gate electrodes. The third gate electrode is formed on both sides of the channel region inside the semiconductor layer. A semiconductor device comprising source and drain regions, and a conductive layer connecting the pair of gate electrodes and the third gate electrode. 2. A step of forming a concave portion in a predetermined region defined on one surface of the supporting substrate, a step of making the surface of the supporting substrate having the concave portion insulative, and the insulating surface Forming a first conductive layer that selectively fills the concave portion on the supporting substrate having a step, forming a first insulating layer that covers the first conductive layer, and the first insulating layer Bonding the support substrate and the semiconductor substrate in a state where the surface of the support substrate having the first conductive layer covered with the semiconductor substrate is in close contact with the one surface of the semiconductor substrate; and the semiconductor bonded to the support substrate. Forming a second recess having a bottom located at a predetermined depth from the other surface of the substrate, and forming a second insulating layer covering the inner surface of the second recess , A second conductor selectively filling the second recess covered with the second insulating layer Forming a layer, forming a third insulating layer selectively covering the second conductive layer and exposing the other surface of the semiconductor substrate around the second recess, Forming a single crystal semiconductor layer on the third insulating layer and covering the other surface of the semiconductor substrate exposed around the third insulating layer; and forming a single crystal semiconductor layer on the single crystal semiconductor layer corresponding to the second conductive layer.
Forming a conductive layer through the fourth insulating layer, ion-implanting impurities of a predetermined conductivity type into the single crystal semiconductor layer and the semiconductor substrate using the third conductive layer as a mask, and And a step of forming a conductive layer for connecting the conductive layer and the first and second conductive layers.