JPH0548117A - Static induction semiconductor device - Google Patents

Abstract

(57) [Summary] [Object] To provide a static induction semiconductor device capable of quick turn-off and capable of protecting a gate insulating film from an excessive drain voltage at the time of interruption. A contact region 18 made of a second conductivity type semiconductor having a high impurity concentration is formed on the surface of the drain region 11 of the electrostatic induction semiconductor device, the contact region 18 being in contact with the gate insulating film 14.
The source region 17 and the contact region 18 are commonly connected to the source electrode 19, respectively. Alternatively, at least a part of the drain region 11 is brought into direct contact with the source electrode 19 to form a Schottky junction 25 on these contact surfaces.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an insulated gate static induction semiconductor device.

[0002]

2. Description of the Related Art In many static induction semiconductor devices such as static induction transistors (SIT) which have been conventionally used, their gates are junction gates. However, the static induction semiconductor device using the junction gate has a problem that the current consumption at the time of turn-off is large, and a static induction semiconductor device using an insulated gate has been proposed for the purpose of reducing the gate driving power. (JP-A-55-99774).

FIG. 13 is a diagram showing an example of an insulated gate type static induction semiconductor device disclosed in Japanese Patent Laid-Open No. 55-99774, which is a sectional view showing a static induction thyristor operating in a bipolar manner. .. In FIG. 13, 1 is an n ⁻ type drain region, 2 is a p ⁺ type drain region, and an n ⁺ type drain region 3 is interposed between these n ⁻ type drain region 1 and p ⁺ type drain region 2. ing. Reference numeral 4 denotes a drain electrode formed in contact with the p ⁺ type drain region 2 on the back surface of the semiconductor device. Reference numeral 5 is a gate insulating film, and 6 is a gate electrode formed on the gate insulating film 5. Reference ^numeral 7 is an n ⁺ type source region, 8 is a source electrode formed on the n ⁺ type source region 7, and the n ⁺ type source region 7 is formed on the surface of the n ⁻ type drain region 1. In the example shown in FIG.
N ⁻ type drain region 1 between the respective n ⁺ type source regions 7
A groove is formed in the gate insulating film 5, and the gate insulating film 5 is formed on the inner surface of the groove.

Next, the operation of this device will be described. In FIG. 13, the source electrode 8 is grounded and the drain electrode 4 is applied with a positive voltage. When a predetermined negative voltage is applied to the gate electrode 6, a depletion layer is formed in the n ⁻ type drain region 1 around the n ⁺ type source region 7, and the depletion layer is formed between the n ⁺ type source region 7 and the p ⁺ type drain region 2. The current path is cut off and the thyristor is turned off. On the other hand, when no voltage is applied to the gate electrode 6 or a positive voltage is applied, the depletion layer that has developed around the n ⁺ type source region 7 disappears and the thyristor is turned on.

In the example shown in FIG. 13, in the n ⁺ type drain region 3, the depletion layer extends to the p ⁺ type drain region 2 in the n ⁻ type drain region 1 having a low impurity concentration and a punch through phenomenon occurs. And has a function of controlling the injection of minority carriers from the p ⁺ type drain region 2 to the n ⁻ type drain region 1.

[0006]

However, in the above-mentioned conventional insulated gate type electrostatic induction semiconductor device, n ⁻ around the gate insulating film 5 is in the ON state of the device.
A large amount of minority carriers are injected from the p ⁺ type drain region 2 into the type drain region 1, and the n ⁻ type drain region 1 around the gate insulating film 5 is in a high level injection state.

In the junction gate type electrostatic induction semiconductor device, the carrier density in the drain region can be reduced in a short time by directly extracting a large amount of minority carriers existing around the gate from the gate electrode, and even until turn-off. However, in the insulated gate type static induction semiconductor device, a large amount of minority carriers existing around the insulated gate 5 cannot escape through the insulated gate 5. , Therefore, minority carriers because no place to go, these minority carriers n ^-
There is no choice but to wait for spontaneous disappearance in the mold drain region 1.
Therefore, the insulated gate electrostatic induction semiconductor device has a problem that it takes a long time to turn off, which leads to a loss of power consumption.

Even in the static OFF state, when a high voltage is applied to the drain electrode, minority carriers generated in the depletion layer around the gate insulating film 7 cause an inversion layer around the gate insulating film 7. There is also a problem that the gate insulating film 7 is formed and the drain voltage is applied to the gate insulating film 7 without extending the depletion layer and the gate insulating film 7 is destroyed. This phenomenon can also occur in a unipolar operation static induction transistor in which the drain region 2 is an n ⁺ type region.

The object of the present invention is to solve the above-mentioned problems of the prior art, and enables quick turn-off and protects the gate insulating film from an excessive drain voltage at the time of interruption. Another object of the present invention is to provide a static induction semiconductor device that can be used.

[0010]

The present invention will be described with reference to FIGS. 1 and 11 showing an embodiment, in which a drain region 11 made of a semiconductor of the first conductivity type and a surface of the drain region 11 are provided. Insulated gates (14, 15) buried in a U-shaped groove and a first conductivity type source region 17 formed on the surface of the drain region 11 and ohmic-connected to the source electrode 19 are provided. It is applied to electrostatic induction semiconductor devices. The invention of claim 1 provides the insulated gate (14, 1) on the surface of the drain region 11.
By forming the contact region 18 of the second conductivity type which is in contact with the source electrode 19 and is in ohmic contact with the source electrode 19, the above-mentioned object is achieved. Further, the invention of claim 2 achieves the above-mentioned object by directly contacting at least a part of the drain region 11 with the source electrode 19 and forming a Schottky junction 25 on these contact surfaces. ..

[0011]

In the cutoff state of the electrostatic induction semiconductor device, the inversion layer formed in the drain region 11 near the gate insulating film 14 is connected via the contact region 18 or the Schottky junction 25 formed on the surface of the drain region 11. It is connected to the source electrode 19. Therefore, the potential of this inversion layer is always fixed to the same potential as the source electrode 19. In addition, the drain region 1 is used for bipolar operation.
When the second conductivity type region 12 is sandwiched between the drain electrode 11 and the drain electrode 13, the drain region 11 near the source region 17 at the turn-off when the conductivity modulation state is changed to the cutoff state.
A large amount of minority carriers existing inside the drain region 11 passes through the inversion layer in the vicinity of the gate insulating film 14 caused by the negative voltage applied to the gate electrode 15 to bring it into the cutoff state.
Surface contact area 18 or Schottky junction 2
5 and flows into the source electrode 19. Therefore, the drain region 11 near the source region 17 is quickly depleted, and quick turn-off is realized.

Incidentally, in the section of means and action for solving the above problems for explaining the constitution of the present invention, the drawings of the embodiments are used for making the present invention easy to understand. It is not limited to.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First Embodiment FIG. 1 is a sectional view showing an electrostatic induction thyristor which is a first embodiment of an electrostatic induction semiconductor device according to the present invention. In FIG. 1, 11 is an n ⁻ -type drain region, 12 is a p ⁺ -type drain region, and a drain electrode 13 is formed on the back surface of this p ⁺ -type drain region 12.

[0014] the n ^- the surface of the mold drain region 11, the n ^- a plurality of grooves along the depth direction of the -type drain region 11 has a surface perpendicular is formed, a gate insulating film 14 on the inner surface of the grooves Has been formed. Further, 15 is a gate electrode formed in the gate insulating film 14, and 16 is an interlayer insulating film formed on the surface of the gate electrode 15. Therefore, the insulated gate of the thyristor of this embodiment is embedded in the surface of the n ⁻ type drain region 11. The gate electrode 15 and the gate insulating film 14 form an insulated gate.

Reference numeral 17 denotes n ⁺ formed on the surface of the n ⁻ type drain region 11 corresponding to the space between the adjacent gate insulating films 14.
The type source area. Reference numeral 18 denotes a p ⁺ type contact region formed on the surface of the n ⁻ type drain region 11 corresponding to the n ⁺ type source region 17 and the gate insulating film 14. In this embodiment, the n ⁺ type source region 17 and the gate insulating film 14 are not in direct contact with each other, but are in contact with each other via the p ⁺ type contact region 18.

Reference numeral 19 denotes a source electrode, which is formed so as to be in contact with the surfaces of all the n ⁺ type source regions 17 and the p ⁺ type contact regions 18.

The impurity concentration of the n ^{+ type} source region 17 is set to a value of, for example, 5 × 10 ¹⁹ cm ^-3 or more, and is ohmic-connected to the source electrode 19. The p ⁺ type contact region 18 is also ohmic-connected to the source electrode 19. In the following description, the gate insulating films 14 adjacent to each other will be described.
The n ⁻ -type drain region 11 sandwiched between them is referred to as a “channel region” 20 of the semiconductor device of the present embodiment, the distance between the adjacent gate insulating films 14 is H, and the bottom of the n ⁺ -type source region 17 to the gate electrode. The depth to the bottom of 15 is L, and this distance L is referred to as the "channel length" of the semiconductor device of this embodiment.

Next, the operation of the electrostatic induction thyristor of this embodiment will be described. First, the source electrode 19 is grounded, and a positive voltage is applied to the drain electrode 13. Then, in order to turn off the thyristor, a negative low voltage is applied to the gate electrode 15. By setting the gate electrode 15 at a low negative potential, a depletion layer is formed in the n ⁻ type drain region 11 around the gate insulating film 14, and this depletion layer depletes the above-mentioned channel region 20 and the n ⁺ type source. The current path between the region 17 and the p ⁺ type drain region 13 is cut off, and the thyristor is turned off.

At this time, the gate insulating film 1 in which the depletion layer exists
An inversion layer due to holes is formed on the surface of No. 4, but since this inversion layer is in contact with the p ⁺ type contact region 18 on the surface of the n ⁻ type drain region 11, the potential of the inversion layer is p ⁺ Mold contact region 18, and thus source electrode 19
It has the same potential as and is held constant. Therefore, the voltage to be applied to the gate electrode 15 described above may be a negative voltage necessary for forming the inversion layer in which the potential is held constant, and it is not necessary to apply an excessive negative voltage higher than that. Absent.

Next, to turn on the thyristor,
By applying a positive voltage to the gate electrode 15, the gate insulating film 14
An electron accumulation layer is formed in the periphery instead of the hole inversion layer. As a result, conduction electrons from the n ⁺ type source region 17 flow from the bottom of the gate insulating film 14 to the n ⁻ type drain region 11 through the storage layer around the gate insulating film 14 and the thyristor is turned on. .. For this reason, the drift resistance of the channel region 20 in the ON state becomes small enough to be ignored.

As described above, when the thyristor is turned on and conduction electrons are emitted from the n ⁺ type source region 17 to the n ⁻ type drain region 11, the p ⁺ type drain region 12 is also changed to the n ⁻ type drain region 11. Holes are released, the n ⁻ -type drain region 11 is in a high-level injection state, the conductivity is modulated, and the resistivity is significantly reduced.

Further, in order to turn off the thyristor, a negative low voltage is applied to the gate electrode again, and an inversion layer by holes is formed in the periphery of the gate insulating film 14 instead of the accumulation layer by electrons. Immediately after applying the negative voltage, n
^{The −} type drain region 11 is in a high-level injection state, and many holes are present in the n ⁻ type drain region 11 around the n ⁺ type source region 17. However, this region is also in contact with the p ⁺ -type contact region 18, and holes rapidly flow to the source electrode 19 through the inversion layer near the gate insulating film 14 and the p ⁺ -type contact region 18, so that the n ⁺ -type source region is formed. The high level implantation state in the n ⁻ type drain region 11 around 17 is promptly resolved. As a result, a depletion layer is formed in the channel region 20 and the p ⁺ -type drain region 13 and the n ⁺
The current path to the mold source region 17 is cut off and the thyristor is turned off.

Next, the condition of the distance H between the gate insulating films 14 will be described. When the thyristor of this embodiment is in the off state, certain conditions are necessary to interrupt the current path in this thyristor. FIG. 2 is a diagram showing energy bands in a region between BB ′ in FIG. 1 along a direction orthogonal to the channel length L. In FIG. 2, the band shown separately on the right side is of the p ⁺ -type contact region 18 fixed to the same potential as the source electrode 19, and the potential of the gate insulating film 14 matches this band. The broken line at the center of each band indicates the position of the midgap, and E _g is the bandgap energy.

The channel region 20 must be completely depleted in order to block the current path. That is, as shown in FIG. 2A, in the center of the channel region 20, the potential at the bottom of the conduction band must be at least E _g / 2 above the Fermi level E _F of the n ⁺ type source region 17. .. If the potential at the bottom of the conduction band in the channel region 20 is E _g /
If there is a portion lower than 2, this region cannot be completely depleted, so that a considerable leakage current flows through the channel region 20 and the current path is not sufficiently blocked.

The distance H between the gate insulating films 14 for satisfying the cutoff condition shown in FIG. 2A is expressed by the following equation.

[Equation 1] Here, q is the elementary charge, N _p is the donor concentration of the channel region 20, ε _Si is the dielectric constant of silicon, and φ _{p +} is the midgap potential measured from the Fermi level in the p ⁺ type contact region 18. As an example, N _p = 5 × 10 ¹⁴
If cm ⁻³ and φ _{p +} = 0.56 eV, then H = (about) 2.47 μm. It can be said that the numerical value of H is not a highly advanced technology from the current photo-etching technology.

Further, the condition of the channel length L will be described. If the electrostatic induction thyristor of this embodiment is a device having a so-called pentode characteristic, it is desirable that the side surfaces of the insulated gate that sandwich the channel region 20 be as vertical as possible to the surface of the device. The channel length L also has to satisfy a certain condition.

The even channel region 20 is depleted by electrical fields generated by the insulated gate, are bent potential by the effect of the n ⁺ -type source region 18 near the channel region 20 in the n ⁺ -type source region 18. It has been clarified by numerical calculation (simulation) that this effect extends to the distance H in the direction of the channel length L (that is, the vertical direction). Such a phenomenon similarly occurs in the channel region 20 near the p ⁺ type drain region 12 (that is, near the bottom of the gate insulating film 14).

That is, the side walls of the insulated gate sandwiching the channel region 20 are formed in the vertical plane, and the channel region 20 is formed.
In the case where the distance H between the gate insulating films 14 is constant everywhere, when L / H is 2 or less, when the drain voltage becomes high, the influence range of the drain electric field and the influence range of the n ⁺ type source region 18 become. And the current-voltage characteristics of the element become triode characteristics. On the other hand, if L / H is approximately 2 or more, the n ⁺ -type source region 18 is affected by the drain electric field no matter how high the drain voltage becomes.
The current-voltage characteristic of the device becomes a pentode characteristic without being connected to the range affected by. These triode characteristics,
Although the critical value of the pentode characteristic is determined by the impurity concentration of the channel region 20 and the geometrical structure, it is necessary that L / H is 3 or more as a realistic value in order to realize an element having the pentode characteristic. ..

If the side wall of the insulated gate is not formed in a vertical plane as shown in FIG. 3, the distance H between the gate insulating films 14 increases toward the bottom of the insulated gate.
That is, when the side wall of the insulated gate is formed to be wider toward the end, the range affected by the drain electric field further extends to the inside of the channel region 20 as compared with the case where the side wall of the insulated gate is formed to be a vertical surface. As shown in FIG. 3, the distance between the gate insulating films 14 at the end of the channel region 20 on the source region 18 side is H ₀ , and the distance between the gate insulating films 14 at the end on the drain region 12 side is H _1. For example, in order to realize a device having a pentode characteristic, the condition of L> H ₀ + H ₁ must be satisfied.

As described above, in order to realize a device having a pentode characteristic, it is desirable that the sidewalls of the insulated gate that sandwich the channel region 20 be as vertical as possible to the surface of the device, and further, the channel length L. It can be understood that a certain condition (L / H> 3 as a realistic value) must be satisfied.

The static induction thyristor having the above-mentioned structure is manufactured by the steps shown in FIGS. First, as shown in FIG. 4, n having a predetermined thickness and a predetermined impurity concentration is formed on the p ⁺ type substrate (drain region) 12.
^- type epitaxial layer is grown (drain region) 11, the the surface of the n ^- -type epitaxial layer 11, the side wall the n ^- to form a substantially vertical groove region on the surface of the type epitaxial layer 11, the inner surface of the groove area The gate insulating film 14 is formed and the gate electrode 1 is formed in the gate insulating film 14.
5 is formed and the interlayer insulating film 16 is formed on the surface thereof, thereby embedding the insulated gate in the groove region.

Next, as shown in FIG. 5, the surface of the n ^-- type epitaxial layer 11 other than the insulated gate is removed by etching to a depth of several thousand Å, and the etched surface is p-doped.
Impurities for forming the ⁺ type contact region 18 are ion-implanted.

Next, as shown in FIG. 6, sidewall portions 21 made of Si ₃ N ₄ are formed on the sidewall portions of the gate insulating film 14 and the interlayer insulating film 16 exposed by etching. The sidewall portion 21 is formed by depositing a uniform Si ₃ N ₄ film of about 5000 Å everywhere on the entire surface of the etched n ⁻ type epitaxial layer 11 and removing it by anisotropic etching. It is formed.

Further, as shown in FIG. 7, the surface of the n ⁻ type drain region 11 is removed by etching to a depth of about 2000 Å using the sidewall portion 21 as a mask, and then impurities for forming the n ⁺ type source region 17 are formed. Is ion-implanted.

Then, as shown in FIG. 8, Si _{3 is} formed on the surface.
An N ₄ film 22 of about 2000 Å is deposited and annealed at 1000 ° C. for about 20 minutes in a nitrogen atmosphere to activate the ion-implanted impurities and n ⁺ type source region 1
7 and p ⁺ type contact region 18 are formed. After that, the Si ₃ N ₄ film 22 on the surface is removed by hot phosphoric acid and the source electrode 19 is formed on the surface, whereby an electrostatic induction thyristor having a structure as shown in FIG. 1 can be obtained.

As described above, in the electrostatic induction thyristor of this embodiment, the gate insulating film 14 and the source electrode 1 are included.
Since the p ⁺ -type contact region 18 which is in contact with both the electrodes 9 and 9 is provided, the n ⁺ -type source region 1 is
A large number of holes existing in the n ⁻ -type drain region 11 near 7 can be made to flow to the source electrode 19 through the inversion layer near the gate insulating film 14 and the p ⁺ -type contact region 18, and a quick turn-off is realized. As a result, the power consumption can be reduced. Further, since the inversion layer formed in the vicinity of the gate insulating film 14 in the static OFF state is also in contact with the p ⁺ type contact region 18, the potential of the inversion layer of the p ⁺ type contact region 18 and the source electrode 19 is increased. It is fixed at the same potential as the potential. As a result, even when a high voltage is applied to the drain electrode, the voltage applied to the gate insulating film 14 is held constant, and the conventional electrostatic breakdown of the insulating film 14 can be avoided.

-Modification of First Embodiment- In the first embodiment described above, the n ⁺ type source region 17 and the side surface of the gate insulating film 14 are not in direct contact with each other, but they are in contact with each other. May be. That is, as shown in FIG. 9, p ⁺ type contact regions 18 are formed at a predetermined interval at the boundary between the n ⁺ type source region 17 and the gate insulating film 14, and the gate insulating film 14 serves as the p ⁺ type contact region. 18 and the n ⁺ type source region 17 may be alternately contacted. In this way, a part of the n ⁺ type source region 17 is brought into contact with the side surface of the gate insulating film 14 to reduce the on-resistance.

-Second Embodiment- FIG. 10 is a sectional view showing an electrostatic induction thyristor which is a second embodiment of the electrostatic induction semiconductor device according to the present invention. In the following description, the same components as those in the above-described first embodiment will be designated by the same reference numerals to simplify the description.

In this embodiment, the p ⁺ type drain region 12 and the drain electrode 13 are formed on the same surface as the source electrode 19, and the n ⁺ type drain region 23 is formed on the back side of the n ⁻ type drain region 11. And the drain electrode 24 is formed.

Therefore, also in this embodiment, the first
An electrostatic induction thyristor that performs the same operation as that of the embodiment can be realized, and the same effect can be obtained. In particular,
In this embodiment, the drain voltage is n ⁻ type drain region 11
And the p ⁺ -type drain region 12 have a build-in (internal) voltage (about 0.6 V) or less, a current path of n ⁺ -type drain region 23 → n ⁻ -type drain region 11 → n ⁺ -type source region 18 Is ensured and the unipolar operation is performed, which has the advantage that the increase in ON resistance can be suppressed.

Third Embodiment FIG. 11 is a sectional view showing an electrostatic induction thyristor which is a third embodiment of the electrostatic induction semiconductor device according to the present invention. In this embodiment, instead of the p ⁺ type contact region 20 in the first embodiment, the n ⁻ type drain region 11 and the source electrode 19 are brought into direct contact with each other, and the Schottky junction 25 is formed between them. There is. Therefore, according to this embodiment,
It is possible to obtain the same effect as that of the first embodiment described above.

Fourth Embodiment FIG. 11 is a sectional view showing an electrostatic induction transistor which is a fourth embodiment of the electrostatic induction semiconductor device according to the present invention. In this embodiment, in place of the p ⁺ type drain region 12 in the first embodiment described above, n ^{+ is formed on} the back side of the n ⁻ type drain region 11.
The mold drain region 26 is formed. Therefore, according to this embodiment as well, it is possible to obtain the same effects as those of the first embodiment described above. In particular, since the electrostatic induction transistor of this embodiment performs a unipolar operation, it has an advantage that the n ⁻ -type drain region 11 is not conductivity-modulated in the ON state and the turn-off time is short.

The details of the electrostatic induction semiconductor device of the present invention are not limited to the above-mentioned embodiments, and various modifications are possible.

[0044]

As described above in detail, according to the first aspect of the invention, the contact region having the conductivity type opposite to that of the source region is provided in contact with both the gate insulating film and the source electrode. According to the invention of claim 2, at least a part of the drain region is in direct contact with the source electrode to form a Schottky junction. As a result, at turn-off, a large amount of minority carriers existing in the drain region near the source region can flow to the source electrode via the contact region or the Schottky junction via the inversion layer near the gate insulating film, resulting in a fast turn-off. Can be realized, and power consumption can be reduced. In addition, since the inversion layer formed near the gate insulating film in the static OFF state is also in contact with this contact region or the Schottky junction, the potential of the inversion layer is fixed to the same potential as the source electrode. As a result, the voltage applied to the gate insulating film is kept constant, and the conventional situation of electrostatic breakdown of the insulating film can be avoided.

[Brief description of drawings]

FIG. 1 is a sectional view showing an electrostatic induction thyristor which is a first embodiment of an electrostatic induction semiconductor device according to the present invention.

FIG. 2 is a diagram for explaining a condition of a distance between gate insulating films.

FIG. 3 is a diagram for explaining a channel length condition.

FIG. 4 is a process drawing for explaining the manufacturing method of the electrostatic induction thyristor of the first embodiment.

FIG. 5 is a view similar to FIG.

FIG. 6 is a view similar to FIG.

FIG. 7 is a view similar to FIG.

FIG. 8 is a view similar to FIG.

9 is a view showing a modified example of the first embodiment, and is a cross-sectional view taken along the line AA ′ of FIG.

FIG. 10 is a sectional view showing an electrostatic induction thyristor which is a second embodiment of the electrostatic induction semiconductor device according to the present invention.

FIG. 11 is a sectional view showing an electrostatic induction thyristor that is a third embodiment of the electrostatic induction semiconductor device according to the present invention.

FIG. 12 is a sectional view showing an electrostatic induction transistor which is a fourth embodiment of the electrostatic induction semiconductor device according to the present invention.

FIG. 13 is a sectional view showing an example of a conventional electrostatic induction thyristor.

[Explanation of symbols]

11 n ^- type drain region 12 p ⁺ type drain region 13 and 24 drain electrode 14 gate insulating film 15 gate electrode 17 n ⁺ type source region 18 p ⁺ type contact region 19 source electrode 20 channel region 23 and 26 n ⁺ type drain region 25 Schottky junction

Claims (2)

[Claims] 1. A drain region made of a semiconductor of the first conductivity type, an insulated gate buried in a U-shaped groove in the surface of the drain region, and a source electrode formed in the surface of the drain region. In a static induction semiconductor device having a first conductivity type source region ohmic-connected, a second ohmic contact formed on a surface of the drain region, in contact with an insulating film of the insulated gate, and ohmic-connected to the source electrode. An electrostatic induction semiconductor device comprising a conductive type contact region. 2. A drain region made of a semiconductor of the first conductivity type, an insulated gate buried in a U-shaped groove in the surface of the drain region, and a source electrode formed in contact with the drain region. In a static induction semiconductor device comprising an ohmic-connected source region of the first conductivity type, at least a part of the drain region is in direct contact with the source electrode, and a Schottky junction is formed on these contact surfaces. An electrostatic induction semiconductor device characterized in that