JPH0548633B2 - - Google Patents

Info

Publication number
JPH0548633B2
JPH0548633B2 JP58168762A JP16876283A JPH0548633B2 JP H0548633 B2 JPH0548633 B2 JP H0548633B2 JP 58168762 A JP58168762 A JP 58168762A JP 16876283 A JP16876283 A JP 16876283A JP H0548633 B2 JPH0548633 B2 JP H0548633B2
Authority
JP
Japan
Prior art keywords
substrate
photoelectric conversion
film
transparent conductive
scanning
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP58168762A
Other languages
Japanese (ja)
Other versions
JPS6059786A (en
Inventor
Masaru Yamano
Yukinori Kuwano
Shoichi Nakano
Tsugufumi Matsuoka
Soichi Sakai
Hirosato Yagi
Nobuhiro Okuda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP58168762A priority Critical patent/JPS6059786A/en
Priority to FR8412006A priority patent/FR2550007A1/en
Publication of JPS6059786A publication Critical patent/JPS6059786A/en
Priority to US06/899,789 priority patent/US4670293A/en
Publication of JPH0548633B2 publication Critical patent/JPH0548633B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/24—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials using chemical vapour deposition [CVD]
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02S—GENERATION OF ELECTRIC POWER BY CONVERSION OF INFRARED RADIATION, VISIBLE LIGHT OR ULTRAVIOLET LIGHT, e.g. USING PHOTOVOLTAIC [PV] MODULES
    • H02S20/00—Supporting structures for PV modules
    • H02S20/20—Supporting structures directly fixed to an immovable object
    • H02S20/22—Supporting structures directly fixed to an immovable object specially adapted for buildings
    • H02S20/23—Supporting structures directly fixed to an immovable object specially adapted for buildings specially adapted for roof structures
    • H02S20/25—Roof tile elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F19/00—Integrated devices, or assemblies of multiple devices, comprising at least one photovoltaic cell covered by group H10F10/00, e.g. photovoltaic modules
    • H10F19/30—Integrated devices, or assemblies of multiple devices, comprising at least one photovoltaic cell covered by group H10F10/00, e.g. photovoltaic modules comprising thin-film photovoltaic cells
    • H10F19/31—Integrated devices, or assemblies of multiple devices, comprising at least one photovoltaic cell covered by group H10F10/00, e.g. photovoltaic modules comprising thin-film photovoltaic cells having multiple laterally adjacent thin-film photovoltaic cells deposited on the same substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F71/00—Manufacture or treatment of devices covered by this subclass
    • H10F71/10—Manufacture or treatment of devices covered by this subclass the devices comprising amorphous semiconductor material
    • H10F71/103—Manufacture or treatment of devices covered by this subclass the devices comprising amorphous semiconductor material including only Group IV materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F77/00—Constructional details of devices covered by this subclass
    • H10F77/10—Semiconductor bodies
    • H10F77/16—Material structures, e.g. crystalline structures, film structures or crystal plane orientations
    • H10F77/169—Thin semiconductor films on metallic or insulating substrates
    • H10F77/1692—Thin semiconductor films on metallic or insulating substrates the films including only Group IV materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/34—Deposited materials, e.g. layers
    • H10P14/3402—Deposited materials, e.g. layers characterised by the chemical composition
    • H10P14/3404—Deposited materials, e.g. layers characterised by the chemical composition being Group IVA materials
    • H10P14/3411—Silicon, silicon germanium or germanium
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B10/00—Integration of renewable energy sources in buildings
    • Y02B10/10—Photovoltaic [PV]
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Landscapes

  • Engineering & Computer Science (AREA)
  • Architecture (AREA)
  • Civil Engineering (AREA)
  • Structural Engineering (AREA)
  • Photovoltaic Devices (AREA)

Description

【発明の詳細な説明】 (イ) 産業上の利用分野 本発明は太陽光等の光エネルギを直接電気エネ
ルギに変換する瓦状光起電力装置の製造方法に関
する。
DETAILED DESCRIPTION OF THE INVENTION (A) Field of Industrial Application The present invention relates to a method for manufacturing a tiled photovoltaic device that directly converts light energy such as sunlight into electrical energy.

(ロ) 従来技術 光エネルギを直接電気エネルギに変換する光起
電力装置、所謂太陽電池は無尽蔵な太陽光を主た
るエネルギ源としているために、エネルギ資源の
枯渇が問題となる中で脚光を浴びている。太陽は
晴天時に約1KW/m2のエネルギを地表に与えて
おり、家庭で斯るエネルギを電気エネルギに変換
する光起電力装置を電力源とする場合、家屋の屋
上或いは屋根上に敷設する方法が一般的である。
(b) Prior Art Photovoltaic devices that directly convert light energy into electrical energy, so-called solar cells, use inexhaustible sunlight as their main energy source, so they have been in the spotlight as energy resources become a problem. There is. The sun gives about 1KW/ m2 of energy to the earth's surface during clear weather, and if a photovoltaic device that converts this energy into electrical energy is used as a power source at home, it is installed on the roof of the house or on the roof. is common.

特開昭57−68454号公報、或いは実開昭58−
11261号公報に開示された太陽電池を備えた屋根
瓦、即ち瓦状光起電力装置は斯る家庭用電力源と
して好適である。
Japanese Unexamined Patent Publication No. 1984-68454 or Utility Model Application No. 1983-
A roof tile equipped with a solar cell, ie, a tile-shaped photovoltaic device, disclosed in Japanese Patent No. 11261 is suitable as such a household power source.

(ハ) 発明の目的 本発明の目的は、斯る家庭用電力源として好適
な太陽電池を備えた屋根瓦の如き曲面状絶縁表面
を瓦状基板とする瓦状光起電力装置の製造方法を
提供することにある。
(c) Purpose of the Invention The purpose of the present invention is to provide a method for manufacturing a tiled photovoltaic device using a tiled substrate having a curved insulating surface such as a roof tile, which is equipped with a solar cell and is suitable as a household power source. It is about providing.

(ニ) 発明の構成 本発明の瓦状光起電力装置の製造方法は、曲面
を有する、絶縁表面を備えた瓦状基板で、該基板
は二主面間が略均等な肉厚を保つ領域を有し、該
領域の一主面には、直接被着された、電極膜と半
導体膜と透明導電膜が積層され一定間隔を隔てて
整列配置された複数の光電変換領域を備え、該光
電変換領域の隣接間隔部では一方の光電変換領域
の上記電極膜と他方の透明導電膜とを重畳するこ
とにより直列接続されて成る瓦状光起電力装置の
製造方法であつて、上記光電変換領域は、対物レ
ンズを通過したエネルギービームを上記曲面の稜
線と平行に走査することにより上記光電変換領域
を分割し上記隣接間隔部を形成すると共に、該隣
接間隔部と上記一定間隔を隔つた隣接間隔部への
走査にあつては、上記隣接間隔部の被加工面と上
記対物レンズとの距離が予め定められた一定値と
なるように該隣接間隔部への走査に先立つて一旦
補正した後、走査することにある。
(d) Structure of the Invention The method for manufacturing a tile-shaped photovoltaic device of the present invention provides a method for manufacturing a tiled photovoltaic device having a curved surface and an insulating surface; A plurality of photoelectric conversion regions are provided on one main surface of the region, in which an electrode film, a semiconductor film, and a transparent conductive film are laminated and arranged at regular intervals, which are directly adhered to each other. A method for manufacturing a tile-shaped photovoltaic device in which the electrode film of one photoelectric conversion region and the transparent conductive film of the other are connected in series by superimposing the electrode film of one photoelectric conversion region and the transparent conductive film of the other photoelectric conversion region in an adjacent interval part of the conversion region, the method comprising: divides the photoelectric conversion region by scanning an energy beam that has passed through an objective lens in parallel with the ridgeline of the curved surface to form the adjacent interval portions, and also divides the adjacent interval portions into adjacent intervals separated by the constant interval. When scanning to the adjacent space, the distance between the surface to be processed in the adjacent space and the objective lens is corrected to a predetermined constant value before scanning to the adjacent space, and then The purpose is to scan.

(ホ) 実施例 第1図及び第2図は本発明製造方法により製造
される瓦状光起電力装置を示し、第1図は斜視
図、第2図は第1図に於けるA−A線断面図であ
つて、1は強化ガラス・透明セラミツクス等の透
光性且つ絶縁性の材料を瓦状に成型し波状の絶縁
表面が付与された基板、2,2…は上記基板1の
うち、二主面間が略均等な肉厚を保つた領域であ
つて、その領域の一主面の絶縁表面に、一定間隔
を隔てて整列配置された複数の光電変換領域であ
る。上記光電変換領域2,2…は、例えば基板1
側から、酸化スズ、酸化インジウムスズ等の透明
導電膜3,3…と、その内部に半導体接合を備え
た非晶質シリコン系の非晶質半導体膜4,4…
と、該半導体膜4,4…とオーミツク接触するア
ルミニウム等の裏面電極膜5,5…と、が順次積
層されたミクロンオーダの膜状を呈する。
(e) Example FIGS. 1 and 2 show a tiled photovoltaic device manufactured by the manufacturing method of the present invention, FIG. 1 is a perspective view, and FIG. It is a line cross-sectional view, and 1 is a substrate formed from a translucent and insulating material such as tempered glass or transparent ceramics into a tile shape and provided with a wavy insulating surface; 2, 2, . , a region having substantially uniform thickness between the two principal surfaces, and a plurality of photoelectric conversion regions arranged at regular intervals on the insulating surface of one principal surface of the region. The photoelectric conversion regions 2, 2... are, for example, the substrate 1
From the side, transparent conductive films 3, 3... made of tin oxide, indium tin oxide, etc., and amorphous silicon-based amorphous semiconductor films 4, 4... with semiconductor junctions therein.
and back electrode films 5, 5, etc., made of aluminum or the like, which are in ohmic contact with the semiconductor films 4, 4, etc., are sequentially laminated to have a film shape on the order of microns.

各非晶質半導体膜4,4…は、その内部に例え
ば膜面に平行なPIN接合を形成すべく受光面側か
ら厚み50〜250Å程度のP型層、4000〜7000Å程
度のI型(真性)層及び300〜600Å程度のN型層
が順次積層被着され、従つて基板1及び透明導電
膜3,3…を透過して光入射があると、主にI型
層の於いて自由状態の電子及び正孔が発生し、斯
る電子及び正孔は上記各層が形成するPIN接合電
界に引かれて各透明導電膜3,3…及び裏面電極
膜5,5…に集電され、隣接する光電変換領域
2,2…の透明導電膜3,3…と裏面電極膜5,
5…との重畳により電気的に相加された電力が取
り出される。
Each amorphous semiconductor film 4, 4... has a P-type layer with a thickness of about 50 to 250 Å from the light-receiving surface side and an I-type (intrinsic) layer with a thickness of about 4000 to 7000 Å in order to form a PIN junction parallel to the film surface. ) layer and an N-type layer of about 300 to 600 Å are sequentially deposited, so that when light is incident through the substrate 1 and the transparent conductive films 3, 3, etc., the I-type layer is mainly in a free state. Electrons and holes are generated, and these electrons and holes are attracted by the PIN junction electric field formed by each of the above layers and are collected by each transparent conductive film 3, 3... and back electrode film 5, 5..., and the adjacent The transparent conductive films 3, 3... of the photoelectric conversion regions 2, 2... and the back electrode film 5,
5... The electrically added power is taken out.

第3図乃至第10図は本発明製造方法を説明す
るための要部拡大断面図及び概略的斜視図であ
る。
FIGS. 3 to 10 are an enlarged sectional view and a schematic perspective view of essential parts for explaining the manufacturing method of the present invention.

第3図の工程では、基板1の周縁部をマスクで
覆つた状態で複数の光電変換領域2,2…を含む
曲面状絶縁表面全域に、電子ビーム蒸着により直
接被着された厚み500Å〜4000Åの酸化インジウ
ムスズ及び酸化スズの積層構造から成る透明導電
膜3が、レーザビームの如きエネルギビームの照
射により各光電変換領域2,2…毎に分割され
る。使用されるレーザは波長1.06μm、エネルギ
密度7×107W/cm2、パルス周波数3KHzのNd:
YAGレーザが適当であり、対物レンズf50mm、走
査速度50mm/secによりパターニングされる。こ
のレーザパターニングにより除去された透明導電
膜3の間隔L1は約50μmに設定される。
In the process shown in FIG. 3, a film with a thickness of 500 Å to 4000 Å is directly deposited by electron beam evaporation over the entire curved insulating surface including a plurality of photoelectric conversion regions 2, 2, etc. with the peripheral edge of the substrate 1 covered with a mask. A transparent conductive film 3 having a laminated structure of indium tin oxide and tin oxide is divided into photoelectric conversion regions 2, 2, . . . by irradiation with an energy beam such as a laser beam. The laser used is Nd with a wavelength of 1.06μm, an energy density of 7×10 7 W/cm 2 , and a pulse frequency of 3KHz:
A YAG laser is suitable, and patterning is performed using an objective lens of f50 mm and a scanning speed of 50 mm/sec. The interval L1 between the transparent conductive films 3 removed by this laser patterning is set to about 50 μm.

斯るレーザパターニングで留意しなければなら
ないことは被加工面である透明導電膜3との距離
が大幅に変動してはならないことである。即ち、
対物レンズに入射したレーザビームは、該レンズ
による収束作用によりエネルギ密度及び加工幅が
制御されるために、上述の如く被加工面との距離
が大幅に変動すると、エネルギ密度及び加工幅も
変動し所望の加工を施すことができなくなるから
である。
What must be kept in mind in such laser patterning is that the distance to the transparent conductive film 3, which is the surface to be processed, must not vary significantly. That is,
The energy density and machining width of the laser beam incident on the objective lens are controlled by the convergence effect of the lens, so if the distance to the workpiece surface changes significantly as described above, the energy density and machining width will also fluctuate. This is because it becomes impossible to perform desired processing.

従つて本発明にあつては、曲面状絶縁表面に直
接被着された透明導電膜3を各光電変換領域2,
2…毎に分割せしめる際に、第4図に示す如く基
板1を載置しX軸、Y軸及びZ軸方向に移動せし
めるXYZステージ6の上記X軸方向と、基板1
表面に於ける稜線7方向と、を一致せしめ、斯る
X軸方向に移動する過程に於いて上記レーザビー
ム8を照射し対物レンズ9と被加工面との距離を
一定に保つている。次いで、一つの隣接間隔部に
位置する透明導電膜3の除去が基板1のX軸方向
の移動による走査によつて終了すると、XYZス
テージ6は次に除去すべき隣接間隔部に位置する
透明導電膜3と対物レンズ9とが対向すべく基板
1をY軸方向に移動せしめる。この状態に於い
て、上記対物レンズ9と被加工面との距離は基板
1の曲面壮絶縁表面がY軸方向に変化しているた
めに先のレーザビーム照射時と異なつており、
XYZステージ6をZ軸方向に上昇或いは下降せ
しめ予め定められた距離に一旦補正し、斯る補正
を上記隣接間隔部に位置する透明導電膜3へのレ
ーザビーム照射に先立つて行つた後、再びXYZ
ステージ6をX軸方向に移動せしめ隣接間隔部に
位置する不要な透明導電膜3をレーザビーム9の
照射により除去する。以後、斯る動作を繰返し行
ない透明導電膜3,3…を曲面の稜線7と平行に
パターニングする。
Therefore, in the present invention, the transparent conductive film 3 directly adhered to the curved insulating surface is attached to each photoelectric conversion region 2,
When dividing the substrate 1 into 2... parts, the XYZ stage 6 on which the substrate 1 is placed and moved in the
The distance between the objective lens 9 and the surface to be processed is kept constant by irradiating the laser beam 8 during the process of moving in the X-axis direction. Next, when the removal of the transparent conductive film 3 located in one adjacent gap is completed by scanning by moving the substrate 1 in the X-axis direction, the XYZ stage 6 moves the transparent conductive film 3 located in the next adjacent gap to be removed. The substrate 1 is moved in the Y-axis direction so that the film 3 and the objective lens 9 face each other. In this state, the distance between the objective lens 9 and the surface to be processed is different from that during the previous laser beam irradiation because the curved insulating surface of the substrate 1 is changing in the Y-axis direction.
The XYZ stage 6 is raised or lowered in the Z-axis direction to once make a correction to a predetermined distance, and after making such correction prior to laser beam irradiation to the transparent conductive film 3 located in the adjacent interval, the XYZ
The stage 6 is moved in the X-axis direction, and the unnecessary transparent conductive film 3 located at the adjacent interval is removed by irradiation with the laser beam 9. Thereafter, such an operation is repeated to pattern the transparent conductive films 3, 3, . . . parallel to the ridge line 7 of the curved surface.

以上のように、本発明製造方法によれば、稜線
7と平行にレーザビーム8を照射することから、
レーザビームの走査時には常に対物レンズ9と被
加工面との距離を一定とすることが可能となる。
As described above, according to the manufacturing method of the present invention, since the laser beam 8 is irradiated parallel to the ridge line 7,
During laser beam scanning, it is possible to always keep the distance between the objective lens 9 and the surface to be processed constant.

このことは、レーザビーム8の照射後、その隣
接間隔部への照射に当つては、斯る部分でのレー
ザビーム照射に先立つて、その被加工面と対物レ
ンズとの距離補正を一旦行つておけば、そのレー
ザビーム照射中の上記補正を不要とすることがで
きる。
This means that after irradiation with the laser beam 8, when irradiating adjacent spaced parts, the distance between the surface to be processed and the objective lens must be corrected before irradiating the laser beam on that part. If this is done, the above correction during laser beam irradiation can be made unnecessary.

また、この様な安定した補正を行い得ることか
ら、本発明製造方法による瓦状光起電力装置にあ
つては、各光電変換領域の特性が安定斯すること
となり、光起電力装置自体の特性向上を図ること
ができる。
In addition, since such stable correction can be performed, in the tile-shaped photovoltaic device produced by the manufacturing method of the present invention, the characteristics of each photovoltaic conversion region are stabilized, and the characteristics of the photovoltaic device itself are stabilized. You can improve your performance.

透明導電膜3,3…のパターニング後、非晶質
半導体膜2の被着工程に移る。第5図はモノシラ
ン(SiH4)、ジシラン(Si2H6)等のシリコン化
合物雰囲気中でグロー放電を励起し、反応ガスを
プラズマ分解して基板1上に非晶質シリコン(a
−Si:H)、非晶質シリコンカーバイド(a−Six
Ci-x:H)、非晶質シリコンスズ(a−SiySni-y:
H)等の非晶質シリコン系の非晶質半導体膜4を
被着する工程を模式的に示している。シリコン化
合物雰囲気中でのグロー放電により非晶質シリコ
ンの薄膜が得られることは例えば特公昭53−
37718号公報に開示された如く既に知られている。
即ち、従来知られたグロー放電による非晶質半導
体の形成は、該半導体膜を被着すべきガラス、ス
テンレス等の基板を、相対向しグロー放電を励起
する平行電極間に位置せしめているために、基板
がプラズマの高速荷電粒子の移動範囲に於いてそ
の移動方向と直交する結果、斯るプラズマ中の高
速荷電粒子が基板1の表面に衝突し、透明導電膜
3,3…或いは形成されつつある非晶質半導体膜
4の特性が悪化する欠点を備えている。しかも、
非晶質半導体膜4が被着せしめられる基板1の表
面は従来平坦であつたのに対し、本発明のそれは
曲面状表面であり、従つて従来の如く平行平板電
極間に曲面状表面を備えた基板1を配置せしめた
のでは斯る曲面状表面と対向する一方の平行平板
電極との対向距離が不揃いとなるために、被着せ
しめられる非晶質半導体膜4は非均一とならざる
を得ない。
After patterning the transparent conductive films 3, 3, . . . , the process moves to the step of depositing the amorphous semiconductor film 2. FIG. 5 shows that glow discharge is excited in an atmosphere of silicon compounds such as monosilane (SiH 4 ) and disilane (Si 2 H 6 ), and amorphous silicon (a
-Si:H), amorphous silicon carbide (a-Si x
C ix : H), amorphous silicon tin (a-Si y Sn iy :
This schematically shows a step of depositing an amorphous silicon-based amorphous semiconductor film 4 such as H). For example, the fact that a thin film of amorphous silicon can be obtained by glow discharge in a silicon compound atmosphere is reported in
This is already known as disclosed in Publication No. 37718.
That is, in the conventionally known formation of an amorphous semiconductor by glow discharge, a substrate made of glass, stainless steel, etc. to which the semiconductor film is to be deposited is placed between parallel electrodes that face each other and excite glow discharge. In addition, as a result of the substrate being perpendicular to the moving direction of the high-speed charged particles in the plasma, the high-speed charged particles in the plasma collide with the surface of the substrate 1, and the transparent conductive films 3, 3... or are formed. This has the disadvantage that the characteristics of the amorphous semiconductor film 4 are deteriorated. Moreover,
While the surface of the substrate 1 on which the amorphous semiconductor film 4 is deposited has conventionally been flat, the surface of the present invention has a curved surface. When the substrate 1 is arranged, the facing distance between the curved surface and one of the parallel plate electrodes facing the surface becomes uneven, so that the deposited amorphous semiconductor film 4 has to be non-uniform. I don't get it.

そこで本発明に用いらえる曲面壮絶縁表面を備
えた基板1は相対応する平行平板電極間に配置さ
れるのではなく、斯る平行平板電極の外で且つ電
極の対向面に対し基板1の被着表面を実質的に垂
直方向に配置せしめると共に、該基板1を図中矢
印で示す如き表面の曲面方向、即ち稜線7に対し
て垂直方向に移動させながら非晶質半導体膜4を
形成せしめている。即ち、第5図の実施例にあつ
ては、上記平行平板電極はアース電極10,1
0,10と、高周波電源11に連なる高周波電極
12,12とを交互に相対向せしめたマルチ電極
構造を構成し、それ等電極10,12,10…の
並設方向に基板1を移動せしめている。
Therefore, the substrate 1 with a curved insulating surface used in the present invention is not disposed between corresponding parallel plate electrodes, but is placed outside the parallel plate electrodes and on the opposite surface of the substrate 1. The amorphous semiconductor film 4 is formed by arranging the adhered surface in a substantially vertical direction and moving the substrate 1 in the direction of the curved surface of the surface as shown by the arrow in the figure, that is, in the direction perpendicular to the ridgeline 7. ing. That is, in the embodiment shown in FIG. 5, the parallel plate electrodes are ground electrodes 10, 1.
A multi-electrode structure is constructed in which high-frequency electrodes 0, 10 and high-frequency electrodes 12, 12 connected to a high-frequency power source 11 are made to face each other alternately, and the substrate 1 is moved in the direction in which the electrodes 10, 12, 10... are arranged in parallel. There is.

しかし、上記マルチ電極構造に関し、基本的に
は互いに対向する一つのアース電極10と、一つ
の高周波電極12との間に於いてグロー放電が励
起され両電極間にプラズマが発生し、反応ガスを
分解して得られた例えばシリコン原子が該両電極
の外に近接配置された基板1の曲面状表面に付着
することによつて、序々に非晶質半導体膜4が形
成されるので、必ずしもマルチ電極構造を採用す
る必要はない。
However, regarding the above multi-electrode structure, basically, a glow discharge is excited between one earth electrode 10 and one high-frequency electrode 12, which face each other, and plasma is generated between both electrodes, which generates a reactive gas. For example, silicon atoms obtained by decomposition adhere to the curved surface of the substrate 1 disposed close to the outside of the two electrodes, so that the amorphous semiconductor film 4 is gradually formed. It is not necessary to adopt an electrode structure.

この様に基板1を、互いに相対向するアース電
極10,10,10と、高周波電極12,12の
外に配置することによつて、基板1の被着表面は
プラズマ中での高速荷電粒子の移動領域から外
れ、斯る荷電粒子の衝突が大幅に軽減される結
果、非晶質は半導体膜4へのダメージが低減さ
れ、次いで非晶質半導体膜4の形成(被着)工程
を、基板1をその表面の曲面方向(電極の並設方
向)に移動する過程に施すことによつて、第6図
の示す如く均一性の高い非晶質半導体膜4が得ら
れる。
By arranging the substrate 1 outside the ground electrodes 10, 10, 10 and the high frequency electrodes 12, 12, which face each other in this way, the adhesion surface of the substrate 1 is protected against high-speed charged particles in the plasma. As a result of being removed from the moving region and the collision of such charged particles is significantly reduced, damage to the amorphous semiconductor film 4 is reduced, and the formation (deposition) process of the amorphous semiconductor film 4 is then performed on the substrate. 1 in the process of moving in the curved direction of the surface (the direction in which the electrodes are arranged in parallel), an amorphous semiconductor film 4 with high uniformity can be obtained as shown in FIG.

しかも、非晶質半導体膜形成時に於ける高速荷
電粒子によるダメージを低減すべく抑えられてい
た高周波出力を、高めることができ膜の成長速度
を上昇せしめることも可能となる。
Moreover, the high frequency output, which has been suppressed to reduce damage caused by high-speed charged particles during the formation of an amorphous semiconductor film, can be increased, and the growth rate of the film can also be increased.

尚、斯る第5図の実施例にあつては、基板1は
互いに相対向配置されたアース電極10,10,
10及び高周波電極12,12を挾むように2枚
設けられており、従つて同時に2枚の基板1,1
に対し、非晶質半導体膜4の形成が実行される。
この時基板1,1を加熱すべきヒータは図示して
いない反応室の側壁の凹所に埋設保持され、該基
板1,1の各々をその被着面背後から均一に加熱
している。
In the embodiment shown in FIG. 5, the substrate 1 has ground electrodes 10, 10,
10 and high frequency electrodes 12, 12, and therefore two substrates 1, 1 are provided at the same time.
On the other hand, formation of the amorphous semiconductor film 4 is performed.
At this time, a heater for heating the substrates 1, 1 is buried and held in a recess in the side wall of the reaction chamber (not shown), and uniformly heats each of the substrates 1, 1 from behind the surface to which it is attached.

第7図は非晶質半導体膜4の他の被着(形成)
工程を模式的に示し、先の実施例、即ち第1の実
施例とは、アース電極10,10及び高周波電極
12,12と、基板1との対向状態と、更には反
応ガスを吐出するガス供給体13の具体的構造に
於いて相違する。即ち、基板1と対向する各アー
ス電極10,10及び高周波電極12,12の対
向面10a,12a…は基板1表面の曲面と平行
に対向すべく同形状の曲面を呈している。従つ
て、同形状の曲面の各電極10,12…の対向面
10a,12a…に付与することにより、該対向
面10a,12a…と基板1表面との対向距離は
等しくなる結果、均一な非晶質半導体膜4の形成
を基板1が停止した状態でも行なうことができる
が、より均一な非晶質半導体膜4を得ようとした
場合、やはり図中矢印で示す如く第1の実施例と
同様に基板1をアース電極10,10及び高周波
電極12,12の並設方向、(基板1の稜線方向)
への移動過程中に実行した方が好ましい。
FIG. 7 shows another deposition (formation) of the amorphous semiconductor film 4.
The process is schematically shown, and the previous example, that is, the first example, shows the state in which the ground electrodes 10, 10 and the high-frequency electrodes 12, 12 are opposed to the substrate 1, and the gas for discharging the reaction gas. The specific structure of the supply body 13 is different. That is, the opposing surfaces 10a, 12a, . . . of the ground electrodes 10, 10 and high frequency electrodes 12, 12, which face the substrate 1, have curved surfaces having the same shape so as to face parallel to the curved surface of the surface of the substrate 1. Therefore, by applying curved surfaces of the same shape to the opposing surfaces 10a, 12a... of the electrodes 10, 12..., the opposing distances between the opposing surfaces 10a, 12a... and the surface of the substrate 1 become equal, resulting in uniform non-conformity. Although the crystalline semiconductor film 4 can be formed even when the substrate 1 is stopped, in order to obtain a more uniform amorphous semiconductor film 4, it is possible to form the crystalline semiconductor film 4 even when the substrate 1 is stopped. Similarly, the substrate 1 is arranged in the direction in which the ground electrodes 10, 10 and the high frequency electrodes 12, 12 are arranged side by side (in the direction of the ridge line of the substrate 1).
It is preferable to perform this during the process of moving to.

一方、ガス供給体13は多数の吐出口14,1
4…が穿たれたガス吐出面15を、アース電極1
0,10及び高周波電極12,12を挾んで基板
1の曲面状表面と対向すべく配置し、斯るガス吐
出面15と曲面状表面との対向距離を等しくすべ
くガス吐出面15も基板1表面と同形状の曲面状
を呈している。吐出せしめられる反応ガスは形成
すべき非晶質半導体により異なるが、例えば非晶
質シリコンの場合、モノシラン(SiH4)及びま
たはジシラン(Si2H6)をベースに、P型決定不
純物を含むジボラン(B2H6)、若しくはN型決定
不純物を含むホスフイン(PH3)が適宜添加され
る。尚、斯るガス供給体13に代つて基板1をも
う一枚配置しても良い。
On the other hand, the gas supply body 13 has a large number of discharge ports 14, 1
The gas discharge surface 15 with holes 4... is connected to the ground electrode 1
0, 10 and high-frequency electrodes 12, 12 are placed in between to face the curved surface of the substrate 1, and the gas discharge surface 15 is also arranged to face the curved surface of the substrate 1 in order to equalize the facing distance between the gas discharge surface 15 and the curved surface. It has the same curved shape as the surface. The reactive gas discharged varies depending on the amorphous semiconductor to be formed, but for example, in the case of amorphous silicon, it is based on monosilane (SiH 4 ) and/or disilane (Si 2 H 6 ), and diborane containing P-type impurities. (B 2 H 6 ) or phosphine (PH 3 ) containing an N-type determining impurity is added as appropriate. Incidentally, in place of the gas supply body 13, another substrate 1 may be arranged.

上記第1・第2の実施例ともほぼ同一の反応条
件により非晶質半導体膜4を形成することができ
る。
The amorphous semiconductor film 4 can be formed under substantially the same reaction conditions as in the first and second embodiments.

以下にPIN接合型非晶質シリコンを形成する場
合の基本的反応条件を記す。
The basic reaction conditions for forming PIN junction type amorphous silicon are described below.

Γ基板温度 250〜300℃ Γ高周波電源 13.56MHz Γ高周波出力 100W Γ反応ガス(組成比) P型層 B2H6/SiH4=0.1% I型(ノンドープ)層 SiH4=100% N型層 PH3/SiH4=1% Γガス圧 0.3〜1Torr Γガス流量 10〜40c.c./mit この様にして基板1の曲面状表面に均一に被着
形成された被晶質シリコンの如き非晶質半導体4
は第4図に示したようにXYZステージ6に載置
されて、第8図の工程でその隣接間隔部がレーザ
ビーム8の照射により除去されて各光電変換領域
2,2…毎に分離形成されると共に、該除去され
た非晶質半導体膜4,4…に覆われていた透明導
電膜3,3…の一部がレーザビーム8の走査方向
全長に亘つて露出せしめられる。使用されるレー
ザは波長1.06μm、エネルギ密度5×107W/cm2、
パルス周波数3KHzのNd:YAGレーザであり、
除去された非晶質半導体膜4…の間隔L2は約
200μmに設定される。
Γ Substrate temperature 250 to 300℃ Γ High frequency power supply 13.56MHz Γ High frequency output 100W Γ Reactive gas (composition ratio) P type layer B 2 H 6 /SiH 4 = 0.1% I type (non-doped) layer SiH 4 = 100% N type layer PH 3 /SiH 4 = 1% Γ gas pressure 0.3 to 1 Torr Γ gas flow rate 10 to 40 c.c./mit Non-crystalline silicon, which is uniformly deposited on the curved surface of the substrate 1, crystalline semiconductor 4
is placed on the XYZ stage 6 as shown in Fig. 4, and in the process shown in Fig. 8, the adjacent spaced portions are removed by irradiation with the laser beam 8 to form separate photoelectric conversion regions 2, 2... At the same time, parts of the transparent conductive films 3, 3, . . ., which were covered with the removed amorphous semiconductor films 4, 4, . The laser used has a wavelength of 1.06 μm and an energy density of 5×10 7 W/cm 2 .
It is a Nd:YAG laser with a pulse frequency of 3KHz,
The distance L2 between the removed amorphous semiconductor films 4 is approximately
It is set to 200μm.

斯るレーザビーム8の走査方向は透明導電膜
3,3…のそれと同様に、対物レンズ9と被加工
面との距離を一定に保つべくXYZステージ6の
X軸と一致した基板1の曲面状表面に於ける稜線
7方向であり、上記XYZステージ6のX軸方向
の移動により50mm/secの速度で上記レーザビー
ム8は走査される。一つの隣接間隔部のレーザビ
ーム8の走査が終了すると、XYZステージ6を
Y軸方向に移動せしめて次に除去すべき非晶質半
導体膜4…と対物レンズ9とを対向させ、然る後
両者の対向距離を予め定められた一定値に補正す
べくZ軸方向に移動せしめる。そして再びX軸方
向の移動によりレーザビーム8を走査する動作を
繰返し実行し、非晶質半導体膜4,4…を透明導
電膜3,3…の一部を露出せしめた状態で基板1
表面の稜線7と平行にパターニングする。
The scanning direction of the laser beam 8 is similar to that of the transparent conductive films 3, 3, . . . in order to keep the distance between the objective lens 9 and the surface to be processed constant. The laser beam 8 is scanned in the direction of the ridge line 7 on the surface at a speed of 50 mm/sec by moving the XYZ stage 6 in the X-axis direction. When the scanning of one adjacent space with the laser beam 8 is completed, the XYZ stage 6 is moved in the Y-axis direction so that the amorphous semiconductor film 4 to be removed next faces the objective lens 9, and then It is moved in the Z-axis direction to correct the facing distance between the two to a predetermined constant value. Then, the operation of scanning the laser beam 8 by moving in the X-axis direction is repeated again, and the amorphous semiconductor films 4, 4, . . .
Patterning is performed parallel to the ridge line 7 on the surface.

第9図の工程では、裏面電極膜5が非晶質半導
体膜4,4…及び透明導電膜3,3…の露出部3
a,3a…の表面を含んで全光電変換領域2,2
…に跨つて連続的に被着せしめられる。
In the process shown in FIG.
The entire photoelectric conversion area 2, 2 including the surfaces of a, 3a...
It is applied continuously over...

斯る裏面電極膜5の隣接間隔部は、続く第10
図の工程で、一つの光電変換領域2,2…から延
在した裏面電極膜5,5の延長部5a,5a…が
隣接せる光電変換領域2,2…の透明導電膜3,
3…の露出部3a,3a…と結合すべくレーザビ
ーム8の照射により除去され、その間隔L3は
50μmに設定される。使用されるレーザは透明導
電膜3,3…、非晶質半導体膜4,4…と同様波
長1.06μmのNd:YAGレーザであり、XYZステ
ージ6のX軸方向の移動により50mm/secの速度
で走査される。X軸方向の走査後の動作、即ち対
物レンズ9と被加工面との対向距離の補正等につ
いては先のレーザパターニング(除去)工程と同
じにつき説明を割愛する。
The adjacent interval part of the back electrode film 5 is the following 10th
In the process shown in the figure, the transparent conductive films 3 of the photoelectric conversion regions 2, 2... where the extension parts 5a, 5a... of the back electrode films 5, 5 extending from one photoelectric conversion region 2, 2... are adjacent to each other,
3... is removed by irradiation with a laser beam 8 in order to combine with the exposed parts 3a, 3a..., and the interval L3 is
It is set to 50μm. The laser used is an Nd:YAG laser with a wavelength of 1.06 μm, similar to the transparent conductive films 3, 3..., amorphous semiconductor films 4, 4..., and the speed is 50 mm/sec by moving the XYZ stage 6 in the X-axis direction. is scanned. The operations after scanning in the X-axis direction, ie, correction of the facing distance between the objective lens 9 and the surface to be processed, etc., are the same as in the previous laser patterning (removal) process, and therefore will not be described.

レーザビーム8の照射による除去に際し、留意
すべきは除去せんとする膜部分の下に他の膜が存
在しておれば、それに損傷を与えないことであ
る。非晶質シリコン系の非晶質半導体膜4のレー
ザビーム8の加工しきい値密度は、約4×
107W/cm2と透明導電膜3の7×107W/cm2より小
さいために、非晶質半導体膜4の除去工程に於い
てレーザビーム8が透明導電膜3を直撃したとし
ても損傷を与えない。
When removing by irradiation with the laser beam 8, care should be taken not to damage other films if they exist below the film to be removed. The processing threshold density of the laser beam 8 for the amorphous silicon-based amorphous semiconductor film 4 is approximately 4×
10 7 W/cm 2 is smaller than 7×10 7 W/cm 2 of the transparent conductive film 3, so even if the laser beam 8 directly hits the transparent conductive film 3 during the removal process of the amorphous semiconductor film 4, No damage.

然し乍ら、裏面電極膜5を形成可能な材料、即
ち非晶質半導体膜4とオーミツク接触する金属は
加工しきい値エネルギ密度が透明導電膜3のそれ
より高いのが一般的である。例えばアルミニウム
にあつては、該アルミニウムはレーザビームの吸
収率が低く、熱伝導が優れているためにレーザビ
ームの照射熱が散逸する結果、膜厚にも左右され
るが5000Åに於いて約8×107/cm2と透明導電膜
3のそれに比して僅かながら高い値を示す。
However, the material that can form the back electrode film 5, ie, the metal that is in ohmic contact with the amorphous semiconductor film 4, generally has a processing threshold energy density higher than that of the transparent conductive film 3. For example, in the case of aluminum, aluminum has a low laser beam absorption rate and excellent thermal conductivity, so the heat of laser beam irradiation is dissipated, and as a result, at a thickness of about 8 ×10 7 /cm 2 , which is a slightly higher value than that of the transparent conductive film 3.

そこで本発明にあつては裏面電極膜5をアルミ
ニウム単体で構成するのではなく、照射熱の散逸
を少なくすべくアルミニウムの膜厚を約数100Å
と肉薄にすると共に、厚み5000Å程度の吸収率の
高い材料、例えばチタン或いはチタン銀合金を表
面に積層することによつて加工しきい値エネルギ
密度を2×107W/cm2と低減せしめている。また
裏面電極膜5を上記チタン或いはチタン銀合金単
独で構成しても良い。
Therefore, in the present invention, the back electrode film 5 is not made of aluminum alone, but the thickness of the aluminum film is approximately several 100 Å in order to reduce the dissipation of irradiated heat.
The processing threshold energy density is reduced to 2×10 7 W/cm 2 by making the material thinner and by layering a material with high absorption rate, such as titanium or titanium-silver alloy, with a thickness of about 5000 Å on the surface. There is. Further, the back electrode film 5 may be composed of the above-mentioned titanium or titanium-silver alloy alone.

(ヘ) 発明の効果 本発明は以上の説明から明らかな如く、曲面を
有する瓦状基板の絶縁表面に、直接膜状の光電変
換領域を被着しているので、瓦状基板を光電変換
領域の支持基板と屋根瓦として兼用することがで
き、光電変換領域を披着するための基板を別途必
要とせず、また光電変換領域を非着した基板を瓦
状基板に被着する工程も不要となり、構成並びに
製造工程が簡単になる。
(F) Effects of the Invention As is clear from the above description, the present invention directly adheres a photoelectric conversion region in the form of a film to the insulating surface of a tiled substrate having a curved surface. It can be used both as a supporting substrate and as a roof tile, eliminating the need for a separate substrate for attaching the photoelectric conversion area, and also eliminating the need for the process of attaching the substrate without the photoelectric conversion area to the tile-shaped substrate. , the configuration and manufacturing process are simplified.

更に、瓦状基板に直接非着された膜状の光電変
換領域に対し、上記曲面の稜線と平行にエネルギ
ビームを照射するので、上記光電変換領域を、そ
れらの隣接間隔を極めて減縮した状態で簡単に複
数の領域に曲面に沿つて分割することができ、発
電に寄与する有効面積の上昇が図れる。
Furthermore, since the energy beam is irradiated parallel to the ridgeline of the curved surface to the film-like photoelectric conversion region that is not directly attached to the tile-like substrate, the photoelectric conversion region can be formed in a state where the distance between adjacent regions is extremely reduced. It can be easily divided into multiple regions along a curved surface, increasing the effective area that contributes to power generation.

また、本発明によればエネルギビームの照射
後、その隣接間隔部への照射に当つて、斯る部分
での上記エネルギビーム照射で使用する対物レン
ズと、被加工面との距離を予め定めされた一定値
とする補正を、該隣接間隔部へのエネルギビーム
の走査に先立つて一旦行うことによつて、好適な
分割を行い得る。
Further, according to the present invention, after irradiating the energy beam, when irradiating the adjacent spaced portion, the distance between the objective lens used for irradiating the energy beam at that portion and the surface to be processed is determined in advance. Suitable division can be achieved by once making a correction to a constant value before scanning the energy beam to the adjacent spaced portion.

このことは、前述した上記稜線と平行にエネル
ギビームを照射することとしたことから、エネル
ギビーム走査中の上記距離補正を要しないことと
なり、工程が複雑化することがない。また、斯る
補正により、本発明製造方法による瓦状光起電力
装置の各光電変換領域の特性の安定化を図ること
が可能となる。
This means that since the energy beam is irradiated parallel to the above-mentioned ridgeline, the distance correction described above during scanning of the energy beam is not required, and the process is not complicated. Furthermore, such correction makes it possible to stabilize the characteristics of each photoelectric conversion region of the shingled photovoltaic device produced by the manufacturing method of the present invention.

【図面の簡単な説明】[Brief explanation of the drawing]

図は本発明の実施例を示し、第1図は本発明製
造方法により製造される光起電力装置の斜視図、
第2図は第1図に於けるA−A′線断面図、第3
図、第6図及び第8図乃至第10図は製造工程を
順次説明するための要部拡大断面図、第4図はレ
ーザパターニング(除去)工程の概略的斜視図、
第5図は非晶質半導体の被着(形成)工程の第1
実施例を示す概略的斜視図、第7図は非晶質半導
体の被着(形成)工程の第2実施例を示す概略的
斜視図である。 1……基板、2……光電変換領域、4……非晶
質半導体膜、6……XYZステージ、8……レー
ザビーム、10……アース電極、12……高周波
電。
The figures show examples of the present invention, and FIG. 1 is a perspective view of a photovoltaic device manufactured by the manufacturing method of the present invention;
Figure 2 is a sectional view taken along line A-A' in Figure 1, and Figure 3
6 and 8 to 10 are enlarged cross-sectional views of main parts for sequentially explaining the manufacturing process, and FIG. 4 is a schematic perspective view of the laser patterning (removal) process.
Figure 5 shows the first step of the amorphous semiconductor deposition (formation) process.
A schematic perspective view showing an embodiment. FIG. 7 is a schematic perspective view showing a second embodiment of an amorphous semiconductor deposition (formation) process. DESCRIPTION OF SYMBOLS 1...Substrate, 2...Photoelectric conversion region, 4...Amorphous semiconductor film, 6...XYZ stage, 8...Laser beam, 10...Ground electrode, 12...High frequency electric field.

Claims (1)

【特許請求の範囲】[Claims] 1 曲面を有する、絶縁表面を備えた瓦状基板
で、該基板は二主面間が略均等な肉厚を保つ領域
を有し、該領域の一主面には、直接被着された、
電極膜と半導体膜と透明導電膜が積層され一定間
隔を隔てて整列配置された複数の光電変換領域を
備え、該光電変換領域の隣接間隔部では一方の光
電変換領域の上記電極膜と他方の透明導電膜とを
重畳することにより直列接続されて成る瓦状光起
電力装置の製造方法であつて、上記光電変換領域
は、対物レンズを通過したエネルギービームを上
記曲面の稜線と平行に走査することにより上記光
電変換領域を分割し上記隣接間隔部を形成すると
共に、該隣接間隔部と上記一定間隔を隔たつた隣
接間隔部への走査にあつては、上記隣接間隔部の
被加工面と上記対物レンズとの距離が予め定めら
れた一定値となるように該隣接間隔部への走査に
先立つて一旦補正した後、走査することを特徴と
した瓦状光起電力装置の製造方法。
1. A tile-shaped substrate having a curved surface and an insulating surface, the substrate has a region where the thickness is maintained substantially even between the two main surfaces, and one main surface of the region is directly adhered to.
A plurality of photoelectric conversion regions are provided in which an electrode film, a semiconductor film, and a transparent conductive film are laminated and arranged at regular intervals. A method for manufacturing a tile-shaped photovoltaic device formed by superimposing and connecting transparent conductive films in series, wherein the photoelectric conversion region scans an energy beam that has passed through an objective lens in parallel to the ridgeline of the curved surface. By this, the photoelectric conversion region is divided to form the adjacent spaced parts, and when scanning to the adjacent spaced part separated from the adjacent spaced part by the constant distance, the processing surface of the adjacent spaced part and the part to be processed are separated. A method for manufacturing a tile-shaped photovoltaic device, characterized in that the scanning is performed after first correcting the distance from the objective lens to a predetermined constant value prior to scanning to the adjacent spaced portion.
JP58168762A 1983-07-29 1983-09-12 Manufacture of photovoltaic device Granted JPS6059786A (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP58168762A JPS6059786A (en) 1983-09-12 1983-09-12 Manufacture of photovoltaic device
FR8412006A FR2550007A1 (en) 1983-07-29 1984-07-27 Method for producing a semiconducting film and photovoltaic device obtained by the method
US06/899,789 US4670293A (en) 1983-07-29 1986-08-22 Method of making semiconductor film

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58168762A JPS6059786A (en) 1983-09-12 1983-09-12 Manufacture of photovoltaic device

Publications (2)

Publication Number Publication Date
JPS6059786A JPS6059786A (en) 1985-04-06
JPH0548633B2 true JPH0548633B2 (en) 1993-07-22

Family

ID=15873966

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58168762A Granted JPS6059786A (en) 1983-07-29 1983-09-12 Manufacture of photovoltaic device

Country Status (1)

Country Link
JP (1) JPS6059786A (en)

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55115376A (en) * 1979-02-26 1980-09-05 Shunpei Yamazaki Semiconductor device and manufacturing thereof
US4292092A (en) * 1980-06-02 1981-09-29 Rca Corporation Laser processing technique for fabricating series-connected and tandem junction series-connected solar cells into a solar battery
FR2503457B1 (en) * 1981-03-31 1987-01-23 Rca Corp SOLAR CELL SYSTEM CONNECTED IN SERIES ON A SINGLE SUBSTRATE
JPS5811261U (en) * 1981-07-14 1983-01-25 長島 正彦 tile

Also Published As

Publication number Publication date
JPS6059786A (en) 1985-04-06

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