JPH0550885B2 - - Google Patents
Info
- Publication number
- JPH0550885B2 JPH0550885B2 JP61010417A JP1041786A JPH0550885B2 JP H0550885 B2 JPH0550885 B2 JP H0550885B2 JP 61010417 A JP61010417 A JP 61010417A JP 1041786 A JP1041786 A JP 1041786A JP H0550885 B2 JPH0550885 B2 JP H0550885B2
- Authority
- JP
- Japan
- Prior art keywords
- resistor
- output
- differential
- current
- terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000001514 detection method Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 230000005540 biological transmission Effects 0.000 description 2
- 230000003321 amplification Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 229920006395 saturated elastomer Polymers 0.000 description 1
Landscapes
- Control Of Voltage And Current In General (AREA)
- Amplifiers (AREA)
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は差動電流源に関し、特に差動出力型の
電流源に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a differential current source, and particularly to a differential output type current source.
従来、この種の差動出力型の電流源としては、
カレントミラー回路を主体とした回路構成となつ
ていた。例えば第２図に示すようなものがある。
同図において、端子１０，１１が差動出力端子で
それぞれ負荷Zeに対し、吐出し電流IX、吸込み電
流IYを出力する。カレントミラー回路３１はミラ
ー比0.5：１、カレントミラー回路３２〜３５は
それぞれミラー比１：１である。基準電流I1を流
す電流源と、伝達コンダクタンスアンプGn（以降
Gnアンプと称す）と、Gnアンプの出力端子１
９，２１と、入力端子IN及び同一抵抗値の抵抗
Ｒ９，Ｒ１０を有している。基準電流源の電流I1
は、カレントミラー回路３２，３１，３４を通つ
て差動型の電流として出力される。抵抗R9，R10
は端子１０，２２間電圧と端子１１，２３間電圧
との整合性を検出するもので、それぞれの電圧に
比例した電流がカレントミラー３３と３５とに流
れる。整合がとれていないとGnアンプが駆動さ
れ、Gnアンプの出力電流は、電流加算点A1，A2
及びカレントミラー回路３１，３４を通つて差動
出力端子１０，１１に負帰置される。こうして差
動出力端子１０，１１のバランスがとれ、カレン
トミラー回路３１、又は３４の一方が飽和する事
のない差動電流源が得られる。
Conventionally, this type of differential output type current source is
The circuit configuration was based on a current mirror circuit. For example, there is one shown in FIG.
In the figure, terminals 10 and 11 are differential output terminals that respectively output a discharge current I X and a sink current I Y to a load Z e . Current mirror circuit 31 has a mirror ratio of 0.5:1, and current mirror circuits 32 to 35 each have a mirror ratio of 1:1. A current source that flows a reference current I 1 and a transfer conductance amplifier G n (hereinafter
G n amplifier) and the output terminal 1 of the G n amplifier.
9 and 21, an input terminal IN, and resistors R9 and R10 having the same resistance value. Reference current source current I 1
is output as a differential current through current mirror circuits 32, 31, and 34. Resistance R9 , R10
Detects the consistency between the voltage between the terminals 10 and 22 and the voltage between the terminals 11 and 23, and currents proportional to the respective voltages flow through the current mirrors 33 and 35. If there is no matching, the G n amplifier will be driven, and the output current of the G n amplifier will be the current addition point A 1 , A 2
and is negatively reflected to the differential output terminals 10 and 11 through current mirror circuits 31 and 34. In this way, the differential output terminals 10 and 11 are balanced, and a differential current source is obtained in which either the current mirror circuit 31 or 34 does not become saturated.
上述した従来の差動型電流源が、ミラー回路を
多用するので、ミラー回路個有のエラー即ち、ミ
ラー回路の入力端子側にシリーズに入る複数個の
ダイオード電圧値のオフセツト、有限電流増幅率
hfeによるエラー、電流値の増減によるミラー比
エラーがある。この為精度上問題があつた。
Since the above-mentioned conventional differential current source makes extensive use of mirror circuits, errors inherent in the mirror circuits, such as offsets of voltage values of multiple diodes entering in series on the input terminal side of the mirror circuit, and finite current amplification factors occur.
There are errors due to h fe and mirror ratio errors due to increases and decreases in current value. This caused a problem in accuracy.
本発明の差動型電流は、差動入出力演算増幅器
と、差動入出力演算増幅器の正相入力端子と逆相
出力端子との間に接続された第１の抵抗と、逆相
入力端子と正相出力端子との間に接続された第２
の抵抗と、正相入力端子と正相出力端子との間に
直列に接続された第３、第４の抵抗と、逆相入力
端子と逆相出力端子との間に直列に接続された第
５、第６の抵抗と、正相出力端子と逆相出力端子
との間に直列に接続された第７、第８の抵抗とを
有し、第７の抵抗と第８の抵抗との接続点が前記
差動入出力演算増幅器の同相入力端子に接続さ
れ、電流源が正相または逆相の入力端子に接続さ
れ、第３の抵抗と第４の抵抗との接続点と前記第
５の抵抗と第６の抵抗との接続点とを差動出力端
子とすることを特徴とする。
The differential type current of the present invention includes a differential input/output operational amplifier, a first resistor connected between a positive phase input terminal and a negative phase output terminal of the differential input/output operational amplifier, and a negative phase input terminal. and the second output terminal connected between the positive phase output terminal and the positive phase output terminal.
a third and fourth resistor connected in series between the positive phase input terminal and the positive phase output terminal, and a third resistor connected in series between the negative phase input terminal and the negative phase output terminal. 5. It has a sixth resistor, and seventh and eighth resistors connected in series between the positive phase output terminal and the negative phase output terminal, and the connection between the seventh resistor and the eighth resistor. A point is connected to the common mode input terminal of the differential input/output operational amplifier, a current source is connected to the positive phase or negative phase input terminal, and a point between the third resistor and the fourth resistor is connected to the common mode input terminal of the differential input/output operational amplifier. It is characterized in that the connection point between the resistor and the sixth resistor is a differential output terminal.
次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図は本発明の一実施例の回路図である。第
１図に示す回路は、入力端子I+，I-と、入力端子
I+，I-に加わる電圧の極性と逆極性電圧がそれぞ
れ増巾出力される出力端子，Ｑと、出力電圧の
バランス検出端子CMとを有する差動入出力型演
算増幅器１と、抵抗値が等しく設定された４本の
抵抗Ｒ１〜Ｒ４と、抵抗値が等しく設定された抵
抗Ｒ５，Ｒ６と、抵抗値が等しく設定され、それ
ぞれバランス検出端子CMと差動出力端子Ｑ，
との間に接続された抵抗Ｒ７，Ｒ８と、負荷Zeに
電流値IX，IYなる出力電流を吐出し、吸込み供給
をする差動出力端子２，３と、電流値I1，I0なる
電流を切り換える電流スイツチ回路４１とから成
る。 FIG. 1 is a circuit diagram of an embodiment of the present invention. The circuit shown in Figure 1 consists of input terminals I + , I - and input terminals
A differential input/output type operational amplifier 1 has an output terminal Q to which the polarity and reverse polarity voltage of the voltage applied to I + and I - are respectively amplified and output, and an output voltage balance detection terminal CM, and a resistance value is Four resistors R1 to R4, which are set equally, and resistors R5 and R6, whose resistance values are set equally, are connected to the balance detection terminal CM and the differential output terminal Q, respectively.
resistors R7 and R8 connected between the differential output terminals 2 and 3, which discharge and sink output currents with current values I X and I Y to the load Z e , and current values I 1 and I It consists of a current switch circuit 41 that switches the current to zero .
端子２，３から見た差動電流源の出力インピー
ダンスは、端子２，３間電圧と端子，Ｑ間電圧
の伝送利得が＋１の為、端子２から抵抗Ｒ５側を
見たインピーダンス、又端子３から抵抗Ｒ６側を
見たインピーダンスは、無限大となる。従つて出
力インピーダンスは、抵抗Ｒ１〜Ｒ４の和とな
る。端子２と端子３とのアンバランス性は、抵抗
Ｒ７と抵抗Ｒ８とで検出できる。これは、通常抵
抗Ｒ１〜Ｒ４のインピーダンスを抵抗Ｒ５，Ｒ６
に比し十分大きくとつてあるので可能である。抵
抗Ｒ７と抵抗Ｒ８との中点は、バランス検出端子
CMに帰還接続されており、端子２と端子３との
電圧のバランスを保つ事ができる。 The output impedance of the differential current source seen from terminals 2 and 3 is the impedance seen from terminal 2 to the resistor R5 side, and the impedance seen from terminal 3 because the transmission gain of the voltage between terminals 2 and 3 and the voltage between terminals and Q is +1. The impedance seen from the resistor R6 side becomes infinite. Therefore, the output impedance is the sum of the resistors R1 to R4. The unbalance between terminals 2 and 3 can be detected by resistors R7 and R8. This usually changes the impedance of resistors R1 to R4 to resistors R5 and R6.
This is possible because it is sufficiently large compared to . The midpoint between resistor R7 and resistor R8 is the balance detection terminal.
Feedback connection is made to CM, and the voltage balance between terminal 2 and terminal 3 can be maintained.
次に出力電流IX，IYは次式で表わされる。 Next, the output currents I X and I Y are expressed by the following equations.
IX＝I1／２×R3／R6＝IY
従つて、抵抗R3と抵抗R6との比により、容易
に基準電流の電流値I1を増幅できる。又、電流値
I0とI1とを切換える事により、異なつた差動電流
値を出力でき、データ伝送に利用できる。 I X = I 1 /2×R 3 /R 6 = I Y Therefore, the current value I 1 of the reference current can be easily amplified by the ratio between the resistor R 3 and the resistor R 6 . Also, the current value
By switching between I0 and I1 , different differential current values can be output, which can be used for data transmission.
以上説明したように本発明は、高利得、入力オ
セツト電圧が小さく、入力インピーダンスが高い
差動入出力演算増幅器を使用することにより、高
精度なバランスのとれた差動型電流源を実現でき
る効果がある。又、回路的にもシンプルな構成に
できる。
As explained above, the present invention has the effect of realizing a highly accurate balanced differential current source by using a differential input/output operational amplifier with high gain, low input offset voltage, and high input impedance. There is. Furthermore, the circuit can be made simple.
第１図は本発明の一実施例の回路図、第２図は
従来の差動電流源の回路図である。
１……差動入出力演算増巾器、R1〜R10……抵
抗、Ｉ，I0……基準電流、IX……吐き出し電流、
IY……吸込み電流、Ze……負荷抵抗、３１〜３５
……カレントミラー回路、Gn……伝達コンダク
タンスアンプ。
FIG. 1 is a circuit diagram of an embodiment of the present invention, and FIG. 2 is a circuit diagram of a conventional differential current source. 1...Differential input/output arithmetic amplifier, R1 to R10 ...Resistance, I, I0 ...Reference current, IX ...Source current,
I Y ...Sinking current, Z e ...Load resistance, 31~35
...Current mirror circuit, G n ...Transfer conductance amplifier.
Claims (1)
増幅器の正相入力端子と逆相出力端子との間に接
続された第１の抵抗と、逆相入力端子と正相出力
端子との間に接続された第２の抵抗と、正相入力
端子と正相出力端子との間に直列に接続された第
３、第４の抵抗と、逆相入力端子と逆相出力端子
との間に直列に接続された第５、第６の抵抗と、
正相出力端子と逆相出力端子との間に直列に接続
された第７、第８の抵抗とを有し、第７の抵抗と
第８の抵抗との接続点が前記差動入出力演算増幅
器の同相入力端子に接続され、電流源が正相また
は逆相の入力端子に接続され、前記第３の抵抗と
第４の抵抗との接続点と前記第５の抵抗と第６の
抵抗との接続点とを差動出力端子とすることを特
徴とする差動電流源。1 A differential input/output operational amplifier, a first resistor connected between the positive phase input terminal and the negative phase output terminal of the differential input/output operational amplifier, and a first resistor connected between the negative phase input terminal and the positive phase output terminal. a second resistor connected between, a third and fourth resistor connected in series between the positive phase input terminal and the positive phase output terminal, and between the negative phase input terminal and the negative phase output terminal. fifth and sixth resistors connected in series,
It has seventh and eighth resistors connected in series between the positive phase output terminal and the negative phase output terminal, and the connection point between the seventh resistor and the eighth resistor is the differential input/output operation. A current source is connected to the in-phase input terminal of the amplifier, the current source is connected to the positive-phase or negative-phase input terminal, and the connection point between the third resistor and the fourth resistor and the fifth resistor and the sixth resistor are connected. A differential current source characterized in that a connection point of and a differential output terminal are used.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61010417A JPS62168403A (en) | 1986-01-20 | 1986-01-20 | Differential current source |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61010417A JPS62168403A (en) | 1986-01-20 | 1986-01-20 | Differential current source |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62168403A JPS62168403A (en) | 1987-07-24 |
| JPH0550885B2 true JPH0550885B2 (en) | 1993-07-30 |
Family
ID=11749569
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61010417A Granted JPS62168403A (en) | 1986-01-20 | 1986-01-20 | Differential current source |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62168403A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5320503B2 (en) * | 2010-09-10 | 2013-10-23 | 旭化成エレクトロニクス株式会社 | Amplifier circuit |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5715531B2 (en) | 2010-09-10 | 2015-05-07 | 旭化成エレクトロニクス株式会社 | Single differential converter |
-
1986
- 1986-01-20 JP JP61010417A patent/JPS62168403A/en active Granted
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5320503B2 (en) * | 2010-09-10 | 2013-10-23 | 旭化成エレクトロニクス株式会社 | Amplifier circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS62168403A (en) | 1987-07-24 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPH04351969A (en) | Electric current measuring circuit | |
| EP0453680B1 (en) | Three-terminal operational amplifier and applications thereof | |
| JPH0770935B2 (en) | Differential current amplifier circuit | |
| US4429284A (en) | Operational amplifier | |
| JPH0550885B2 (en) | ||
| JPS63185107A (en) | Voltage control type current source | |
| JP2710507B2 (en) | Amplifier circuit | |
| US4137506A (en) | Compound transistor circuitry | |
| US3548330A (en) | Bipolar amplifier | |
| JPH0346581Y2 (en) | ||
| JPH0619208Y2 (en) | Variable gain circuit | |
| JPH0478044B2 (en) | ||
| US4530044A (en) | Self-balancing DC-substitution measuring system | |
| JPH055503Y2 (en) | ||
| JPS6031126B2 (en) | BTL amplification circuit | |
| JPH0495406A (en) | Differential amplifier circuit | |
| US6031409A (en) | Three-input multiplier and multiplier core circuit used therefor | |
| JPS6223164Y2 (en) | ||
| JPS6126848B2 (en) | ||
| JPH0316066Y2 (en) | ||
| JPH0316065Y2 (en) | ||
| JPS6336747Y2 (en) | ||
| JPS60675Y2 (en) | Signal addition circuit | |
| JPS6223133Y2 (en) | ||
| JPS6118457Y2 (en) |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |