JPH0554681A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To prevent outputting erroneous data even though a memory cell makes an erroneous selection by detecting an address change and controlling the output level of a sense amplifier through a P channel transistor(TR). CONSTITUTION:A sense amplifier consists of P channel TR1 and 2, which configure a current mirror circuit, N channel TR3 and 4 which are serially connected to the N channel TRs and a complementary inverter 5 and the output of the sense amplifier is outputted through an output buffer 19. When an address detecting circuit 18 detects an address change, a P channel TR16 is turned off, the TR2 is turned off through a P channel TR17, the output level of the sense amplifier is reduced and an erroneous data output is prevented during an erroneous selection of the memory cell.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device including a non-volatile memory.

[0002]

2. Description of the Related Art Generally, in a semiconductor memory device including a non-volatile memory, a current detection type sense amplifier circuit that senses the presence or absence of a minute current flowing in a memory cell and electrically outputs a high level or low level signal. Is used.

FIG. 3 is a circuit diagram showing a semiconductor memory device including a conventional current detection type sense amplifier circuit. Figure 3
As shown in FIG. 3, the conventional semiconductor memory device corresponds to the digit lines 205, 206, 207 and 208, and includes P channel MOS transistors 24 and 25 forming a current mirror circuit and a P channel MO transistor, respectively.
N channel MOS transistors 26 and 27 connected in series to S transistors 24 and 25, and N
A sense amplifier circuit formed by a complementary inverter 28 connected between the source and gate of the channel MOS transistor 26 and a memory cell selection signal 10 respectively.
N corresponding to 7, 108, 109, 110 and 111
Channel MOS transistors 29, 30, 31 and 3
3, 32 and 34, memo cells 35 to 38, and an output buffer 39. It should be noted that in FIG. 3, reference numerals 40, 41, 42 and 43 denote digit lines 205, 206 and 207, respectively.
And the parasitic capacitances of 208.

In FIG. 3, the output of the sense amplifier circuit formed by P channel MOS transistors 24 and 25, N channel MOS transistors 26 and 27, and inverter 28 is P channel MOS transistor 25 and N channel MOS transistor 27. It is taken out from the drain connection point E of and and outputted as an output signal 112 via the output buffer 39.

In the memory area, the digit line 20
Memory cells 35-38 are connected to each of 5-208 and N-channel M forming a second Y selector connected between each digit line and connection points C and D.
One digit line is selected by the OS transistors 31 to 34. Further, an N-channel MOS forming a first Y selector is provided between the connection points C and D and the connection point B.
Transistors 29 and 30 are connected, and parasitic capacitances 40 to 40 are respectively connected to the digit lines 205 to 208.
43 is interposed. Further, in FIG. 3, V _DD and V _EE indicate the power supply voltage and the reference voltage, respectively.

In the sense amplifier circuit shown in FIG. 3, the output level of the sense amplifier circuit (the level of the connection point E) is the mutual conductance g _m25 of the P channel MOS transistor 25 and the N channel MOS transistor 27.
_Is determined by the ratio of the transconductances g _m27 of That is, when g _m25 > g _m27 , the output level of the sense amplifier circuit becomes high level, and conversely, when g _m25 <g _m27 , the output level of the sense amplifier circuit becomes low level.

4 (a), (b), (c), (d),
(E), (f), and (g) are the conventional semiconductor memory device shown in FIG. 3, in which only the first Y selector is switched and the stored information of the two switched memory cells at the same time is shared. FIG. 9 is an operation waveform diagram in the case where a threshold voltage is kept high and a cell is always in an off state (hereinafter referred to as an off cell). As is clear from FIG. 4, the memory cell selection signals 110 and 111 are fixed to the high level,
Further, when the memory cell selection signal 109 is fixed to the low level, the memory cell selection signal 107 is switched from the low level to the high level, and the memory cell selection signal 108 is switched from the high level to the low level (only the first Y selector is (Corresponding to the case of switching), the memory cell selection is switched from the memory cell 38 to the memory cell 36, and the operation of each connection point is as shown in FIG. 4 (f). That is, the level of the connection point B is momentarily lowered to charge the parasitic capacitance 41 of the digit line 206,
After the charging of the parasitic capacitance 41 of the digit line 206 is completed, it returns to a stable level. The level of the connection point A also follows the level of the connection point B and decreases during the charging period of the parasitic capacitance 41 of the digit line 206. _Therefore , the value of the mutual conductance g _m25 of the P-channel MOS transistor 25 is reduced. Increased, and thus momentarily g _m25
> G _m27 , and the output of the sense amplifier circuit (level at the connection point E) temporarily rises from the low level. However, since the floating level is a level equal to or lower than V _DD / 2, the output buffer 39 in the next stage of the sense amplifier circuit is
The level of the output signal 112 (see FIG. 4 (g)) from
Although it temporarily rises, it does not reach the level at which it reverses.

Although not mentioned in the above description, in the case of switching only the second Y selector, the operation of each connection point is the same as in the case of switching only the first Y selector.

[0009]

In the above-described conventional semiconductor memory device, in the case where only the first Y selector or only the second Y selector is independently switched, the problem of the output level inversion occurs. Although it does not happen, when the first Y selector and the second Y selector are switched together, the first Y selector and the second Y selector are not actually switched at the same time, and there is some delay in switching one of the selectors. Therefore, due to the delay, when a digit line is switched, a digit line different from the digit line to be temporarily selected is selected.

5 (a), (b), (c), (d),
(E), (f) and (g) are waveform charts showing the operation when the first Y selector and the second Y selector are switched at the same time, and FIGS. ) And (d), depending on the simultaneous switching of both Y selectors,
When the memory cell selection signals 107 and 109 are switched from low level to high level and the memory cell selection signals 108 and 110 are switched from high level to low level, the memory cell selection signal 109 is delayed with respect to the memory cell selection signal 107. The output waveforms of the respective parts in the situation where the level transition occurs and the memory cell selection signal 110 delays with respect to the memory cell selection signal 108 and the level transitions are shown.

In FIG. 5, the memory cell selection signal 107
When the memory cell selection signals 109 and 110 are switched with a momentary delay after the switching of the memory cells 35 and 108, the target memory cell 38 to be selected is the memory cell 35.
Until the memory cell 36
Will be selected. Therefore, first, the memory cell 36
Is selected, the parasitic capacitance 4 of the digit line 206 is
1 is charged, and the level at the connection point B momentarily decreases toward the low level. Subsequently, whether or not the charging of the parasitic capacitance of the digit line 206 is completed or not, the parasitic capacitance 40 of the digit line 205 is further charged because the memory cell 35 is selected. The level will drop further. Then, after the charging of the parasitic capacitance of the digit line 205 is completed, the level at the connection point B returns to the original stable level. Even in this case, the connection point A
Changes in accordance with the level of the connection point B, and the parasitic capacitance 41 of the digit line 206 and the digit line 205.
During the charging period for the parasitic capacitance 40 of, the level is further reduced as compared with the case of switching only the first Y selector described above,
Therefore, the output of the sense amplifier circuit (the level at the connection point E) temporarily exceeds the level of V _DD / 2. Therefore, following the output level of the connection point E, the output signal 112 (see FIG. 5 (g)) is temporarily inverted,
False data called "whisker of output data" is generated.

That is, when the first Y selector and the second Y selector are switched together, a situation occurs in which a digit line different from the digit line to be temporarily selected is selected when the digit line is switched. As a result, There is a drawback that erroneous data is output.

[0013]

A semiconductor memory device of the present invention includes a current detection type sense amplifier circuit and detects an address change accompanying address switching in a semiconductor memory device formed of a non-volatile semiconductor memory. do it,
At least a means for outputting an address detection signal of a predetermined level and a sense amplifier output control means for receiving the address detection signal and controlling and adjusting the output level of the sense amplifier circuit are controlled.

The output level control adjusting operation by the sense amplifier output control means is performed by controlling and adjusting the mutual conductance ratio of two transistors connected in series to form the output stage of the sense amplifier circuit. In the output stage of the sense amplifier circuit, a source is connected to a power supply on the high potential side, a drain is connected to an output end, and a P-channel MOS transistor whose gate receives a predetermined input signal is provided. An N-channel MOS transistor having a drain connected to the output end, a source connected to a low-potential-side power supply, and a gate supplied with a predetermined reference potential, the sense amplifier output control means comprising: A first P-channel MOS transistor whose source is connected to the power source on the high potential side and whose gate receives the address detection signal. And a second P-channel MOS transistor having a source connected to the drain of the first P-channel MOS transistor, a drain connected to the output end, and a gate to which the predetermined input signal is input. It may be formed.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. As shown in FIG. 1, this embodiment corresponds to the digit lines 201, 202, 203 and 204.
Between P-channel MOS transistors 1 and 2 forming a current mirror circuit, N-channel MOS transistors 3 and 4 connected in series to P-channel MOS transistors 1 and 2, respectively, and between the source and gate of N-channel MOS transistor 3. Sense amplifier circuit formed by the complementary inverter 5 connected to the P-channel MOS transistors 16 and 17 for controlling the output level of the sense amplifier circuit by receiving the detection output of the address change, and memory cell selection respectively. Signal 10
N corresponding to 1, 102, 103, 104 and 105
Channel MOS transistors 6, 7, 8 and 10, 9
11 and 11, memory cells 12 to 15, an address change detection circuit 18, and an output buffer 19.

In FIG. 1, reference numerals 20, 21, 22 and 23 denote digit lines 2 respectively.
The parasitic capacitances of 01, 202, 203 and 204.

The output of the above sense amplifier circuit is taken out from the drain connection point E between the P-channel MOS transistor 2 and the N-channel MOS transistor 4, and is output as the output signal 106 via the output buffer 19. Further, the P-channel MOS transistor 17 is operated in parallel with the P-channel MOS transistor 2 when the P-channel MOS transistor 16 is on, and the output level of the sense amplifier circuit becomes higher. However, when the address change detection circuit 18 detects an address change and outputs a pulse signal rising in the positive direction, the P-channel MOS transistor 1
Since 6 is turned off, the output level of the sense amplifier circuit decreases.

In the memory area, memory cells 12 to 15 are connected to the digit lines 201 to 204, respectively, as in the case of the above-mentioned conventional example, and between each digit line and the connection points C and D. N-channel MOS transistors 8 to 1 forming a connected second Y selector
By 1, one digit line is selected. Further, N-channel MOS transistors 6 and 7 forming a first Y selector are connected between the connection points C and D and the connection point B, and the digit lines 201 to 204 have parasitic capacitances 20 to 20 respectively. 23 intervenes. The switching operation of the first Y selector and the second Y selector in this memory area is the same as in the case of the above-mentioned conventional example, and the description thereof will be omitted.

Further, FIGS. 2 (a), 2 (b), 2 (c),
(D), (e), (f), (g) and (h) are the first
The Y-selector and the second Y-selector are switched together, and the memory cell selection signals 101, 1 when the information of the memory cells switched at that time are both OFF cells
FIG. 10 is an operation waveform diagram showing 02, 103, 104 and 105 and the level state at each connection point. 2 (a),
As shown in (b), (c), (d), (e), (f), (g) and (h), the address change detection circuit 18
The output signal (level of the connection point F) is normally low level, but when the address changes, it is output as a high level signal for a predetermined time (see FIG. 2 (f)). Further, in the sense amplifier circuit of this embodiment, the P-channel MOS transistor 2 and the P-channel M
Sum of mutual conductance of OS transistor 17 g
The output level of the sense amplifier circuit (the level at the connection point E) is determined by the ratio of _{m2 · 17} and the mutual conductance g _m4 of the N-channel MOS transistor 4, but as described above, In connection with turning on / off, the P-channel MOS transistor 16 is turned off in the time zone when the output level of the address change detection circuit 18 (level of the connection point F) is high level,
The power supply voltage V _DD is not supplied to the P-channel MOS transistor 17. Therefore, the output of the sense amplifier circuit in this time zone is determined by the ratio of the mutual conductance g _m2 of the P channel MOS transistor 2 alone and the mutual conductance g _m4 of the N channel MOS transistor 4. Sum of mutual conductances of the P-channel MOS transistor 2 and the P-channel MOS transistor 17 described above.
There is a relation of gg _{m2 · 17} > g _m4 between g _{m2 · 17} and the mutual conductance g _m4 of the N-channel MOS transistor 4, and therefore the output level of the address change detection circuit 18 (the level at the connection point F). ) Is low level, the output level of the sense amplifier circuit (level of connection point E) is high level, but conversely, the output level of the address transition detection circuit 18 (level of connection point F) is high level. In the time zone of, the output level of the sense amplifier circuit (level of the connection point E) is low level.

In this case, as shown in FIG. 2 (g), the level does not exceed the potential of V _DD / 2. As a result, even if an erroneous memory cell is temporarily selected at the time of address switching, the output level of the sense amplifier circuit does not exceed V _DD / 2, and the level of the output signal 106 is inverted. The situation that occurs is avoided, and the output of erroneous data is suppressed.

As described above, according to the present invention, between the power supply and the output point of the sense amplifier circuit, the transistor which is set to the off state for a fixed time corresponding to the change of the address is provided to switch the address. Sometimes, by reducing the output level of the sense amplifier circuit, it is possible to suppress the output of erroneous data even when a memory cell is erroneously selected.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention.

FIG. 2 is an operation waveform diagram in the present embodiment.

FIG. 3 is a circuit diagram showing a conventional example.

FIG. 4 is an operation waveform diagram in a conventional example.

FIG. 5 is an operation waveform diagram in a conventional example.

[Explanation of symbols]

1, 2, 16, 17, 24, 25 P-channel MOS
Transistors 3, 4, 6-11, 26, 27, 29-34 N-channel MOS transistors 5, 28 Complementary inverters 12-15, 35-38 Memory cells 20-23, 40-43 Parasitic capacitance

Claims (3)

[Claims] 1. A current detection type sense amplifier circuit is provided,
In a semiconductor memory device formed by a non-volatile semiconductor memory, means for detecting an address change accompanying address switching and outputting an address detection signal of a predetermined level, and the sense amplifier circuit for receiving the address detection signal. And a sense amplifier output control means for controlling and adjusting so as to suppress the output level of the semiconductor memory device. 2. The output level control adjusting action by the sense amplifier output control means is performed by controlling and adjusting a mutual conductance ratio of two transistors connected in series to form an output stage of the sense amplifier circuit. The semiconductor memory device according to claim 1, wherein the semiconductor memory device comprises: 3. The output stage of the sense amplifier circuit has a source connected to a high-potential-side power supply, a drain connected to an output terminal, and a gate to which a predetermined input signal is input.
A channel MOS transistor, a drain of which is connected to the output terminal, a source of which is connected to a low-potential-side power supply, and a gate of which is supplied with a predetermined reference potential. A control means is a first P-channel MOS whose source is connected to the power supply on the high potential side and whose gate receives the address detection signal.
A transistor and a second P-channel transistor having a source connected to the drain of the first P-channel MOS transistor, a drain connected to the output terminal, and a gate to which the predetermined input signal is input.
3. The semiconductor memory device according to claim 1, which is formed by a channel MOS transistor.