JPH0555211A - Forming method of wiring - Google Patents
Forming method of wiringInfo
- Publication number
- JPH0555211A JPH0555211A JP21517891A JP21517891A JPH0555211A JP H0555211 A JPH0555211 A JP H0555211A JP 21517891 A JP21517891 A JP 21517891A JP 21517891 A JP21517891 A JP 21517891A JP H0555211 A JPH0555211 A JP H0555211A
- Authority
- JP
- Japan
- Prior art keywords
- glass substrate
- layer wiring
- resist pattern
- film
- wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 19
- 239000011521 glass Substances 0.000 claims abstract description 19
- 239000000758 substrate Substances 0.000 claims abstract description 19
- 238000000059 patterning Methods 0.000 claims abstract description 4
- 239000000463 material Substances 0.000 claims description 6
- 238000005530 etching Methods 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims description 2
- 239000011248 coating agent Substances 0.000 claims 1
- 238000000576 coating method Methods 0.000 claims 1
- 239000010408 film Substances 0.000 abstract description 21
- 239000010409 thin film Substances 0.000 abstract description 5
- 229910052782 aluminium Inorganic materials 0.000 abstract description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 2
- 230000015572 biosynthetic process Effects 0.000 abstract 2
- 238000004519 manufacturing process Methods 0.000 abstract 1
- 238000001039 wet etching Methods 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 16
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 230000003071 parasitic effect Effects 0.000 description 2
- RZVAJINKPMORJF-UHFFFAOYSA-N Acetaminophen Chemical compound CC(=O)NC1=CC=C(O)C=C1 RZVAJINKPMORJF-UHFFFAOYSA-N 0.000 description 1
- 238000004380 ashing Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 239000003960 organic solvent Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 239000005297 pyrex Substances 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
Landscapes
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Thin Film Transistor (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は配線形成方法に係り、特
に詳細には、ガラス基板上に多層配線する方法に関す
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring forming method, and more particularly, to a method for forming a multi-layer wiring on a glass substrate.
【0002】[0002]
【従来の技術】従来、このような分野の技術として、例
えば特開昭59−124123号、同61−94366
号に示されるものがある。これらは、ガラス基板の一部
に凹部を設け、ここに薄膜トランジスタ(TFT)の要
素(例えばソース電極やドレイン電極)を埋め込むもの
である。しかし、ガラス基板における多層配線について
は、従来から特に工夫されておらず、様々な問題が生じ
ていた。2. Description of the Related Art Conventionally, as a technique in such a field, for example, JP-A-59-124123 and JP-A-61-94366.
There is something shown in the issue. In these, a recess is provided in a part of a glass substrate, and elements of thin film transistors (TFTs) (for example, a source electrode and a drain electrode) are embedded therein. However, the multilayer wiring on the glass substrate has not been devised in the past, and various problems have occurred.
【0003】[0003]
【発明が解決しようとする課題】すなわち、ガラス基板
上に大面積薄膜電子デバイスを作製すると、配線には多
くの交差部が生じる。このため、寄生容量が増大したり
S/N比が劣化したり、あるいは段差によるリーク電流
やショート、断線が生じ易い。この問題点を克服するた
めに、前述の公報の技術を応用すると、プロセスが複雑
化し、大面積かつ低コストの薄膜デバイスに適さない。That is, when a large-area thin film electronic device is manufactured on a glass substrate, many intersections are formed in the wiring. Therefore, the parasitic capacitance is increased, the S / N ratio is deteriorated, or leak current, short circuit, or disconnection due to a step is likely to occur. If the technique of the above-mentioned publication is applied to overcome this problem, the process becomes complicated and it is not suitable for a large area and low cost thin film device.
【0004】[0004]
【課題を解決するための手段】本発明は、上述の課題を
解決するためになされたもので、ガラス基板にマスク材
をコーティングし、パターンニングによって選択的にガ
ラス基板を露出させる第1の工程と、エッチングにより
露出したガラス基板に凹溝を形成する第2の工程と、配
線材料を堆積し、マスク材を除去することにより、第1
層配線を形成する第3の工程と、全面に絶縁膜を形成す
る第4の工程と、所定パターンの第2層配線を絶縁膜上
に形成する第5の工程とを備えることを特徴とする。SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems. The first step is to coat a glass substrate with a mask material and selectively expose the glass substrate by patterning. And a second step of forming a groove on the glass substrate exposed by etching, and a first step by depositing a wiring material and removing the mask material.
It is characterized by comprising a third step of forming a layer wiring, a fourth step of forming an insulating film on the entire surface, and a fifth step of forming a second layer wiring of a predetermined pattern on the insulating film. ..
【0005】[0005]
【作用】本発明によれば、同一のマスクを介してガラス
基板における凹溝の形成と第1層配線の形成を行なうこ
とができ、また平坦化できる。According to the present invention, it is possible to form the concave groove and the first layer wiring in the glass substrate through the same mask, and it is possible to flatten the surface.
【0006】[0006]
【実施例】以下、添付図面により、本発明の一実施例を
説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the accompanying drawings.
【0007】図1および図2は実施例のプロセスを説明
するための、工程別の素子断面図である。FIG. 1 and FIG. 2 are cross-sectional views of the element for each step for explaining the process of the embodiment.
【0008】まず、パイレックス、石英などのガラス基
板1を用意し、フォトレジスト膜20を全面にスピンコ
ート法で形成する。なお、フォトレジスト膜20の代り
に、感光性ポリイミド膜を用いてもよい(図1(a)参
照)。First, a glass substrate 1 such as Pyrex or quartz is prepared, and a photoresist film 20 is formed on the entire surface by spin coating. A photosensitive polyimide film may be used instead of the photoresist film 20 (see FIG. 1A).
【0009】次に、フォトリソグラフィ技術によりフォ
トレジスト膜20の露光、現像を行い、第1層配線の形
成部でガラス基板1を露出させる。このとき、フォトレ
ジスト膜20をパターンニングしたレジストパターン2
1のエッヂは、なるべくシャープになるようにする(図
1(b)参照)。Next, the photoresist film 20 is exposed and developed by the photolithography technique to expose the glass substrate 1 at the first layer wiring forming portion. At this time, the resist pattern 2 formed by patterning the photoresist film 20
Edge 1 should be as sharp as possible (see FIG. 1 (b)).
【0010】次に、レジストパターン21をマスクとし
て、ウェットエッチング法などで露出部のガラス基板1
を除去する。エッチングの深さは、レジストパターン2
1の厚さd1 =2.0μmの1/10程度が望ましく
(2000オングストローム程度)、これによって、僅
かにサイドエッチングされた凹溝3が形成される。(図
1(c)参照)。Next, using the resist pattern 21 as a mask, the exposed portion of the glass substrate 1 is wet-etched or the like.
To remove. The etching depth is the resist pattern 2
It is desirable that the thickness d 1 of 1 is about 1/10 of the thickness d 1 = 2.0 μm (about 2000 Å), whereby the slightly side-etched concave groove 3 is formed. (See FIG. 1 (c)).
【0011】次に、全面にアルミニウムなどの金属膜3
0を堆積する。この厚さは、凹溝3の深さ(2000オ
ングストローム)と同程度にするのが望ましい。このと
き、レジストパターン21のエッヂはシャープになって
おり、凹溝3は僅かにサイドエッチングされているの
で、段差で金属膜30は完全に切れる(図2(a)参
照)。しかる後、レジストパターン21を有機溶剤やア
ッシングにより除去すると、リフトオフ法により凹溝3
の金属膜30が第1層配線31として残される。Next, a metal film 3 of aluminum or the like is formed on the entire surface.
0 is deposited. It is desirable that this thickness be approximately the same as the depth of the concave groove 3 (2000 angstrom). At this time, the edge of the resist pattern 21 is sharp and the groove 3 is slightly side-etched, so that the metal film 30 is completely cut at the step (see FIG. 2A). After that, when the resist pattern 21 is removed by an organic solvent or ashing, the concave groove 3 is formed by the lift-off method.
The metal film 30 is left as the first layer wiring 31.
【0012】次に、全面に絶縁膜4を形成する(図2
(b)参照)。この絶縁膜4は、誘電率の小さいSiO
2 やSi3 N4 が好ましい。また、厚さは4000オン
グストローム以下でよい。次に、絶縁膜4上に第2層配
線5を形成する。その厚さは4000オングストローム
程度である。この第2層配線5は、例えばリフトオフ法
で形成できる(図2(c)参照)。Next, the insulating film 4 is formed on the entire surface (FIG. 2).
(See (b)). The insulating film 4 is made of SiO having a small dielectric constant.
2 and Si 3 N 4 are preferred. The thickness may be 4000 angstroms or less. Next, the second layer wiring 5 is formed on the insulating film 4. Its thickness is about 4000 angstroms. The second layer wiring 5 can be formed by, for example, a lift-off method (see FIG. 2C).
【0013】図3は、上記のプロセスで作製したデバイ
スの、一部を断面で示した斜視図である。図示の通り、
層間絶縁膜4の表面は平坦化され、したがって交差部で
の段差がほとんど無くすることができる。このため、第
1層配線31と第2層配線5の間のショートやリーク電
流を防止でき、また第2層配線5の断線も防止できる。
また、第1層配線31と第2層配線5の間の寄生容量も
低減できる。FIG. 3 is a perspective view showing a part of the device manufactured by the above process in cross section. As shown,
The surface of the interlayer insulating film 4 is flattened, so that the step at the intersection can be almost eliminated. Therefore, it is possible to prevent a short circuit and a leak current between the first layer wiring 31 and the second layer wiring 5, and it is also possible to prevent disconnection of the second layer wiring 5.
Also, the parasitic capacitance between the first layer wiring 31 and the second layer wiring 5 can be reduced.
【0014】[0014]
【発明の効果】以上、詳細に説明した通り、本発明の配
線形成方法によれば、同一のマスクを介してガラス基板
における凹溝の形成と第1層配線の形成を行なうことが
でき、また平坦化できる。このため、特性が良好な大面
積薄膜デバイスを、簡単なプロセスによって低コストで
提供できる効果がある。As described above in detail, according to the wiring forming method of the present invention, it is possible to form the concave groove and the first layer wiring in the glass substrate through the same mask. Can be flattened. Therefore, there is an effect that a large area thin film device having excellent characteristics can be provided at low cost by a simple process.
【図1】実施例のプロセス前半を示す断面図である。FIG. 1 is a cross-sectional view showing the first half of the process of an example.
【図2】実施例のプロセス後半を示す断面図である。FIG. 2 is a cross-sectional view showing the latter half of the process of the example.
【図3】実施例で作製されたデバイスの斜視図である。FIG. 3 is a perspective view of a device manufactured in an example.
【符号の説明】 1…ガラス基板 20…フォトレジスト膜 21…レジストパターン 3…凹溝 30…金属膜 31…第1層配線 4…絶縁膜 5…第2層配線[Explanation of Codes] 1 ... Glass substrate 20 ... Photoresist film 21 ... Resist pattern 3 ... Recessed groove 30 ... Metal film 31 ... First layer wiring 4 ... Insulating film 5 ... Second layer wiring
フロントページの続き (51)Int.Cl.5 識別記号 庁内整理番号 FI 技術表示箇所 H01L 29/784 9056−4M H01L 29/78 311 A Continuation of the front page (51) Int.Cl. 5 Identification code Office reference number FI Technical display location H01L 29/784 9056-4M H01L 29/78 311 A
Claims (2)
し、パターンニングによって選択的に前記ガラス基板を
露出させる第1の工程と、 エッチングにより前記露出したガラス基板に凹溝を形成
する第2の工程と、 配線材料を堆積し、前記マスク材を除去することによ
り、第1層配線を形成する第3の工程と、 全面に絶縁膜を形成する第4の工程と、 所定パターンの第2層配線を前記絶縁膜上に形成する第
5の工程とを備えることを特徴とする配線形成方法。1. A first step of coating a glass substrate with a mask material to selectively expose the glass substrate by patterning, and a second step of forming a concave groove in the exposed glass substrate by etching. A third step of forming a first layer wiring by depositing a wiring material and removing the mask material; a fourth step of forming an insulating film on the entire surface; and a second layer wiring having a predetermined pattern. A fifth step of forming on the insulating film, the wiring forming method.
を略同程度とした請求項1記載の配線形成方法。2. The wiring forming method according to claim 1, wherein the depth of the groove and the thickness of the first layer wiring are substantially the same.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21517891A JPH0555211A (en) | 1991-08-27 | 1991-08-27 | Forming method of wiring |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21517891A JPH0555211A (en) | 1991-08-27 | 1991-08-27 | Forming method of wiring |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0555211A true JPH0555211A (en) | 1993-03-05 |
Family
ID=16667965
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP21517891A Pending JPH0555211A (en) | 1991-08-27 | 1991-08-27 | Forming method of wiring |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0555211A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH09307080A (en) * | 1996-05-02 | 1997-11-28 | Lg Semicon Co Ltd | Semiconductor device capacitor manufacturing method |
| CN102153046A (en) * | 2010-12-22 | 2011-08-17 | 中国科学院光电技术研究所 | Method for preparing semi-cylindrical micro-groove by combining two-time film deposition and dry-wet method |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5878454A (en) * | 1981-10-08 | 1983-05-12 | Nec Corp | Manufacture of semiconductor device |
| JPH01170048A (en) * | 1987-12-25 | 1989-07-05 | Casio Comput Co Ltd | Manufacturing method of thin film transistor |
-
1991
- 1991-08-27 JP JP21517891A patent/JPH0555211A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5878454A (en) * | 1981-10-08 | 1983-05-12 | Nec Corp | Manufacture of semiconductor device |
| JPH01170048A (en) * | 1987-12-25 | 1989-07-05 | Casio Comput Co Ltd | Manufacturing method of thin film transistor |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH09307080A (en) * | 1996-05-02 | 1997-11-28 | Lg Semicon Co Ltd | Semiconductor device capacitor manufacturing method |
| CN102153046A (en) * | 2010-12-22 | 2011-08-17 | 中国科学院光电技术研究所 | Method for preparing semi-cylindrical micro-groove by combining two-time film deposition and dry-wet method |
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