JPH0555480A - SOI type BiCMOS gate array - Google Patents

Abstract

(57) [Abstract] [Purpose] To increase the degree of integration of a BiCMOS gate array as much as a CMOS gate array. A BiCMOS gate array is formed on an SOI layer 2, and a lateral bipolar transistor that determines the width of a base 6 in a self-aligned manner by using a sidewall 3 in an LDD type MOS structure portion is formed by the base 6 S.
The wiring layer 9 is formed so as to be exposed on the bottom surface of the OI layer 2 and buried under the SOI layer 2 to take out the electrode of the base. [Effect] The electrode of the base can be taken out without increasing the occupied area of each cell.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to an SOI type BiCMOS.
SOI type Bi that does not require a large occupied area of each gate cell for taking out a gate array, especially a base electrode
It relates to a CMOS gate array.

[0002]

2. Description of the Related Art A gate array can be classified into a CMOS gate array, a bipolar gate array, and a BiCMOS gate array depending on the type of transistors to be formed. In the BiCMOS gate array, each gate is composed of a CMOS and a bipolar transistor.

Since the BiCMOS gate array can be highly integrated as compared with the bipolar gate array and has a higher speed than the CMOS gate array, it is expected that it will be widely used in the future.

In particular, the BiCMOS gate array is shown in FIG.
As shown in (1), an npn transistor and a resistor R are connected to the output stage of the CMOS to form an emic follower, which is attracting attention because the speed can be increased without significantly lowering the degree of integration.

[0005]

However, in the conventional BiCMOS gate array, it is necessary to add a bipolar transistor, a bipolar transistor and a resistor connected to the base to the CMOS, and it is necessary to take out the base electrode and form the resistor. Therefore, it is very difficult to obtain the degree of integration equivalent to that of the CMOS gate array because the occupied area must be divided.

The present invention has been made to solve such a problem, and an object thereof is to increase the integration degree of a BiCMOS gate array.

[0007]

Means for Solving the Problems The present invention SOI type BiCM
The OS gate array comprises a MOS transistor and a bipolar transistor in the SOI layer, and
It is characterized in that the base of the bipolar transistor is exposed on the bottom surface of the SOI layer, and the electrode of the base is taken out by a wiring layer buried under the SOI layer.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The SOI type BiCMOS gate array of the present invention will be described in detail below with reference to the illustrated embodiments. FIGS. 1 and 2A to 2D show one embodiment of the SOI type BiCMOS gate array of the present invention. FIG. 1 is a plan view of a basic cell, and FIG. 2A is A- of FIG. A sectional view taken along line A, FIG.
1B is a sectional view taken along line BB of FIG. 1, FIG. 2C is a sectional view taken along line CC of FIG. 1, and FIG. 2D is a sectional view taken along line DD of FIG. ..

In the drawings, 1a and 1b are the gate electrodes of a pair of p-channel MOS transistors of a basic cell, and 1
c and 1d are gate electrodes of a pair of n-channel MOS transistors of the basic cell, 2a and 2b are SOI layers, 2a is a pair of p-channel MOS transistors and bipolar transistors, and 2b is a pair of n-channel MOS transistors. Are formed.

Each MOS transistor has an LDD structure, and 3, 3, ... Are sidewalls formed on the side surfaces of the gate electrode of each MOS transistor. Reference numeral 4 denotes a bipolar transistor formation region formed at the end of the SOI layer 2a on the SOI layer 2b side, and an npn bipolar transistor is formed in the region 4. The sectional shape of this bipolar transistor is shown in FIG.

The npn bipolar transistor is M
It is formed laterally by utilizing the OS structure and further utilizing the sidewall for self-alignment formation of the base width. Reference numeral 5 is an n ⁺ -type emitter of the bipolar transistor, 6 is a p ⁺ -type base, the surface of which is located under the side wall 3, which extends under the emitter 5 and is exposed at the bottom surface of the SOI layer 2a.

Reference numeral 7 is an n ⁺ type common emitter of the bipolar transistor. The bipolar transistor 7 has a structure shared by two bipolar transistors, but one bipolar transistor (the left bipolar transistor in FIGS. 1 and 2B) is not used in this embodiment. The base electrode is not taken out and it is famous and innocent.

An insulating film 8 made of SiO ₂ surrounds and supports the SOI layers 2a and 2b, and a wiring layer 9 made of polycrystalline silicon buried under the SOI layers 2a and 2b serves as a base of the bipolar transistor. , And the collector of one n-channel MOS transistor is connected [Fig. 1
2B to 2D]. As will be described later, reference numerals 12 and 12 are contact holes for connecting the wiring layer 9 and the SOI layers 2a and 2a. The wiring layer 9 not only plays the role of taking out the base electrode of the bipolar transistor and connecting it to the n-channel MOS transistor,
Due to its own resistance, it also functions as the resistance R shown in FIG. Incidentally, the resistor R is used to prevent the amplitude of the output signal of the circuit is reduced by that V _BE by the base-emitter voltage V _BE of the bipolar transistor.

According to such an SOI type BiCMOS gate array, the bipolar transistor has a lateral structure in which the base 6 is formed in its width by the sidewall 3 in a self-aligned manner, and it extends below the emitter 5 and the SOI layer. The wiring layer 9 exposed on the lower surface of 2a and taking out the base electrode is embedded in the lower side of the SOI layer 2a. Therefore, the base electrode can be taken out without increasing the occupied area of the basic cell.

Moreover, since the wiring layer 9 has its own resistance, it also functions as the resistance R, so that the area occupied by the basic cell is not increased by the resistance R. Therefore, BiC
The area occupied by the MOS gate array can be reduced to the same extent as the CMOS gate array. Since this gate array is of the SOI type, it is needless to say that it has a high resistance to the narrow channel effect and a high resistance to soft errors.

Of course, the bipolar transistor and the wiring layer 9 are incorporated in the gate array, and the connection between the bipolar transistor and the wiring layer 9 and the connection between the bipolar transistor and the wiring layer 9 and other circuit elements have already been performed. Therefore, it is not necessary to electrically connect these with aluminum wiring, and the reliability and layout efficiency are excellent. The two-dot chain line in FIG. 1 shows the wiring required to make the circuit shown in FIG.

3A to 3F are SOI type BiCMs.
FIG. 9 is a cross-sectional view showing a manufacturing process in the order of steps until the SOI layer is formed in manufacturing the OS gate array. (A) As shown in FIG. 3A, the trench 11 is formed in the surface portion of the semiconductor substrate 10. This trench 11 will be later S
It becomes a part that partitions the OI layer 2 into islands. (B) Next, the surface of the semiconductor substrate 10 is formed by CVD as shown in FIG.
The insulating film 8 is formed as shown in FIG.

(C) Next, contact holes 12 and 12 are formed in the insulating film 8, and then a wiring layer 9 is formed by CVD. FIG. 3C shows a state after the wiring layer 9 is formed.
The contact holes 12 and 12 are for connecting both ends of the wiring layer 9 to the base 6 of the bipolar transistor and the drain of the n-channel MOS transistor. (D) Next, as shown in FIG. 3D, the wiring layer 9 is patterned.

(E) Next, the insulating film 8 is formed on the surface by CVD.
Is formed, and then a polycrystalline silicon layer 13 is formed on the surface thereof, and then the surface of the polycrystalline silicon 13 is polished to form a flat wafer bonding surface 14. FIG. 3E shows a state after the wafer bonding surface 14 is formed. (F) Then, another semiconductor substrate 15 is bonded to the wafer bonding surface 14, and then the semiconductor substrate 10 is polished from the back surface side. This polishing is performed by using the insulating film 8 as a stopper, and by this polishing, the SOI layer 2 having the polished surface as a surface
a and 2b are formed.

4A to 4E are sectional views showing a method of forming a bipolar transistor and a p-channel MOS transistor in the order of steps. (A) Gate electrodes 1a, 1b, 1a, 1b are formed on the surface of the SOI layer 2a (and 2b) via a gate insulating film, and then, as shown in FIG. The portion to be formed is masked by the resist film 16, and p ⁻ type impurities are ion-implanted in this state. This is a process for forming a lightly doped drain of a MOS transistor.

(B) Next, as shown in FIG. 4B, the collector film portion of the bipolar transistor and the MOS transistor portion are masked with the resist film 16, and p-type impurities are ion-implanted in this state. This is done to form the p ⁺ type base 6 of the bipolar transistor. (C) Next, sidewalls are formed on the side surfaces of the gate electrodes 1a and 1b, and then the bipolar transistor portion is masked with a resist film 16 as shown in FIG.
Ion implantation of p-type impurities into the p-channel MOS transistor portion forms p ⁺ -type source and drain regions.

(D) Next, as shown in FIG. 4D, the n ⁺ -type emitters 5 and 5 are formed by ion-implanting n-type impurities with the resist film 16 masking the portions other than the lateral bipolar transistor. And an n ⁺ -type common collector is formed. The width of the base 6 of the bipolar transistor is determined by the width of the sidewall 3 in a self-aligned manner.

The bottom surfaces of the emitters 5 and 5 are SOI.
It is formed shallower than the thickness of the SOI layer 2a so as not to reach the bottom surface of the layer 2a. Therefore, the base 6 has a structure exposed on the bottom surface of the SOI layer 2a. The order of steps (C) and (D) may be reversed. (E) After that, when activation annealing is performed, a bipolar transistor and p-channel MO as shown in FIG.
S-transistor is completed.

5A and 5B are SOI type Bi shown in FIG.
It is a top view which shows each another modified example of a CMOS gate array. The SOI type BiCMOS gate array of FIG. 5A is one in which only one bipolar transistor is formed in one basic cell. That is, in the above embodiment, only the wiring layer for one bipolar transistor of the pair of bipolar transistors formed in one basic cell is formed, and the wiring layer for the other bipolar transistor is not formed, and the base electrode is eventually formed. Has not been taken out. So in this case,
It can be said that the other bipolar transistor does not have to be formed. Therefore, in the modified example shown in FIG. 5A, the other bipolar transistor is not provided.

In the SOI type BiCMOS gate array of FIG. 5B, wiring layers 9 and 9 are formed for two bipolar transistors formed in one basic cell, respectively. In this case, one basic cell can be used to configure two inverters each having a bipolar transistor radiator in the output section. Therefore, it can be said that the usage is wide.

[0026]

According to the SOI type BiCMOS gate array of the present invention, a MOS transistor having an LDD structure is formed in the SOI layer.
SOI type B formed by forming a bipolar transistor having a base from under the side wall to the bottom surface of the SOI layer
An iCMOS gate array, below the SOI layer,
It is characterized in that a wiring layer forming a base extraction electrode connected to the base of the bipolar transistor is embedded. Therefore, the present invention SOI type BiCM
According to the OS gate array, since the base electrode of the bipolar transistor is taken out by the wiring layer buried under the SOI layer, the base electrode can be taken out without increasing the occupied area of the basic cell. ..

[Brief description of drawings]

FIG. 1 is a plan view of a basic cell showing one embodiment of an SOI type BiCMOS gate array of the present invention.

2A is a sectional view taken along line AA of FIG. 1, FIG. 2B is a sectional view taken along line BB of FIG. 1, and FIG. 2C is a sectional view taken along line CC of FIG. D) is a sectional view taken along the line D-D of FIG. 1.

3A to 3F are SOI type B shown in FIGS.
FIG. 7 is a cross-sectional view showing a sequence of manufacturing steps up to forming an SOI layer of an iCMOS gate array.

4A to 4E are SOI type BiCs shown in FIG.
FIG. 6 is a cross-sectional view showing a method of forming a bipolar transistor and a p-channel MOS transistor of a MOS gate array in the order of steps.

5A and 5B are SOI type Bi shown in FIGS.
It is a top view which shows each another modified example of a CMOS gate array.

FIG. 6 is a circuit diagram showing a typical example of a circuit formed by basic cells of a basic gate array.

[Explanation of symbols]

 2a, 2b SOI layer 5 Emitter of bipolar transistor 6 Base of bipolar transistor 7 Collector of bipolar transistor 9 Wiring layer

Claims (1)

[Claims] 1. An S-type MOS transistor having an LDD structure formed in an SOI layer and a bipolar transistor having a base extending from under a sidewall to a bottom surface of the SOI layer.
An SOI type BiCMOS gate array in which a wiring layer forming a base extraction electrode connected to the base of the bipolar transistor is embedded under the SOI layer.