JPH0555902A - Output buffer circuit - Google Patents

Abstract

(57) [Abstract] [Purpose] For an output buffer circuit of an integrated circuit, to realize a circuit that accelerates the fall of an output signal. [Structure] A differential amplifier composed of NPN transistor pairs 7 and 8, an emitter follower type composed of a transistor 10 and a resistor 15, and transistors 11 and 1
It is configured by combining each of the current mirror circuits configured by 3 and 14. [Effect] The output of the differential amplifier is output via the emitter follower, and the current mirror circuit that uses the inverted output signal as a control signal is connected in parallel to the resistance of the emitter follower. Impedance is reduced and the fall time becomes faster.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention relates to an output buffer circuit of an integrated circuit.

[0002]

2. Description of the Related Art As a conventional output buffer circuit, a circuit as shown in FIG. 2 or 3 has been known.

First, the circuit of FIG. 2 will be described.

The circuit shown in FIG. 2 includes a transistor 7,
It has a differential amplifier composed of 8, resistors 5, 6 and a current source 9, and an emitter follower circuit composed of a transistor 10 and a resistor 15.

Next, the operation of the circuit shown in FIG. 2 will be described. An input signal a is input from an input terminal 1 and an inverted input signal b is input from an input terminal 2, and an amplified signal c amplified by a differential amplifier is obtained. can get. The amplified signal c is used as the input signal of the emitter follower, and the output signal is output from the output terminal 3. The emitter follower functions to reduce the output impedance.

Next, the circuit shown in FIG. 3 will be described.

The circuit shown in FIG. 3 includes a transistor 7,
8, a differential amplifier composed of resistors 5 and 6 and a current source 9, and a push-pull type output stage composed of transistors 10, 11, 13 and 14 and a resistor 12. Next, to explain the operation of the circuit shown in FIG. 3, when the input signals a and b are input in balance from the two input terminals 1 and 2 of the differential amplifier, the amplified signal c and the inverted signal are obtained. d is obtained and applied to the bases of the NPN type transistors 10 and 11, respectively.
Here, when the input signal a rises, the inverted input signal b falls, so that the amplified signal c rises and the inverted amplified signal d falls. Therefore, the collector current of the transistor 11 decreases, and the collector current of the transistor 14 also decreases due to the current mirror effect of the current mirror circuit formed by the transistors 13 and 14. On the other hand, since the amplified signal c is applied to the base of the transistor 10, the potential of the output terminal 3 rises.

On the contrary, when the input signal a falls, the inverted input signal b rises, so that the amplified signal c falls and the inverted amplified signal d rises. Because of this, the collector current of the transistor 11 increases and the transistor 1
The collector current of the transistor 14 also increases due to the current mirror effect of the current mirror circuit composed of 3 and 14. On the other hand, since the amplified signal c is applied to the base of the transistor 10, the potential of the output terminal 3 drops.

[0009]

In the conventional output buffer circuit as shown in FIG. 2, when the output signal rises, the impedance with respect to the rise of the output signal is determined by the "on" resistance of the transistor 10 in the output stage. When is falling, the resistor 15 in the output stage
It depends on the time constant that depends on the value of.

Here, the "on" resistance of the transistor is generally several Ω to several tens Ω, and the resistance value of the resistor 15 in the output stage is set to several hundred Ω to several KΩ, so that the impedance with respect to the fall is It can be seen that is much larger than the impedance for rising. For this,
In the case of the circuit of FIG. 2, there is a drawback in that the fall of the output signal is significantly delayed with respect to the rise.

Further, in order to improve this point, the value of the resistor 15 in the output stage must be set to a sufficiently small value. By doing so, the fall of the output waveform becomes faster, but On the other hand, a very large amount of current flows through the resistor 15
However, there is a drawback that the efficiency becomes poor.

In the circuit shown in FIG. 3, the impedance seen from the collector of the output-stage transistor 14 is still several hundred Ω to several kΩ, and the fall of the output signal is delayed similarly to the circuit of FIG. However, there is a drawback that the efficiency becomes poor.

The present invention has been made in view of the above-mentioned conventional circumstances, and therefore, an object of the present invention is to provide a novel output buffer circuit capable of solving the above-mentioned drawbacks inherent in the prior art. To do.

[0014]

In order to achieve the above object, an output buffer circuit according to the present invention comprises a differential amplifier composed of a transistor pair, and a base electrode serving as an output electrode of the differential amplifier and a collector electrode. A first transistor connected to the first voltage source, and a second transistor whose base electrode is connected to the inverting output electrode of the differential amplifier and whose collector electrode is connected to the first voltage source, respectively. A third transistor in which the base electrode and the collector electrode are common and the emitter electrode is grounded; and a base electrode is common to the base electrode of the third transistor and a collector electrode is the first
A fourth transistor connected to the emitter electrode of the second transistor and having the emitter electrode grounded, and a first resistor connected between the emitter electrode of the second transistor and the collector electrode of the third transistor And a second resistor connected between the collector electrode and the emitter electrode of the fourth transistor.

[0015]

BEST MODE FOR CARRYING OUT THE INVENTION The present invention will now be described in detail with reference to the accompanying drawings with reference to the accompanying drawings.

FIG. 1 is a circuit configuration diagram showing an embodiment of the present invention.

Referring to FIG. 1, one embodiment of the present invention is
A differential amplifier composed of NPN transistors 7, 8 and resistors 5, 6 and a current source 9, and an NPN transistor 1
It is provided with 0, 11, 13, 14 and an output stage composed of resistors 12, 15. This output stage receives the positive and negative outputs of the differential amplifier as input, and outputs an output signal from the output terminal 3. Reference numerals 1 and 2 are input terminals to which an input signal and its inverted signal are applied, respectively.

Next, the operation of the embodiment of the present invention shown in FIG. 1 will be described.

The input signals a and b are balanced-input from the two input terminals 1 and 2 of the differential amplifier, and a signal c and an inverted signal d obtained by amplifying them are output from the differential amplifier to output the NPN transistors 10 and 11. Each is applied to the base. Here, when the input signal a rises, the inverted input signal b falls, so that the amplified signal c rises and the inverted amplified signal d falls. To this end, the transistor 1
The collector current of 1 decreases, and the collector current of the transistor 14 also decreases due to the current mirror effect of the current mirror circuit composed of the transistors 13 and 14.

On the other hand, the amplified signal c is applied to the base of the transistor 10, and the potential of the output terminal 3 rises. On the contrary, when the input signal a falls, the inverted input signal b
Rises, so the amplified signal c falls and the inverted amplified signal d rises. To this end, the transistor 1
The collector current of 1 increases, and the collector current of the transistor 14 also increases due to the current mirror effect of the current mirror circuit composed of the transistors 13 and 14. Further, since the amplified signal c is applied to the base of the transistor 10, the potential of the output terminal 3 drops.

Now, the operation when the output waveform falls will be compared with the circuits of FIGS.

First, in comparison with the circuit of FIG. 2, in the circuit of FIG. 1, a current source is connected in parallel to a resistor of the output stage, and this current source supplies the current of the output stage only when the output signal is at a low level. Since it is increased, the fall of the output signal becomes faster.

On the other hand, comparing with the circuit of FIG. 3, the impedance seen from the collector of the output stage transistor 14 is several hundred Ω to several KΩ, and the impedance seen from the output terminal to the ground can be obtained by connecting the resistor 15 in parallel. Becomes smaller. Therefore, the fall of the output signal is improved so as to be faster.

In the embodiment of the present invention described above, the NPN type is used as the transistor,
It goes without saying that the present invention can be easily implemented by substituting a PNP transistor instead.

[0025]

As described above, according to the present invention,
By outputting the output of the differential amplifier through the output stage that is a combination of the emitter follower circuit and the current mirror circuit, it is possible to output a waveform having a fast falling edge.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram showing an embodiment of the present invention.

FIG. 2 is a circuit diagram showing an example of a conventional technique.

FIG. 3 is a circuit diagram showing another example of the conventional technique.

[Explanation of symbols]

 1, 2 ... Input terminal 3 ... Output terminal 4 ... DC voltage source 5, 6 ... Resistor 7, 8 ... NPN type transistor 9 ... Current source 10, 11 ... NPN type transistor 12 ... Resistor 13, 14 ... NPN transistor 15 …Resistor

Claims (1)

[Claims] 1. A differential amplifier circuit comprising a pair of transistors, a first electrode having a base electrode connected to a non-inverted output electrode of the differential amplifier circuit and a collector electrode connected to a first voltage source. A transistor and a second transistor whose base electrode is connected to the inverting output electrode of the differential amplifier circuit and whose collector electrode is connected to the first voltage source;
A third transistor in which the base electrode and the collector electrode are common and the emitter electrode is grounded; and the base electrode is commonly connected to the base electrode of the third transistor and the collector electrode is connected to the emitter electrode of the first transistor. A first transistor connected in series between the emitter electrode of the second transistor and the collector electrode of the third transistor, and the fourth transistor A second resistor connected between the collector electrode and the emitter electrode of the first transistor, and inputting signals from the two input terminals of the differential amplifier circuit, the emitter electrode of the first NPN transistor. An output buffer circuit characterized in that a signal output is obtained from the output buffer circuit.