JPH0557916B2 - - Google Patents
Info
- Publication number
- JPH0557916B2 JPH0557916B2 JP60192217A JP19221785A JPH0557916B2 JP H0557916 B2 JPH0557916 B2 JP H0557916B2 JP 60192217 A JP60192217 A JP 60192217A JP 19221785 A JP19221785 A JP 19221785A JP H0557916 B2 JPH0557916 B2 JP H0557916B2
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- voltage
- power supply
- state
- logic
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B41—PRINTING; LINING MACHINES; TYPEWRITERS; STAMPS
- B41J—TYPEWRITERS; SELECTIVE PRINTING MECHANISMS, i.e. MECHANISMS PRINTING OTHERWISE THAN FROM A FORME; CORRECTION OF TYPOGRAPHICAL ERRORS
- B41J29/00—Details of, or accessories for, typewriters or selective printing mechanisms not otherwise provided for
- B41J29/38—Drives, motors, controls or automatic cut-off devices for the entire printing mechanism
- B41J29/387—Automatic cut-off devices
Landscapes
- Accessory Devices And Overall Control Thereof (AREA)
- Electronic Switches (AREA)
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、サーマルヘツド駆動装置に関し、
特に、ロジツク電源に異常が生じた場合に、ロジ
ツク回路の誤動作によるサーマルヘツドの発熱抵
抗体の損傷等を防止する保護回路を備えた駆動装
置に関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a thermal head drive device.
In particular, the present invention relates to a drive device equipped with a protection circuit that prevents damage to the heating resistor of the thermal head due to malfunction of the logic circuit when an abnormality occurs in the logic power supply.
第３図は従来のサーマルヘツド駆動装置の回路
図で、１はサーマルヘツド、２は発熱抵抗体、３
はＮチヤンネルMOS FETで構成されているス
イツチ、４はAND回路で、３，４でドライブ回
路５を構成し、ラツチ回路６から入力される１ラ
イン分のラツチデータと、ストローブ信号入力端
子７から入力されるストローブ信号とにより駆動
される。８は１ライン分のデータを記憶するシフ
トレジスタで、ラツチ回路６から出力されるラツ
チデータにより、通電する発熱抵抗体２が選択さ
れ、ストローブ信号により通電時間が規制される
ように構成されている。
Figure 3 is a circuit diagram of a conventional thermal head drive device, where 1 is a thermal head, 2 is a heating resistor, and 3 is a thermal head drive device.
4 is an AND circuit. 3 and 4 constitute a drive circuit 5, which receives one line of latch data input from the latch circuit 6 and input from the strobe signal input terminal 7. It is driven by a strobe signal. Reference numeral 8 denotes a shift register that stores data for one line, and is configured such that the heating resistor 2 to be energized is selected according to latch data outputted from the latch circuit 6, and the energization time is regulated by a strobe signal.
従来のサーマルヘツド駆動装置は、ラツチ回路
６やシフトレジスタ８、およびストローブ信号発
生回路（図示省略）などの、ドライブ回路５を制
御するロジツク回路を駆動するロジツク電源（例
えば、VR＝5V）の作動開始時の電圧の立上り
が、発熱抵抗体２を駆動する駆動電源（例えば、
VD＝24V）の電圧の立上りより遅く、ロジツク
回路が安定に作動するスレツシヨルド電圧（以
下、Vthと略記する）に達する前に、発熱抵抗体
２に高い駆動電圧VDが印加されると、ロジツク
回路の誤動作により、ドライバ回路５がONとな
つて発熱抵抗体２に長時間電流が流れ、過熱して
破損することがある。
The conventional thermal head drive device uses a logic power supply (for example, V R =5V) to drive logic circuits that control the drive circuit 5, such as the latch circuit 6, shift register 8, and strobe signal generation circuit (not shown). The voltage rise at the start of operation is the driving power source (for example,
If a high driving voltage V D is applied to the heating resistor 2 before the voltage rises later than the voltage rise of V D = 24 V ) and before reaching the threshold voltage (hereinafter abbreviated as Vth) at which the logic circuit operates stably, Due to a malfunction in the logic circuit, the driver circuit 5 is turned on and current flows through the heating resistor 2 for a long time, which may cause it to overheat and be damaged.
また、作動停止時に、ロジツク電源電圧VR
（以下、VRと略記する場合もある）の降下速度
が速く、駆動電源電圧VDの降下速度が遅い場合
にも、同様の問題が生じる。 Also, when the operation is stopped, the logic power supply voltage VR
(hereinafter sometimes abbreviated as VR) is fast and the drive power supply voltage V D is slow to fall, a similar problem occurs.
そこで、従来のサーマルヘツド駆動装置では、
まずロジツク電源電圧VRがVthを越えたのち、駆
動電源電圧VDを印加し、作動停止時には、まず
駆動電源電圧VDを開くシーケンス操作がとられ
ている。 Therefore, in the conventional thermal head drive device,
First, after the logic power supply voltage V R exceeds Vth, the drive power supply voltage V D is applied, and when the operation is stopped, the drive power supply voltage V D is first opened.
しかしながら、作動中に、過負荷などの理由で
ヒユーズが断線し、ロジツク回路の駆動電圧が失
なわれたような場合、ロジツク回路に誤動作を生
じ、ドライブ回路５がONとなつて、発熱抵抗体
２が通電状態となり、過熱により焼損する場合が
ある。 However, if the fuse breaks during operation due to an overload or other reason, and the driving voltage of the logic circuit is lost, the logic circuit will malfunction, the drive circuit 5 will turn on, and the heating resistor will turn on. 2 becomes energized and may burn out due to overheating.
この発明は、上述のようなシーケンス操作を不
要にするとともに、作動中に、過負荷などにより
VRがVthより低下したり、失われた場合、ドライ
ブ回路をOFF状態に移行させて、発熱抵抗体へ
の通電にともなう過熱焼損を防止することがで
き、しかも、何らかの原因でVRが少し下がつた
場合でもチヤタリングを起こすことなく、安定し
た印字動作を保つことができるサーマルヘツド駆
動装置を提供することを目的とする。 This invention eliminates the need for sequence operations as described above, and also eliminates the need for overload during operation.
If V R drops below Vth or is lost, the drive circuit can be turned OFF to prevent overheating and burnout due to energization of the heating resistor. To provide a thermal head drive device capable of maintaining stable printing operation without causing chattering even when the head is lowered.
この発明に係るサーマルヘツド駆動装置は、ロ
ジツク電源電圧VRの立上り時には、ロジツク回
路が安定に動作するように設定されてるスレツシ
ヨルド電圧Vthよりも十分に高いOFF状態解除電
圧Vonになるまでドライブ回路をOFF状態に錠
止し、また、上記ロジツク電源電圧VRの立下り
時には上記スレツシヨルド電圧Vthよりも高く、
かつ上記OFF状態解除電圧Vonよりも低いOFF
状態移行電圧VOFFになつたとき、上記ドライブ回
路をOFF状態に移行させて錠止する保護回路を
備えたことを特徴とする。
In the thermal head drive device according to the present invention, when the logic power supply voltage VR rises, the drive circuit is operated until the OFF state release voltage Von is sufficiently higher than the threshold voltage Vth, which is set to ensure stable operation of the logic circuit. It is locked in the OFF state, and when the logic power supply voltage V R falls, it is higher than the threshold voltage Vth.
and OFF lower than the above OFF state release voltage Von
The present invention is characterized in that it includes a protection circuit that shifts the drive circuit to the OFF state and locks it when the state transition voltage V becomes OFF .
この発明によれば、ロジツク電源電圧VRの立
上り時には、上記スレツシヨルド電圧Vthよりも
十分に高いOFF状態解除電圧Vonになるまでド
ライブ回路をOFF状態に錠止し、また、上記ロ
ジツク電源電圧VRの立下り時には上記スレツシ
ヨルド電圧Vthよりも高く、かつ上記OFF状態解
除電圧Vonよりも低いOFF状態移行電圧VOFFに
なつたとき、上記ドライブ回路をOFF状態に移
行させて錠止する。したがつて、ロジツク電源電
圧VRがスレツシヨルド電圧Vthよりも低い範囲で
は、ドライブ回路をOFF状態に保つので、従来
必要であつた電源のシーケンス回路が不要とな
る。
According to this invention, when the logic power supply voltage V R rises, the drive circuit is locked in the OFF state until the OFF state release voltage Von is sufficiently higher than the threshold voltage Vth, and the logic power supply voltage VR When the OFF state transition voltage V OFF becomes higher than the threshold voltage Vth and lower than the OFF state release voltage Von at the falling edge of the OFF state, the drive circuit is shifted to the OFF state and locked. Therefore, in the range where the logic power supply voltage V R is lower than the threshold voltage Vth, the drive circuit is kept in the OFF state, so the power supply sequence circuit that was conventionally required is no longer necessary.
また、作動中に、過負荷などによつて、ロジツ
ク電源電圧VRがスレツシヨルド電圧Vthよりも低
下するような事態になつたとき、そのスレツシヨ
ルド電圧Vthにまで下降するまでにドライブ回路
を強制的にOFF状態に移行させるので、発熱抵
抗体に長時間電流が流れて該発熱抵抗体が過熱焼
損されることを防止できる。 Additionally, if the logic power supply voltage V R falls below the threshold voltage Vth due to an overload or the like during operation, the drive circuit is forcibly activated until the logic power supply voltage V R drops to the threshold voltage Vth. Since the heating resistor is shifted to the OFF state, it is possible to prevent the heating resistor from being overheated and burnt out due to current flowing through the heating resistor for a long time.
さらに、OFF状態解除電圧Von＞OFF状態移
行電圧VOFFのヒステリス特性をもたせることで、
Vonを超えて印字動作を開始した後に何らかの原
因でロジツク電源電圧VRが少し下がつた場合で
も、印字動作が停止するといつたチヤタリング現
象が発生せず、安定した印字動作を保つことが可
能である。 Furthermore, by providing a hysteresis characteristic of OFF state release voltage Von>OFF state transition voltage V OFF ,
Even if the logic power supply voltage V R drops slightly for some reason after exceeding Von and starting printing, stable printing can be maintained without the chattering phenomenon that occurs when printing stops. be.
第１図はこの発明の一実施例の回路図で、９は
錠止信号発生回路、１０は錠止回路で、９，１０
で保護回路１１を構成する。
FIG. 1 is a circuit diagram of an embodiment of the present invention, in which 9 is a locking signal generation circuit, 10 is a locking circuit, and 9, 10
The protection circuit 11 is configured by:
錠止信号発生回路９は、ロジツク電圧端子とア
ース間に接続されている抵抗r1、r2の直列体、こ
れと並列に接続されているＰチヤンネルMOS
FET P1、ＮチヤンネルMOS FET N2の直列
体、および、抵抗r2に並列接続されている抵抗r3
とＮチヤンネルMOS FET N1の直列体で構成さ
れ、P1のゲートは接地、N1のゲートはP1とN2の
接続点Ａに、N2のゲートはr1、r2の接続点Ｂにそ
れぞれ接続されている。 The locking signal generating circuit 9 consists of a series body of resistors r 1 and r 2 connected between the logic voltage terminal and the ground, and a P channel MOS connected in parallel with this.
FET P 1 , N-channel MOS FET N 2 in series, and resistor r 3 connected in parallel to resistor r 2
The gate of P1 is grounded, the gate of N1 is connected to the connection point A of P1 and N2 , and the gate of N2 is connected to the connection point of r1 and r2 . are connected to B.
また、錠止回路１０は、ストローブ信号が入力
されるNOT回路と、その出力信号が入力される
NOR回路で構成され、NOR回路には、錠止信号
発生回路９のＡ点の電位が錠止信号として入力さ
れており、NOR回路の出力信号は、ドライブ回
路５のAND回路４に、ラツチデータとともに入
力される。 The locking circuit 10 also includes a NOT circuit to which a strobe signal is input, and a NOT circuit to which an output signal thereof is input.
It is composed of a NOR circuit, and the potential at point A of the locking signal generation circuit 9 is input as a locking signal to the NOR circuit, and the output signal of the NOR circuit is sent to the AND circuit 4 of the drive circuit 5 together with the latch data. is input.
つぎに、ロジツク電源のスイツチを投入し、電
圧VRが、零から定電圧に上昇する過程における
保護回路１１の動作を説明する。 Next, the operation of the protection circuit 11 in the process of turning on the logic power supply and increasing the voltage V R from zero to a constant voltage will be described.
第２図において、VRが上昇してゆき、時刻t1に
おいて、スレツシヨルド電圧Vthよりも十分に高
い電圧Vonに達する前は、まずP1がONとなり、
VAVT1（N1のしきい値電圧）となつた時点でN1
はONとなり、Ｂ点の電位VBはr2、r3が並列とな
るので低い電位となり、VBがN2のしきい値電圧
VT2よりも低い間、N2はOFFの状態を保つから、
Ａ点の電位VAはVRとともに上昇し、その間、
NOR回路には錠止信号“１”が入力される。 In FIG. 2, as V R increases and before it reaches a voltage Von that is sufficiently higher than the threshold voltage Vth at time t 1 , P 1 is first turned ON.
When V A V T1 (threshold voltage of N 1 ) is reached, N 1
becomes ON, and the potential V B at point B becomes a low potential because r 2 and r 3 are in parallel, and V B becomes the threshold voltage of N 2
Since N 2 remains OFF while V is lower than T2 ,
The potential V A at point A increases with V R , and during that time,
A locking signal “1” is input to the NOR circuit.
この状態において、ストローブ信号がNOT回
路を介してNOR回路に入力されても、NOR回路
の出力は“０”であるから、ドライバ回路５の
AND回路４はOFF状態に錠止され、ラツチデー
タがAND回路４に印加されていても、いずれの
発熱抵抗体２にも電流は流れない。 In this state, even if the strobe signal is input to the NOR circuit via the NOT circuit, the output of the NOR circuit is “0”, so the driver circuit 5
The AND circuit 4 is locked in the OFF state, and even if latch data is applied to the AND circuit 4, no current flows through any of the heating resistors 2.
つぎに、VRが上昇してVthより十分に高い
OFF状態解除電圧Vonを越えると、VBがN2のし
きい値電圧VT2を越え、N2はONとなる。すると、
VAが零となり、NOR回路への錠止信号入力は
“１”→“０”に変り、ストローブ信号が入力さ
れたとき、NOR回路の出力は“１”となつて、
AND回路４に入力され、ラツチデータにより選
択されたAND回路４がONとなり、発熱抵抗体
２に通電される。 Next, V R rises and is sufficiently higher than Vth
When the OFF state release voltage Von is exceeded, V B exceeds the threshold voltage V T2 of N 2 and N 2 is turned ON. Then,
When V A becomes zero, the lock signal input to the NOR circuit changes from "1" to "0", and when the strobe signal is input, the output of the NOR circuit becomes "1",
The AND circuit 4 that is input to the AND circuit 4 and selected by the latch data is turned on, and the heating resistor 2 is energized.
VBがVT2を越えるVRの電圧は、Vthより十分に
高くなるように、r1、r2、r3の値が設定されてい
るので、ロジツク回路は正常に作動する。また、
VA→零となると同時にN1がOFFとなつてr3が開
路され、VBは、高い電位に跳躍するので、N2の
動作にチヤタリングを生じることがなく、錠止状
態の解除は安定に行なわれる。 Since the values of r 1 , r 2 , and r 3 are set so that the voltage of V R where V B exceeds V T2 is sufficiently higher than Vth, the logic circuit operates normally. Also,
At the same time as V A → becomes zero, N 1 is turned OFF and r 3 is opened, and V B jumps to a high potential, so there is no chattering in the operation of N 2 and the unlocking is stable. It will be held in
つぎに、ロジツク電源電圧VRが、故障等の理
由で零に下降する場合の保護回路１１の動作を説
明する。 Next, the operation of the protection circuit 11 when the logic power supply voltage V R drops to zero due to a failure or the like will be explained.
VRが第２図に示すように下降してゆき、時刻t2
で、Vonより低く、Vthより高く設定したOFF状
態移行電圧VOFFに達たとき、Ｂ点の電位VBはVB
＜VT2となりN2がOFFとなる。すると、Ａ点の電
位VAは零→＋電位と変り、NOR回路に錠止信号
“１”が入力されるので、ドライブ回路５がOFF
状態に錠止される。同時に、N1がONとなつてr3
はr2に並列に接続されVBは、より低い電位に跳
躍するので、N2の動作にチヤタリングを生じな
い。 V R continues to fall as shown in Figure 2, and at time t 2
When the OFF state transition voltage V OFF , which is set lower than Von and higher than Vth, is reached, the potential V B at point B becomes V B
<V T2 and N 2 turns OFF. Then, the potential V A at point A changes from zero to + potential, and the lock signal "1" is input to the NOR circuit, so the drive circuit 5 is turned OFF.
locked in state. At the same time, N 1 turns on and r 3
is connected in parallel with r 2 and V B jumps to a lower potential so that it does not cause any chatter in the operation of N 2 .
このように、この実施例の保護回路１１は、ロ
ジツク電源電圧VRの立上り時に、VRが、Vthよ
りも十分に高い電位Vonになるまで、ドライブ回
路をOFF状態に錠止し、また、VRが下降した時、
VRがVOFFより低くなつた時点でドライブ回路５
をOFF状態に鎖止する。したがつて、VRがVth
よりも低い場合に発熱抵抗体２に通電されること
がないので、従来、必要とされていた、電源シー
ケンス操作が不要となるばかりでなく、動作中に
ロジツク電源に故障等が生じても、これに伴うサ
ーマルヘツドの発熱抵抗体の焼損等を防止するこ
とができる。 In this way, the protection circuit 11 of this embodiment locks the drive circuit in the OFF state when the logic power supply voltage V R rises until V R reaches the potential Von that is sufficiently higher than Vth. When VR falls,
When V R becomes lower than V OFF , drive circuit 5
is locked in the OFF state. Therefore, V R is Vth
Since the heating resistor 2 is not energized when the voltage is lower than This can prevent burnout of the heating resistor of the thermal head.
なお、上記実施例は、抵抗r1、r2、r3、MOS
FET、NOR回路およびNOT回路で構成したも
のを示したが、この構成に限られるものでないこ
とはいうまでもない。 Note that in the above embodiment, the resistors r 1 , r 2 , r 3 , MOS
Although the structure shown here includes a FET, a NOR circuit, and a NOT circuit, it goes without saying that the structure is not limited to this.
以上のように、この発明によれば、ロジツク電
源VRがスレツシヨルド電圧VthVthよりも低い範
囲では、ドライブ回路をOFF状態に保つので、
従来必要であつた電源のシーケンス回路が不要と
なり、従来に比べて低コストに構成できる。
As described above, according to the present invention, the drive circuit is kept in the OFF state in the range where the logic power supply V R is lower than the threshold voltage VthVth.
The power supply sequence circuit that was required in the past is no longer necessary, and the structure can be constructed at a lower cost than in the past.
また、作動中に、過負荷などによつて、ロジツ
ク電源電圧VRがスレツシヨルド電圧Vthよりも低
下するような事態になつたときは、そのスレツシ
ヨルド電圧Vth信号にまで下降するまでにドライ
ブ回路を強制的にOFF状態に移行させるので、
発熱抵抗体に長時間電流が流れて該発熱抵抗体が
過熱焼損されることを防止できる。 Additionally, if the logic power supply voltage V R falls below the threshold voltage Vth due to an overload or the like during operation, the drive circuit is forced to shut down until the logic power supply voltage V R drops to the threshold voltage Vth signal. Because it automatically shifts to the OFF state,
It is possible to prevent the heating resistor from being overheated and burnt out due to the current flowing through the heating resistor for a long time.
しかも、OFF状態解除電圧Von＞OFF状態移
行電圧VOFFのヒステリス特性をもたせることで、
Vonを超えて印字動作を開始した後に何らかの原
因でロジツク電源電圧VRが少し下がつた場合で
も、印字動作が停止するといつたチヤタリング現
象が発生せず、常に安定した印字動作を保つたこ
とができるという効果を奏する。 Moreover, by providing a hysteresis characteristic of OFF state release voltage Von>OFF state transition voltage V OFF ,
Even if the logic power supply voltage V R drops slightly for some reason after exceeding Von and starting printing, the chattering phenomenon that occurs when printing stops does not occur, and stable printing is always maintained. It has the effect of being able to do it.
第１図はこの発明の一実施例によるサーマルヘ
ツド駆動装置の回路図、第２図はこの実施例の動
作を説明するためのロジツク電源電圧の波形図、
第３図は従来のサーマルヘツド駆動装置の回路図
である。
１……サーマルヘツド、５……ドライブ回路、
９……錠止信号発生回路、１０……錠止回路、１
１……保護回路。なお、図中、同一符号はそれぞ
れ同一、または相当部分を示す。
FIG. 1 is a circuit diagram of a thermal head driving device according to an embodiment of the present invention, and FIG. 2 is a waveform diagram of a logic power supply voltage for explaining the operation of this embodiment.
FIG. 3 is a circuit diagram of a conventional thermal head driving device. 1...Thermal head, 5...Drive circuit,
9...Lock signal generation circuit, 10...Lock circuit, 1
1...Protection circuit. In addition, in the figures, the same reference numerals indicate the same or corresponding parts.
Claims (1)
するドライブ回路と、このドライブ回路を駆動す
るラツチ回路およびそのラツチ回路から出力され
るラツチデータにより通電する発熱低抗体を選択
するシフトレジスタを含むロジツク回路と、この
ロジツク回路を駆動するロジツク電源とを具備し
たサーマルヘツド駆動装置において、上記ロジツ
ク電源電圧の立上り時には、上記ロジツク回路が
安定に動作するように設定されているスレツシヨ
ルド電圧Vthよりも十分に高いOFF状態解除電圧
Vonになるまで、上記ドライブ回路をOFF状態
に錠止し、また、上記ロジツク電源電圧の立下り
時には上記スレツシヨルド電圧Vthよりも高く、
かつ上記OFF状態解除電圧Vonより低いOFF状
態移行電圧VOFFになつたとき、上記ドライブ回路
をOFF状態に移行させて錠止する保護回路を備
えたことを特徴とするサーマルヘツド駆動装置。1. A logic circuit including a drive circuit that controls energization of the heat-generating low antibody of the thermal head, a latch circuit that drives this drive circuit, and a shift register that selects the heat-generating low antibody to be energized based on latch data output from the latch circuit. , and a logic power supply for driving this logic circuit, when the logic power supply voltage rises, the OFF voltage is sufficiently higher than the threshold voltage Vth set so that the logic circuit operates stably. State release voltage
Von, the drive circuit is locked in the OFF state, and when the logic power supply voltage falls, the voltage is higher than the threshold voltage Vth,
A thermal head drive device comprising: a protection circuit for shifting and locking the drive circuit to the OFF state when the OFF state transition voltage V OFF becomes lower than the OFF state release voltage Von.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60192217A JPS6250180A (en) | 1985-08-29 | 1985-08-29 | Thermal head drive unit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60192217A JPS6250180A (en) | 1985-08-29 | 1985-08-29 | Thermal head drive unit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6250180A JPS6250180A (en) | 1987-03-04 |
| JPH0557916B2 true JPH0557916B2 (en) | 1993-08-25 |
Family
ID=16287608
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60192217A Granted JPS6250180A (en) | 1985-08-29 | 1985-08-29 | Thermal head drive unit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6250180A (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6481814B2 (en) | 2001-02-28 | 2002-11-19 | Lemark International, Inc. | Apparatus and method for ink jet printhead voltage fault protection |
| CN104786676B (en) * | 2014-01-21 | 2017-04-05 | 北大方正集团有限公司 | Ink jet-print head power supply time sequence control device |
| US9636908B2 (en) | 2014-09-30 | 2017-05-02 | Brother Kogyo Kabushiki Kaisha | Liquid discharging apparatus |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57152020A (en) * | 1981-03-16 | 1982-09-20 | Seiko Epson Corp | Power supply circuit for device with small sized printer |
| JPS5964374A (en) * | 1982-10-05 | 1984-04-12 | Sanyo Electric Co Ltd | Apparatus for driving thermal head |
| JPS59148679A (en) * | 1983-02-15 | 1984-08-25 | Matsushita Electric Ind Co Ltd | Thermal head driver |
| JPS6063951A (en) * | 1983-09-16 | 1985-04-12 | Hitachi Ltd | Semiconductor device and manufacture thereof |
-
1985
- 1985-08-29 JP JP60192217A patent/JPS6250180A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6250180A (en) | 1987-03-04 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |