JPH0559621B2 - - Google Patents

Description

[Detailed Description of the Invention] (Technical field to which the invention pertains) The present invention relates to a receiving device using a matched filter in a direct spread spectrum communication system, which is a type of spread spectrum communication system, and particularly relates to a reception device using a matched filter. It is related to synchronous circuits.

(Prior art and its problems) In the spread spectrum communication system, the direct spread system using two-phase phase keying (PSK) modulates the carrier wave with two-phase phase modulation using information data, and then compares the signal transmission rate with the data. The signal is transmitted after being binary-phase modulated using a fast pseudo-random code, or the carrier wave is subjected to binary-phase modulation using the output obtained by multiplying the pseudo-random code and data and transmitted as a spread signal.

A to d in FIG. 2 are examples of waveforms on the transmitting side, where a is information data to be transmitted, b is a pseudorandom code, and c
is the product of both a and b, and d is a spread signal subjected to two-phase phase modulation with the product output c. Here, a case is shown in which the length of one bit of information data a and the length of one period of pseudorandom code b are equal.

FIG. 1 is a diagram illustrating a configuration example of a demodulating section of a receiving apparatus that receives a spread signal. Although there are various demodulation methods, this figure shows a demodulation section circuit using a matched filter 1 in an intermediate frequency band.

2. e to g in FIG. 2 show examples of waveforms of each part of the reception demodulation section in FIG. 1. Matsushido filter 1 is
For example, it can be easily realized using a surface acoustic wave element or the like, and when a desired received signal is input to this, an output having a correlation peak at each period of the pseudorandom code as shown in waveform e is obtained. In the receiving device,
Data demodulation is performed in synchronization with the position of this peak. That is, when the output e of the matched filter 1 is input to the synchronous detector 2 and synchronously detected using the carrier wave regenerated by the carrier wave regeneration circuit 4, an output of waveform f is obtained. A demodulated output g is obtained by sampling this output f at the position of the peak in the sampling determination circuit 3 and determining whether it is positive or negative. If you sample at the peak position like this,
It is possible to determine the S/N in a state where the S/N is improved by the ratio between the code rate of the pseudorandom code and the data transmission rate, that is, the spreading gain of the spread spectrum, with respect to the input.

A timing synchronization circuit 27 that adjusts the sampling timing to the position of this peak is composed of a circuit from an envelope detector 5 to a clock generation circuit 9. The output e of the matched filter 1 is detected by the envelope detector 5, and the phase difference between the detected output and the output clock of the clock generation circuit 9 is determined by the phase detection circuit 6. The oscillation frequency and phase of a voltage controlled oscillator (VCO) 8 having a frequency equal to the repetition frequency are controlled to match the timing of the output clock of the clock generation circuit 9 obtained from the output of the VCO 8 with the peak position of the input signal.

Figure 3 shows the timing synchronization circuit 2 in Figure 1.
This is an example of the circuit configuration of the phase difference detection circuit 6 used in 7, in which 10 and 11 are analog gates (GATE), 12 is a subtraction circuit (SUB), 13, 14
is an input terminal for gate pulses that control the opening and closing of the two analog gates 10 and 11, and is an input from the clock generation circuit 9.

Figure 4 shows the waveforms of each part of the circuit in Figure 3, where h is the input from the envelope detector 5, i and j are the gate pulses input from 13 and 14, and k and l are the outputs of analog gates 10 and 11. , m are the outputs of the arithmetic circuit 12. As shown in the figure, if the output h from the envelope detector 5 has a peak at the time of switching between the two gate pulses i and j, the DC components of the outputs of both gates 10 and 11 are equal, and the subtraction The DC component of the output m of the circuit 12 becomes 0V. However, if the switching point between the two gate pulses i and j and the peak position of the output h shift, one gate output becomes larger depending on the magnitude and direction of the phase difference, so the output m of the subtraction circuit 12 The DC component becomes a positive or negative voltage corresponding to the direction of the phase difference. The output m corresponding to this phase difference passes through the LPF 7 and controls the frequency and phase of the VCO 8 to achieve synchronization.

In order to detect the phase difference using the circuit shown in FIG. control and even a second
Accurate timing was adjusted using analog gates 10 and 11 at each step. In this way, it is necessary to configure a complex control circuit that spans two stages.
The drawback is that it takes time to synchronize. Furthermore, the degree of spreading was limited because it was difficult to manufacture high-speed analog gates capable of passing direct current, which is required when increasing the speed of pseudo-random codes and spreading the spectrum over a wide band.

(Objective of the Invention) An object of the present invention is to provide a spread spectrum signal receiving device equipped with a synchronization circuit that has accurate and stable synchronization pull-in operation with a simple circuit configuration and can cope with increased speed of spread signals. It's about doing.

(Structure of the invention) The present invention will be explained in detail below with reference to the drawings.

FIG. 5 shows an example of the circuit configuration of the phase difference detection circuit 6 in the timing synchronization circuit 27 implementing the present invention.
In the figure, 15 and 16 are analog delay lines having the same delay time t, 17 is a comparator that compares the voltage between the output p of the delay line 16 and the input h from the envelope detector 5, and 18 is the first stage A comparator 19 compares the output voltage n of the delay line 15 with a preset threshold voltage, and 19 indicates both comparators 17 and 18.
AND gate that takes the logical product of the outputs q and r, 20
is a counter that repeats counting at the cycle of the input 24 from the clock generation circuit 9, and 25 is a counting clock whose frequency is an integral multiple of the input 24, preferably several times the spreading code speed, and is generated by the clock generation circuit 9. . 21 is a ROM that converts the code of the output of the counter 20, and 22 is an output u of the ROM 21.
23 is a D/A converter, 26
is the output of the D/A converter, that is, the phase difference detection circuit 6
This is the output of

6 is an example of waveforms of each part of the phase difference detection circuit 6 of FIG. 5 according to the present invention, h is the input from the envelope detector 5, n is the output of the first stage delay line 15, and p is the 2
The output of the delay line 16 in the second stage, q is the output of the comparator 17, r is the output of the comparator 18, s is the AND gate 1
9, u indicates the voltage represented by the output code of the ROM 21.

The operation of the phase difference detection circuit 6 used in the present invention will be explained below with reference to FIGS. 5 and 6. The input h from the envelope detector 5 is input to the comparator 17 as an output p delayed by 2t by delay lines 15 and 16 having the same delay time t. The delay time t is a value smaller than about 1/2 of the correlation peak width A that appears in each period of the pseudorandom code and larger than 0, and is a value that takes into account the noise contained in the input h from the envelope detector, the accuracy of the comparator 17, etc. Considering (1/2)A
~(1/4)A is appropriate. The comparator 17 compares the level of this delayed output p and the other input h, and if the former is large, it is "1", and if the latter is large, it is "0".
Since it is set to output an output q,
This output q changes from "0" to "1" at a position delayed by t from the position of the correlation peak of input h.

On the other hand, the comparator 18 obtains an output r that becomes "1" when the output n obtained by delaying the input h by t in the first stage delay line 15 is greater than a preset threshold voltage v. The output q of the comparator 17 shows many changes from "0" to "1" due to the waveform w having a small level other than the correlation peak, but the output r of the comparator 18 shows the set threshold voltage v and It does not appear in the output because it is compared.

The threshold voltage v of the comparator 18 is a value such that the output of the comparator 18 does not become "1" due to the correlation waveform w of a small signal other than the correlation peak of the output of the matched filter 1 and noise input together with the signal. Moreover, it is set to a value that can sufficiently extract the correlation peak output that appears in each period of the pseudorandom code. The outputs q and r of both comparators 17 and 18 are
If we take AND, we get the output s. On the other hand, the counter 20 is counted up by the counting clock 25 from the clock generating circuit 9, and is reset by the clock 24 having a repetition frequency equal to the repetition frequency of the spreading pseudorandom code. Counting clock 25 is clock 2
Since the value is an integer multiple of 4, the output of the counter 20 is equal to the stepwise rise of the clock 25.
It becomes a sawtooth waveform that is reset at , and when expressed in terms of voltage, it becomes a waveform like U. The waveform u in FIG. 6 is an example when the output of the code conversion ROM 21 is the same as the input (that is, no ROM is used), and when both the output of the counter 20 and the output of the ROM 21 are expressed in voltage, the waveform u becomes. This is sampled by a register 22 using a pulse s obtained from the received data, and an output 26 is obtained via a D/A converter 23. As shown in FIG. 6, this output 26 is approximately
However, if the timing between the input h and the clock is misaligned, the voltage becomes a DC voltage with a polarity corresponding to the direction of the misalignment (phase difference) and a voltage proportional to the magnitude of the misalignment. By this output 26
A synchronous circuit is constructed by controlling the voltage controlled oscillator 8 via the LPF 7.

The phase difference detection circuit 6 having a phase difference detection characteristic like the waveform u in FIG. There is no need for complex synchronous pull-in processing. Furthermore, since circuit elements such as analog switches are not used, a circuit suitable for high-speed operation can be constructed.

FIGS. 7 and 8 show output waveforms u' and u'' when the output of the counter 20 is converted into another form by the code conversion ROM 21.

The waveform u' in Fig. 7 is proportional to the phase difference in the range where the phase difference between the input h and the clock is close to 0, and the phase difference is 0.
This is the output voltage waveform of the ROM 21 when the sign is converted so that it becomes a constant positive or negative voltage in a sufficiently larger range. In this case, compared to the characteristics of the waveform u in Fig. 6, the detection output is large when the phase difference is large, so the pull-in time is fast, and the slope near the phase difference of 0 is large, so the pull-in can be performed with higher precision. be.

The waveform u'' in Fig. 8 is obtained when the sign is converted so that the detected output is obtained only in the range where the phase difference between the input h and the clock is close to 0, and the output becomes 0 in the range where the phase difference is sufficiently larger than 0. This is the output voltage waveform of the ROM 21. In the case of the waveforms u and u' mentioned above, if the peak detection output s appears at the wrong position due to noise etc., a large abnormal voltage is generated at the output 26 and the VCO 8
There is a risk that the oscillation frequency of the oscillation frequency will change and the synchronization state will become unstable, but such a risk can be prevented if the detection characteristics are as shown in the waveform u' in FIG.
However, with the detection characteristics of the waveform u'' shown in Figure 8, if the phase difference is large, it is not possible to pull in the waveform. It is effective to perform processing such as switching to the detection characteristic of the waveform u''.

In addition, if any detection characteristics other than the detection characteristics such as waveforms u, u' and u'' are valid, the ROM21
An effective phase difference detection circuit can be realized by changing the contents of .

(Effects of the Invention) As explained in detail above, according to the present invention, a simple synchronization circuit can be configured without using a conventional complicated control circuit, and a stable and accurate synchronization state can be achieved. In addition, it is possible to achieve optimal synchronization characteristics depending on the situation. Furthermore, it can be used as a stable synchronization circuit even in the case of high-speed spread signals.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an example of a demodulating section circuit of a receiving device to which the present invention is applied, FIG. 2 is an example diagram of transmission waveforms of a transmission system to which the present invention is applied, and waveforms of each part of the circuit in FIG. 1. 4 is a block diagram showing an example of a phase difference detection circuit used in a conventional receiver, FIG. 4 is an example of waveforms of each part of the circuit in FIG. 3, and FIG. 5 is a diagram showing a phase difference detection circuit used in a receiver of the present invention. A block diagram showing a configuration example of a detection circuit, FIG. 6 is a waveform example diagram of each part of the configuration example in FIG. 5, and FIGS. 7 and 8 are waveform example diagrams resulting from code conversion other than that shown in FIG. . 1...Matched filter, 2...Synchronous detector,
3...Sampling judgment circuit, 4...Carrier regeneration circuit, 5...Envelope detector, 6...Phase difference detection circuit, 7...LPF, 8...VCO, 9...Clock generation circuit, 10, 11 ...GATE, 12...
SUB, 13, 14... Gate input terminal, 15,
16...Delay line, 17, 18...Comparator, 19
...AND, 20...Counter, 21...ROM,
22...Register, 23...D/A converter, 2
4, 25...Clock input, 26...Output, 27
...Timing synchronization circuit.

Claims (1)

[Claims] 1. The position of the correlation peak of the envelope detection output obtained by envelope detection of the output of a matched filter that receives a spread spectrum signal as input, and the position of the correlation peak of the envelope detection output obtained by envelope detection of the output of a matched filter that inputs a spread spectrum signal, and A phase difference detection circuit detects a phase difference with a demodulation timing clock pulse generated from a voltage controlled oscillator, controls the voltage controlled oscillator based on the phase difference to create a demodulation timing clock pulse, and generates a demodulation timing clock pulse. In a spread spectrum signal receiving device that samples the output of a wave detector to obtain a demodulated output, the phase difference detection circuit converts the envelope detection output by a delay time that is less than about 1/2 the width of the correlation peak. A first delay line and a second delay line are continuously connected for successive delay, and the voltages of the second delay line output and the envelope detector output are compared, and the second delay line output is determined. a first comparator that outputs an output when the first delay line output exceeds a preset threshold voltage; and a second comparator that outputs an output when the first delay line output exceeds a preset threshold voltage; an AND gate that takes the AND of each output of the device, a counter that resets the count in synchronization with the demodulation timing clock pulse, a ROM that converts the output of the counter into a preset waveform, and the ROM. A receiver for a spread spectrum signal, comprising: a register that samples the output of the register with the output pulse of the AND gate; and a D/A converter that converts the output of the register into a D/A converter to obtain a DC output. .