JPH0561901A - Program-controlled processor - Google Patents

Abstract

(57) [Summary] (Modified) [Objective] To provide a processor capable of achieving high performance by implementing and controlling a pipeline arithmetic unit as a resource of a general-purpose processor of a program control system. Configuration: The program control circuit 1 stops an internal program counter and repeats the execution cycle of a vector pipeline instruction. The address generator 2 continuously generates m addresses in a preset sequence in response to a start signal from the program control circuit 1, and m memory read cycles are continuously started from the data memory 3. The control circuit 1 also controls the function and pipeline configuration of the data processing circuit 4. When the address generator 2 finishes generating m addresses, the program control circuit 1
Give an end signal to. After receiving the end signal from the address generator 2, the control circuit 1 delays it by two more cycles and restarts the program counter. And N
The instructions after the specific instruction of the address are executed sequentially.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a program control type processor, and more particularly to an architecture of a digital signal processor (hereinafter referred to as DSP) which requires high speed arithmetic processing.

[0002]

2. Description of the Related Art A conventional program control type general-purpose processor, for example, a RISC type microinstruction set, includes a memory read / write, register set,
Instruction groups such as data transfer between registers and various arithmetic and logic operations are mounted, and various processing is realized by programming using these instructions. Most of these command groups are commands that command a single operation.
By combining simple operations, finally complex and sophisticated processing can be realized and versatility is realized.

However, since the above-mentioned single operation instructions must be sequentially executed one by one, there has been a problem in terms of processing speed from the prior art.

[0004]

As described above, the processor of the conventional program control system is programmed by combining the single operation instructions and sequentially executes the instructions one by one. There was a problem in terms.

This is an important problem especially in a DSP that requires high-speed arithmetic processing. Compared with a general-purpose processor, a DSP has various speeds up such as a built-in multiplier, a built-in program memory, a separated division of a data memory, a separated division of a data bus / address bus. However, like a general-purpose processor, it is programmed by a single operation instruction and executed one instruction at a time. When the required processing speed cannot be obtained by the program control type DSP, it is necessary to individually develop dedicated hardware that specifies processing.

The present invention has been made in view of the above-mentioned problems, and provides a program control type processor capable of achieving high performance by mounting and controlling a pipeline arithmetic unit as a resource of a general-purpose processor of a program control system. To aim.

[0007]

A program control type processor according to the present invention implements a plurality of instructions including a vector pipeline instruction and executes a pipeline operation based on the vector pipeline instruction. A program control type processor having
A vector including a program memory, a program counter and a decoder, and when the vector pipeline instruction is read from the program memory and decoded by the decoder, the program counter is stopped and an activation signal is output. A program control circuit for controlling the operation of the data processing circuit according to the contents of the pipeline instruction, and an address is continuously generated according to a preset sequence on the basis of the start signal to generate a preset number of addresses. An address generator that outputs an end signal to the program control circuit when the generation is completed, and a data memory that outputs data stored in advance at the generated address based on the address generated by the address generator. And the data processing circuit comprises: Run the pipeline operation under the control of the program control circuit based on the output data from Tamemori, the program control circuit,
After a predetermined cycle from the reception of the end signal, the end of the pipeline operation based on the vector pipeline instruction is detected, and the instructions following the vector pipeline instruction are sequentially executed.

[0008]

With the above-described structure, the present invention can realize a processor in which a vector pipeline instruction for pipeline processing is additionally mounted on the conventional instruction set for instructing a single operation. When the vector pipeline instruction is read, the processor of the present invention sequentially reads the contents of the data memory in a preset order independently of the program control circuit, and executes the operation cycle in parallel with this reading cycle. Then, the pipeline processing is performed, and the output of the arithmetic unit is sequentially written in parallel to another data memory or is sequentially accumulated by an accumulator. When the operation of the set number of data is completed, the instruction is executed sequentially from the instruction at the step next to the vector pipeline instruction, as in the conventional processor. That is, one vector pipeline instruction executes all the operations shown in (Equation 1) or (Equation 2) in pipeline parallel.

[0009]

[Equation 1]

[0010]

[Equation 2]

Here, Ai and Bi are respectively input vector data to the arithmetic unit read from the data memory, and here, there are two inputs, but the number is not limited. Yi is output vector data of the arithmetic unit and is written in another data memory. Further, X is the result data obtained by accumulating the output data of the arithmetic unit by the accumulator. Also, the arithmetic function of the arithmetic unit is indicated by a function F, and the arithmetic unit is selected or reconfigured so as to exhibit the required function depending on the content of the instruction.

[0012]

1 is a block diagram showing the concept of a processor according to the present invention. The processor of the present invention implements vector pipeline instructions in addition to the conventional instruction set. In FIG. 1, reference numeral 1 is composed of a program memory, a program counter, a decoder, and the like. When this vector pipeline instruction is read from the program memory, the program counter is stopped and an activation signal is output, and the vector pipeline is further added. The program control circuit 2 for controlling the function and pipeline configuration of the data processing circuit according to the contents of the instruction is independent of the program control circuit by the start signal and continuously generates and sets the address in a preset sequence. When generation of a number of addresses is completed, the program control circuit 1
An address generator 3 which gives an end signal to the data memory 3 inputs the address and continuously outputs data, and 4 inputs the data read from the data memory 3,
It is a data processing circuit for performing pipeline operation. The execution unit 5 is composed of an address generator 2, a data memory 3, and a data processing device 4.

The operation of FIG. 1 will be described with reference to the operation timing chart of FIG. FIG. 2 shows how the program control circuit 1 of FIG. 1 sequentially reads out the instructions stored in the program memory and controls the execution, and the instruction at address N executes the pipeline processing according to the present invention. Is.

In FIG. 2, it is assumed that the instructions other than the instruction at address N are conventional single operation instructions and are not branch instructions. Further, for simplification of description, cycles required for instruction fetch, decode, etc. are omitted and only execution cycles are shown. Execution of a conventional single-operation instruction other than the instruction at address N is completed in one cycle, with each resource in the processor being controlled as in the conventional processor. Then, the sequential instructions are read and executed, and N-2, N-1
The instruction execution cycle of the address indicates execution of this conventional single operation instruction. When the vector pipeline instruction at the address N is read out and decoded, first, the program control circuit 1 of FIG. 1 stops the internal program counter and controls the vector pipeline instruction execution cycle to be repeated. In addition, the program control circuit 1
From the cycle in which the activation signal is given to the address generator 2, the address generator 2 continuously generates m addresses in a preset sequence. As shown, m memory read cycles are continuously started. Further, the program control circuit 1 controls the data processing circuit 4 in accordance with the content of the instruction to control the function and pipeline configuration of the data processing circuit 4. This can be easily realized by the data processing circuit 4 having a plurality of arithmetic units, registers, memories, and the like, and reconfiguring the combination of respective inputs and outputs by using a multiplexer or the like. FIG. 2 shows a case where the control is performed by a three-stage pipeline configuration of memory reading, processing 1 and processing 2.

By performing the above control,
As shown in FIG. 2, the three-stage pipeline processing of memory reading, processing 1 and processing 2 can be continuously executed for m pieces of data. When the address generator 2 finishes generating m addresses, it gives an end signal to the program control circuit 1. The program control circuit 1 reads out the current vector pipeline instruction from the memory, and processes 1 and 2
I understand that it is a three-stage pipeline process of
Using this information, the program counter is restarted with a further delay of two cycles after receiving the end signal from the address generator 2, ie waiting for the end of all pipeline cycles. Then, the instructions after the vector pipeline instruction at the address N, that is, the instructions at the addresses N + 1, N + 2, N + 3 are sequentially executed.

As described above, according to the present invention, a processor in which a new vector pipeline instruction for realizing pipeline parallel processing is added to the conventional instruction set can be realized. With this vector pipeline instruction, the high speed of pipeline parallel processing and the compression of the program memory capacity can be realized at the same time without losing the versatility of the program control, as compared with the case of using the conventional instruction set.
In the processor of FIG. 1, one instruction at address N
Memory reading for m pieces of data, processing 1, processing 2
Execution control of all three stages of pipeline parallel processing is performed. And this processing is realized in (m + 2) cycles. Controlling using a conventional single operation instruction requires at least 3 m cycles, which is about 3 times faster, and if the number of pipeline processing steps is increased, further higher speed can be easily realized.

FIG. 3 is a block diagram showing the program control circuit of FIG. In FIG. 3, the program control circuit 1
Is a program counter 10 and a program memory 11
, The decoder 12, the vector instruction control circuit 13, and the instruction register circuit 14 as main constituent elements.

The instruction in the program memory 11 addressed by the program counter 10 is read out, the decoder 12 decodes the instruction through the first pipeline register 15, and the second pipeline register 16 through the second pipeline register 16. Are connected so as to send control signals to respective units to the execution unit 5 to form a pipeline for the program memory 11 read cycle, instruction decode cycle, and instruction execution cycle.

The program counter 10 has a program counter register 17, a first multiplexer 18 and an incrementer 19. The first multiplexer 18 outputs the output of the incrementer 19, the branch address control circuit 20 or the program counter register 17. One of them is selected and connected to the program counter register 17.

The instruction register circuit 14 has a second multiplexer 21 and a first pipeline register 15, and the first pipeline register 15 is connected to the program memory 11 or the first pipeline register 15 by the second multiplexer 21. It is connected to select and input one of the outputs of the pipeline register 14.

The vector instruction control circuit 13 includes a decoder 1
The control of the first multiplexer 18 and the second multiplexer 18
Controlling the multiplexer 21 of the execution unit 5 at the same time
Is connected to receive an end signal from the execution unit 5 by sending a start signal to the.

When the program control circuit 1 sequentially reads out the instructions from the program memory 11 and executes them, when the vector pipeline instruction is decoded by the decoder 12, the vector instruction control circuit 13 causes the execution unit to be executed. 5 is given a start signal. At the same time, the vector instruction control circuit 13 controls so that the first multiplexer 18 selects the output of the program counter register 17 and the program counter register 17 holds the data by itself. Further, the second multiplexer 21
Selects the output of the first pipeline register 15 and controls the first pipeline register 14 to hold the data by itself, thereby controlling the vector pipeline instruction to be continuously executed for a plurality of cycles. ..
Here, the program counter 17 and the pipeline register 15 may directly stop the write clocks of these registers as a means for holding the data themselves. Then, when the vector instruction control circuit 13 receives the end signal from the execution unit 5, it delays for a certain cycle according to the content of the vector pipeline instruction, and the first multiplexer 18 and the second multiplexer 18 are delayed. By releasing the control of 21, the self-holding of the program counter register 17 and the self-holding of the first pipeline register 15, the instructions after the vector pipeline instruction are sequentially executed.

FIG. 4 is a block diagram showing the execution unit of FIG. In FIG. 4, the execution unit 5 includes an address generator 2 including first, second, and third address generators 30, 31, and 32, a first, second, and third data memory 33,
It has a data memory 3 composed of 34 and 35, and a data processing circuit 4. The first and second address generators 30 and 31 generate addresses of the first and second data memories 33 and 34, respectively, and the data read from the first and second data memories 33 and 34 are data. The arithmetic processing is performed by the processing circuit 4, and the third
2 is connected to generate an address of the third data memory 35 and write the data processed by the data processing circuit 4 into the third data memory 35. The data processing circuit 4 includes the ALU 36 and the multiplier 3
7, an arithmetic unit block 40 having first and second pipeline arithmetic units 38 and 39, a register 41, an accumulator 42, and a data flow between the arithmetic unit block 40, the register 41, and the accumulator 42. It is composed of a data path selection circuit 43 for switching.

FIG. 5 is a block diagram showing a vector instruction control circuit in the processor of the present invention. In FIG. 5, the vector instruction control circuit 13 includes a start signal generator 50 of the source memory / address generator, a start signal generator 51 of the destination memory / address generator,
It is composed of a first multiplexer control signal generator 52, a second multiplexer control signal generator 53, and a vector instruction delay analyzer 54.

Then, the activation signal generator 50 of the source memory address generator 2 receives the vector instruction signal which the decoder 12 decodes the vector pipeline instruction and outputs to the vector instruction control circuit 13 according to the source memory address generator 2. Is asserted, and the end signal output from the address generator 2 is negated.
In FIG. 5, the RS flip-flop 55 is used to set the start signal by the vector command signal and assert it until reset by the end signal.

Next, the start signal generator 51 of the destination memory address generator is one of the first shift register 56 to which the vector command signal is input and one of the delay outputs of the first shift register 56. Is selected and output. At the same time that the decoder 12 outputs the vector instruction signal, it simultaneously decodes the type of the vector pipeline instruction and outputs the vector instruction type signal. Based on this vector instruction type signal, the vector instruction delay analyzer 54 determines the required delay and controls the third multiplexer 57. The output of the third multiplexer 57 is supplied as a start signal for the destination memory address generator and accumulator.

Next, the second multiplexer control signal generator 53 selects and outputs one of the second shift register 58 to which the end signal is input and each delay output of the second shift register 58. Fourth multiplexer 59 and A
It is composed of the ND gate 60. The fourth multiplexer 59 is controlled by the vector instruction delay analyzer 54 by determining the required delay according to the vector instruction type signal. Then, the vector command signal asserts the second multiplexer control signal, and the output of the fourth multiplexer controls the negation. In FIG. 5, AND gate 60 is used to assert the second multiplexer control signal with the vector instruction signal and hold the state until negated by the output of the fourth multiplexer. As described above, when executing the vector pipeline instruction, the multiplexer 21 of FIG. 3 is controlled so that the first pipeline register 15 holds the data by itself, and when executing another instruction, selects the program memory 11. Controlled.

Finally, the first multiplexer control signal generator 52 has the second multiplexer control signal generator 53.
And a first multiplexer control circuit 61. The first multiplexer control circuit 61 outputs the first multiplexer control signal under the control of the second multiplexer control signal and the address branch control signal output from the decoder 12. As described above, when executing the vector pipeline instruction, the multiplexer 18 of FIG. 3 is controlled so that the program counter register 17 holds the data by itself, and when executing another instruction, the incrementer 19 or the branch address control circuit 20. Is controlled to select.

FIG. 6 is a block diagram showing an address generator in the processor of the present invention. In FIG. 6, the address generator 2 includes an address calculator 67, a cycle counter 68, and an end determination circuit 69. Then, during execution of the vector pipeline instruction, during the period when the activation signal given from the vector instruction control circuit 13 of the program control circuit 1 is asserted, the address arithmetic unit 67 sequentially controls the addresses of the data memory 3 under the control of the activation signal. Occur. At the same time, the cycle counter 68 counts the number of addresses generated by the address calculator 67 by the activation signal. Then, when the value of the cycle counter 68 reaches a constant value, the end determination circuit 69 is controlled to output an end signal. Here, the address calculator 67 can be configured by a conventional pointer, a two-dimensional address calculator, or the like.
Further, when executing an instruction other than the vector pipeline instruction, the address calculator 67 uses the program control circuit 1
The address is generated one by one under the control of the control signals of the respective units of the decoder 12.

With the above configuration, when executing the conventional instruction, the execution unit 5 selects the function and data path of a single operation so that the execution is completed in one cycle.

When executing the vector pipeline instruction, the first and second source data memories 33 and 3 are used.
4 is input to the arithmetic unit block 40 and the output of the arithmetic unit block 40 is input to the third destination data memory 35 or the accumulator 42. It

Then, the first and second address generators 30 and 31 for generating the addresses of the first and second source data memories 33 and 34 from the program control circuit 1 are connected to the first and second address generators 30 and 31, respectively.
The first address generators 30 and 31 start generating a series of addresses in a preset sequence independently of the program control circuit 1 by the activation signal of the above. Then, according to the generated address, a series of vector data is read from the source data memories 33 and 34, and the arithmetic unit block 40 continuously performs arithmetic processing.

The vector data output from the arithmetic unit block 40 is used by the program control circuit 1 to generate the address of the destination data memory 35.
The address generator 32 is supplied with the third activation signal with a delay of the number of pipeline delay stages of the execution unit 5, that is, the number of cycles obtained by subtracting 1 from the number of pipeline stages of the execution unit 5, thereby providing the third activation signal. Address generator 32
Starts to generate a series of addresses and continuously writes to the destination data memory 35, or the program control circuit 1 causes the accumulator 42 to execute unit 5.
The accumulator 42 starts accumulating when the fourth activation signal is given after a delay of the number of pipeline delay stages.

As described above, the vector pipeline operation is executed in a plurality of cycles, and the first address generator 3
When 0 finishes generating the preset number of addresses,
The program control circuit 1 is controlled so as to return an end signal.

Here, the source data memory 33, 34,
Although the embodiment has been described in which the destination data memory is 35, it goes without saying that these combinations are arbitrary. Although the end signal is output from the first address generator 30, there is no problem even if another address generator generates the end signal.

7 and 8 are timing charts for explaining the operation of the processor of the present invention. The processor of the present invention is
This is a processor that implements a vector pipeline instruction in addition to the conventional instruction set, and is composed of the program control circuit of FIG. 3 and the execution unit of FIG. The vector pipeline instruction reads the vector data stored in the source data memory, calculates the vector data with the arithmetic unit, and writes the output vector data into the destination data memory. It has a second type of vector pipeline instruction for accumulating the output vector data of the arithmetic unit in the accumulator 10.

The first type of vector pipeline instruction executes the pipeline parallel operation shown in (Equation 1),
The second type of vector pipeline instruction executes the pipeline parallel operation shown in (Equation 2). FIG. 7 is an operation timing chart for explaining the operation of the first type vector pipeline instruction, and FIG. 8 is an operation timing chart for explaining the operation of the first type vector pipeline instruction.

FIG. 7 shows a state in which the program control circuit 1 of FIG. 3 sequentially reads the instructions stored in the program memory 11 and the execution unit 5 of FIG. 4 is execution-controlled. In FIG. 7, the instruction at address N is a vector pipeline instruction for executing the pipeline processing according to the present invention.
Also in FIG. 7, it is assumed that the instructions other than the instruction at address N are conventional single operation instructions and are not branch instructions.

Here, the vector pipeline instruction at the address N reads the vector data stored in the first data memory 33 and the second data memory 34, and the first pipeline arithmetic unit 38 calculates the vector data. However, it is assumed that the first type of vector pipeline instruction instructs to write the output vector data to the third data memory 35. The vector data is a vector of m elements.

FIG. 7 shows at which address the instruction is processed in each cycle in the instruction read cycle, the decode cycle and the instruction execution cycle. Also, the operation timing of each unit when the vector pipeline instruction is executed is shown. When the program control circuit 1 of FIG. 3 sequentially controls the execution of a program, the operation when executing a conventional single operation instruction, that is, ALU operation, multiplication, 1 data load, store, etc. It is the same. That is, the program memory 1
The instruction read cycle from 1, the decode cycle, and the instruction execution cycle are sequentially performed in the pipeline. Then, the execution unit 5 of FIG. 4 selects the data path by the data path selection circuit 43 according to the content of the single operation instruction decoded by the decoder 12, and the execution is completed in one cycle.
The instruction execution cycles at addresses N-2 and N-1 shown in FIG. 7 show the execution of the conventional single operation instruction.

Next, the operation when the vector pipeline instruction is read and executed will be described. First, the execution unit 5 inputs the outputs of the source data memories 33 and 34 to the first pipeline arithmetic unit 38 by the data path selection circuit 43 according to the contents of the vector pipeline instruction decoded by the decoder 12. , The data path is selected so that the output of the arithmetic unit 38 is input to the destination data memory 35. Further, here, the first pipeline arithmetic unit 38 is realized by a two-stage pipeline, but there is no particular limitation. For image processing, by integrating a filter arithmetic unit, a dedicated pipeline arithmetic unit such as a cosine transformer (DCT), etc., the performance is dramatically increased, for example, 10 to 100 times, depending on the degree of pipeline parallelism. improves.

When the vector pipeline instruction at the address N is decoded by the decoder 12, the vector instruction control circuit 13 outputs a multiplexer control signal as shown in FIG. As a result, the first multiplexer 18 selects the output of the program counter register 17 and controls the program counter register 17 to hold the data by itself. Further, the second multiplexer 21 selects the output of the first pipeline register 15 and controls the pipeline register 15 to hold the data by itself. Therefore, as shown in FIG. 7, control is performed so that the vector pipeline instruction at address N can be continuously executed in a plurality of cycles.

When the vector pipeline instruction at the address N is decoded by the decoder 12, the vector instruction control circuit 13 of the program control circuit 1 sends the first and second address generators 30 and 31 a first instruction. , A second activation signal is applied to each of the address generators 30 and 31.
Is independent of the program control circuit 1 and generates m addresses in a continuous cycle in a preset sequence. The first and second data memories 33 and 34 continuously generate the addresses as shown in FIG. The m memory read cycle is started. Here, the two-stage pipeline arithmetic unit 38 is continuously connected to the arithmetic operation 1 and the arithmetic operation 2 in FIG.
Pipeline arithmetic processing is performed as shown in (3), and the vector data output from the pipeline arithmetic unit 38 is input to the third data memory 35.

Here, the program control circuit 1 delays the third address generator 32 for generating the address of the destination data memory 35 by the pipeline delay stage number of the execution unit, that is, the operation 1, the operation 2, and the write operation. When the third activation signal is applied with a delay of three cycles, the third address generator 32 starts to generate a series of addresses, and the addresses are continuously written in the destination data memory 35. The program control circuit 1 has deciphered that the current vector pipeline instruction at address N is a memory read, and is a four-stage pipeline process of operation 1, operation 2, and memory write, and using this information, The third activation signal to the address generator 32 can be given three cycles later than the first and second activation signals to the first and second address generators 30 and 31.

By performing the above control,
As shown in FIG. 7, a four-stage pipeline process of memory read, operation 1, operation 2, and memory write can be continuously executed for each of m pieces of vector data.

When the first address generator 30 finishes generating m addresses, the program control circuit 1
A first end signal is given to. When the vector instruction control circuit 13 receives the first end signal, according to the processing contents of the vector pipeline instruction at the address N,
As shown in FIG. 7, the control signals of the multiplexer 18 and the multiplexer 21 are released with a certain cycle delay, the self-holding of the program counter register 17 and the self-holding of the pipeline register 15 are released, and the program counter 10 and The pipeline register 15 is restarted.

Here, the constant cycle is two cycles in the vector pipeline instruction at the address N. As described above, the program control circuit 1 deciphers that the current vector pipeline instruction at address N is a memory read, and is a four-stage pipeline process of operation 1, operation 2, and memory write. The information can be used to release the control signal with a fixed or two cycle delay after receiving the first end signal. The reason why the number of cycles is set to 2 instead of 3 is that even if the multiplexer control signal is released, the instruction at address N is executed one cycle later due to the pipeline configuration of the program control circuit, so the control signal is released one cycle earlier To do.

After the program counter 10 and the pipeline register 15 are restarted, all the pipeline cycles relating to the vector pipeline instruction at the address N are completed, and the instruction after the vector pipeline instruction at the address N, that is, N Instructions at addresses +1, N + 2, N + 3 are sequentially executed as in the conventional processor.

As described above, according to the embodiment of the present invention, the pipeline parallel operation shown in (Equation 1) can be realized by one vector pipeline instruction, and the performance is 10 to 100 depending on the pipeline parallel degree. Doubled and dramatically improved. Also, the number of steps in the program memory can be compressed to one step.

FIG. 8 is a timing diagram illustrating another operation of the processor of the present invention. Hereinafter, another operation of the processor of the present invention will be described with reference to FIG. 8 is different from FIG. 7 in that the vector pipeline instruction at the address N is the second data memory 34 and the third data memory 35.
The vector data stored in the
Is a vector pipeline instruction of the second type instructing that the output vector data is accumulated by the accumulator 42. FIG. 8 also shows the address of the instruction processed in each cycle in the instruction read cycle, the decode cycle, and the instruction execution cycle. Also, the operation timing of each unit when the vector pipeline instruction is executed is shown.

When the program control circuit 1 of FIG. 3 sequentially controls the execution of a program, the conventional single operation instruction, that is, the ALU operation, the multiplication, the load of 1 data, the store, etc., are executed conventionally. Similar to the processor of. The instruction execution cycle at addresses N-2 and N-1 shown in FIG. 8 shows the execution of the conventional single operation instruction.

Next, the operation when the vector pipeline instruction is read and executed will be described. First, the execution unit 5 inputs the outputs of the source data memories 34 and 35 to the ALU 36 and accumulates the outputs of the ALU 36 by the data path selection circuit 43 according to the contents of the vector pipeline instruction decoded by the decoder 12. A data path is selected for input to the instrument 42. Here, the ALU 36 is selected as the arithmetic unit, but there is no particular limitation.

When the vector pipeline instruction at the address N is decoded by the decoder 12, the vector instruction control circuit 13 outputs a multiplexer control signal as shown in FIG. As a result, the first multiplexer 18 selects the output of the program counter register 17 and controls the program counter register 17 to hold the data by itself. Further, the second multiplexer 21 selects the output of the first pipeline register 15 and controls the pipeline register 15 to hold the data by itself. Therefore, as shown in FIG. 8, control is performed so that the vector pipeline instruction at address N can be continuously executed in a plurality of cycles.

When the vector pipeline instruction at the address N is decoded by the decoder 12, the vector instruction control circuit 13 of the program control circuit 1 outputs the second instruction to the second and third address generators 31 and 32. The third and third activation signals are respectively applied, and the address generators 31 and 32 independently of the program control circuit 1 generate m addresses in consecutive cycles in a preset sequence. As shown in FIG. 8, m memory reading cycles are continuously started from the data memories 34 and 35 of FIG. Then, here, the ALU 36 performs arithmetic processing, and the vector data output from the ALU 36 is input to the accumulator 42. Here, the program control circuit 1 gives a fourth activation signal to the accumulator 42 after a delay of the number of pipeline delay stages of the execution unit, that is, after a delay of two cycles of ALU operation and accumulation. By this, the accumulation is started.

The program control circuit 1 has deciphered that the current vector pipeline instruction at address N is a memory read and is a three-stage pipeline process of ALU operation and accumulation, and using this information, The fourth activation signal to the accumulator 42 is sent to the second and third address generators 31 and 32,
It can be given two cycles later than the third activation signal.

By performing the above control,
As shown in FIG. 8, three-stage pipeline processing of memory reading, ALU calculation, and accumulation can be continuously executed for each of m pieces of vector data. When the second address generator 31 finishes generating m addresses, it gives a second end signal to the program control circuit 1.

When the vector instruction control circuit 13 receives the second end signal, it delays by a certain cycle as shown in FIG. 8 according to the processing contents of the vector pipeline instruction at the address N, and The control signals of the multiplexer 18 and the multiplexer 21 are released, the self-holding of the program counter register 17 and the self-holding of the pipeline register 15 are released, and the program counter 10 and the pipeline register 15 are restarted.
Here, the fixed cycle is one cycle in the vector pipeline instruction at the address N. As described above, the program control circuit 1 deciphers that the current vector pipeline instruction at address N is a memory read, and is a three-stage pipeline process of ALU operation and accumulation, and uses this information. Thus, the control signal can be released after a certain cycle, that is, one cycle, after receiving the first end signal. The reason why one cycle is set instead of two cycles is that even if the control signal is released, the control signal is released earlier by one cycle because the instruction at address N is executed by one cycle due to the pipeline configuration of the program control circuit. It is a thing.

After the program counter 10 and the pipeline register 15 are restarted, all the pipeline cycles relating to the vector pipeline instruction at address N are completed, and the instruction after the vector pipeline instruction at address N, that is, N Instructions at addresses +1, N + 2, N + 3 are sequentially executed as in the conventional processor.

As described above, according to the embodiment of the present invention, the pipeline parallel operation shown in (Equation 2) can be realized by one vector pipeline instruction, and the performance is 10 to 100 depending on the pipeline parallel degree. Doubled and dramatically improved. Also, the number of steps in the program memory can be compressed to one step.

In the embodiment of the present invention shown in FIGS. 1 to 8, each of the address generators generates the address of the rectangular area of the two-dimensional data proposed by the present inventor. -By providing the function of the two-dimensional address generator described in No. 41424 (Two-dimensional address generator and its control method), it is very efficient for the one having a two-dimensional data structure such as image data. It becomes possible to process well.

[0061]

As described above, according to the present invention, it is possible to realize a processor in which a specific instruction for pipeline processing is additionally mounted on the conventional instruction set for instructing a single operation. When a specific instruction is read, the processor of the present invention sequentially reads the contents of the data memory in a preset order, and performs pipeline processing for executing an operation cycle in parallel with the read cycle,
The output of the arithmetic unit is sequentially written in parallel to another data memory or is sequentially accumulated by an accumulator. Then, when the calculation of the set number of data is completed, the instruction is executed sequentially from the instruction of the step next to the specific instruction as in the conventional processor.

When performing the operation represented by (Equation 1) or (Equation 2) that frequently appears in signal processing, a comparison is made between the specific instruction of the processor of the present invention and the case of executing it using the instruction set of the conventional processor. Then, although depending on the arithmetic function, the speedup of the processing cycle of about 10 to 100 times can be achieved. Further, although the program step also depends on the amount of data to be handled at the same time, a large capacity is required and a large amount of program memory is consumed by one instruction, that is, one step.

[Brief description of drawings]

FIG. 1 is a block diagram showing a concept of a processor of the present invention.

FIG. 2 is a timing diagram illustrating the operation of the processor of the present invention.

FIG. 3 is a block diagram showing a program control circuit of the processor of the present invention.

FIG. 4 is a block diagram showing an execution unit of a processor of the present invention.

FIG. 5 is a block diagram showing a vector instruction control circuit in the processor of the present invention.

FIG. 6 is a block diagram showing an address generator in the processor of the present invention.

FIG. 7 is a timing diagram illustrating the operation of the processor of the present invention.

FIG. 8 is a timing diagram illustrating another operation of the processor of the present invention.

[Explanation of symbols]

 1 Program Control Circuit 2 Address Generator 3 Data Memory 4 Data Processing Circuit 5 Execution Unit 10 Program Counter 11 Program Memory 12 Decoder 13 Vector Instruction Control Circuit

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Akihiko Otani 1006 Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. (72) Hisamu Kodama 1006 Kadoma, Kadoma City, Osaka Matsushita Electric Industrial Co., Ltd. 72) Inventor Kiyoshi Okamoto 1006 Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd.

Claims (4)

[Claims] 1. A program controlled processor comprising a data processing circuit for implementing a plurality of instructions including a vector pipeline instruction and executing a pipeline operation based on the vector pipeline instruction. And a program counter and a decoder, and when the vector pipeline instruction is read from the program memory and then decoded by the decoder, the program counter is stopped and an activation signal is output to output the vector pipe. A program control circuit that controls the operation of the data processing circuit according to the contents of the line command, and an address is continuously generated according to a preset sequence based on the activation signal to generate a preset number of addresses. When finished, give the end signal An address generator for outputting to a RAM control circuit; and a data memory for outputting data stored in advance at the generated address based on the address generated by the address generator, the data processing circuit, The pipeline operation is executed in accordance with the control of the program control circuit based on the data output from the data memory, and the program control circuit outputs the vector pipeline instruction after a predetermined cycle from the time when the end signal is received. A program-controlled processor which detects the end of the pipeline operation based on the instruction and sequentially executes the instructions following the vector pipeline instruction. 2. The program control circuit further includes a branch address control circuit for generating a branch address based on the decoding result of the decoder, and each of the program control circuits in the program control circuit based on the decoding result of the decoder and the end signal. A vector instruction control circuit for controlling the operation of the circuit; an instruction register circuit for temporarily storing data output from the program memory based on a second control signal output from the vector instruction control circuit; And a first pipeline register for temporarily storing the data output from the data memory and the data processing circuit, and the program counter temporarily stores the address output to the program memory. And the program counter register to be stored in An incrementer that outputs the address by incrementing the address output by 1 by 1 for each cycle of the operation clock, and an incrementer from the branch address control circuit based on a first control signal output from the vector instruction control circuit. A first multiplexer for selecting one of an output, an output of the program counter register and an output of the incrementer and outputting the selected address to the program memory via the program counter register, The instruction register circuit includes a second pipeline register for temporarily storing data output to the decoder, an output of the program memory based on a second control signal output from the vector instruction control circuit, and the output of the program memory. Select one of the outputs of the second pipeline register to select the second A second multiplexer for outputting to the decoder via the pipeline register of the vector instruction control circuit, the vector instruction control circuit, when the vector pipeline instruction is decoded by the decoder, the activation signal to the address generator. And the first multiplexer selects and outputs the output of the program counter register so that the program counter register self-holds data, and the second multiplexer controls the second multiplexer to output the data. The output of the pipeline register is selected and output to control the second pipeline register so as to hold data by itself, so that each instruction of the vector pipeline instruction is executed continuously. Control, and then when the end signal is received from the address generator. After a predetermined cycle, when the end of the pipeline operation based on the vector pipeline instruction is detected, the control of the first and second multiplexers is released, whereby the self-holding of the program counter register is performed. And releasing the self-holding of the second pipeline register,
2. The program-controlled processor according to claim 1, wherein the instructions following the vector pipeline instructions are sequentially executed. 3. The address generator comprises a source memory address generator and a destination memory address generator, and the vector instruction control circuit outputs the vector pipeline instruction decoded by the decoder. Based on the vector command signal
The start signal of the source memory address generator is set and output to the source memory address generator, and the start signal of the source memory address generator is generated based on the end signal output from the address generator. A first start-up signal generator for resetting, a first shift register having a predetermined number of stages of delay circuits for delaying and outputting the vector instruction signal, and the decoder for decoding the vector pipeline instruction. Selecting one of the outputs of the delay circuits of the first shift register based on the resulting vector instruction type signal and outputting the selected signal to the destination memory address generator. A second start signal generating section including a multiplexer of 3 and a delay circuit having a predetermined number of stages and delaying the end signal. A second shift register that outputs the signal and one of the outputs of the delay circuits of the second shift register based on the vector instruction type signal, and selects the selected signal as a delay end signal. Based on a fourth multiplexer for outputting, the second control signal is set based on the vector command signal and output to the second multiplexer, and based on the delay end signal output from the fourth multiplexer. A first control signal generation unit including a signal generator that resets the second control signal; the second control signal; and an address branch control signal that is a result of decoding the address branch instruction by the decoder. And a second control signal generating section for generating the first control signal and outputting the first control signal to the first multiplexer. Motomeko 2 program controlled processor according. 4. The address generator counts the number of addresses generated by the address calculator, which continuously generates addresses based on the start signal and outputs the addresses to the data memory. 3. A cycle counter, and an end determination circuit that outputs the end signal to the program control circuit when the number of addresses counted by the cycle counter reaches a predetermined value. Alternatively, the program-controlled processor according to item 3. A processor characterized by being controlled as follows.