JPH0562707B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION BACKGROUND OF THE INVENTION This invention relates generally to gamma cameras, and more particularly to circuits for synchronizing the output of multiple photomultiplier tubes for processing as a group. .

One characteristic that limits nuclear imaging systems is the dead time, i.e., the system is processing one scintillation event and is therefore unable to process subsequent scintillation events. It's time. Here, one "scintillation event" is:
It refers to one scintillation (flash) generated within a scintillator crystal. A common way to reduce dead time in a system is to provide redundancy with buffers in the slowest parts of the processing cycle, such as energy or spatial correction functions. There are also other ways to speed up the signal processing function and thus reduce system dead time. However, even with these methods, there are practical constraints that limit the speed at which scintillation event counts can be received and processed. This practical limit is generally believed to be about 200,000 counts per second for a typical ordinary gamma camera. One reason for this limitation is that the photomultiplier tube array can only receive or process one scintillation event at a time.
That is, if two scintillation events occur at or near the same time at different locations elsewhere in the array, then at least one scintillation event, and possibly both scintillation events, are not used. . Usually, the first scintillation event that occurs or the first scintillation event that is processed is used, and the other is not used.

It may happen that both valid scintillation events are invalidated because they are interpreted as one scintillation event. For example, if two scintillation events occur simultaneously at different locations, they may be interpreted as one brighter scintillation event at a location intermediate between the two. In this case, the window level discrimination invalidates the scintillation event because its brightness exceeds the allowed threshold level. Therefore, removing two counts in this manner is significant in reducing the counting speed of the system.

Another undesirable phenomenon that may occur is the interpretation of two bad scintillation events as one valid scintillation event. For example, a pair of weak scintillation events at different locations is interpreted as a brighter scintillation event at an intermediate location, and this brighter scintillation event falls within a given brightness window. If there is, it will be erroneously counted as a valid scintillation event, thereby reducing the accuracy of the process.

OBJECTS OF THE INVENTION It is therefore an object of the invention to provide a nuclear camera system capable of increasing the counting speed and for which purpose it is possible to provide a nuclear camera system with multiple scintillations occurring simultaneously or nearly simultaneously. Providing means for making it possible to accept events, i.e. to distinguish in the nuclear camera separate scintillation events occurring at or near the same time and distinguishing them as separate scintillation events; It is an object of the present invention to provide a means that allows the validity of scintillation events that have occurred to be determined more accurately and reliably. In other words, means are provided to enable more accurately and reliably measuring the output of the photomultiplier tube for application as a signal for use in forming an image display in the nuclear camera. The purpose is to

These and other objects, features and advantages will be better understood from the following description of the drawings.

SUMMARY OF THE INVENTION The present invention comprises a plurality of light sensing devices (typically photomultiplier tubes) that generate output signals in response to and representative of scintillation events occurring within adjacently disposed scintillator crystals. ) in a scintillation camera circuit having a cluster (an assembly of regularly arranged light sensing devices), the signal is transmitted to the light sensing devices directly surrounding at least one light sensing device in the cluster. transceiver means for transmitting and receiving, the transmitting and receiving means for transmitting and receiving signals from the surrounding light sensing device when the at least one light sensing device records a scintillation event; means for determining a scintillation event to be valid if the at least one light sensing device emits a signal indicating that the at least one light sensing device also recorded a scintillation event when the scintillation event is recorded; Output signal processing means are provided for processing a photosensing device output signal representative of a determined scintillation event. The output signals representing the scintillation event from the light sensing devices in the class are simultaneously, or synchronized, to a conventional processing circuit (the matrix circuit of the gamma camera) for indicating the location and magnitude of the scintillation event. is applied. For this synchronization or simultaneous application, use is made of the output signal of the transceiver means, in particular of the at least one light-sensing device. This output signal is also used to determine the validity of the scintillation event, as described above. By using the output signals of two or more light sensing devices in a cluster as described above, the validity of a scintillation event can be accurately and reliably determined.

To describe this invention more specifically, a communication line is provided between each photomultiplier tube of the gamma camera and each of the photomultiplier tubes surrounding it; A bidirectional switching circuit is provided between the surrounding photomultiplier tubes, and this configuration allows each photomultiplier tube to notify its adjacent photomultiplier tubes when it acquires a scintillation event. I'll do what I can. It also determines when neighboring photomultiplier tubes receive equally valid scintillation events and responds accordingly.
Logic means are then provided for closing the bidirectional switching means. All photomultiplier tubes interconnected in this way are treated as one cluster, and one
One photomultiplier tube acts as a regulator for the entire cluster. Measurements are taken at each photomultiplier in the classer and their outputs are summed and compared to a discrimination window to determine whether their signals should be processed. If the sum falls within the specified window,
The regulator photomultiplier circuit serves to simultaneously apply, or synchronize, the outputs of the individual photomultiplier tubes to an Anger-type signal processing circuit for display. In this way, both the counting speed and the effectiveness determination speed can be increased. That is, since more than one cluster can exist at any given time, valid scintillation events occurring simultaneously can be handled. This is a routine that was previously impossible. Furthermore, instead of treating the output of each photomultiplier tube independently as in conventional devices, they are treated in combination with other outputs in the cluster, making the effectiveness determination and measurement functions more reliable. And it can be done accurately.

In one embodiment, the validity determination logic validates the signal from a particular photomultiplier by identifying at least two adjacent photomultipliers from surrounding photomultipliers that have acquired the signal at that time. Requires the presence of a multiplier tube. Means are also provided for disabling signals that have been active for more than a predetermined period of time.

Preferred embodiments will be described below with reference to the drawings, but various other modifications can be made within the scope of the invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a hexagonal photomultiplier tube N and surrounding photomultiplier tubes N1 to N6. these are,
A gamma camera having a scintillator crystal (not shown) and a plurality of photomultiplier tubes positioned adjacent to the crystal to receive scintillation events generated by the crystal in response to incident radiation. are arranged in the same way as before. Of course, such an arrangement would normally include more photomultiplier tubes, but these are not shown in this example for simplicity.

Unlike the configuration of a normal gamma camera,
Each of the photomultiplier tubes N to N6 is interconnected with each adjacent photomultiplier tube by a communication circuit as shown. That is, although FIG. 1 shows that the photomultiplier tube N is individually connected to each adjacent photomultiplier tube N1-N6, each photomultiplier tube N1-N6 is also connected to its respective one. It should be noted that the array is connected in the same manner to its neighbors, and that such connections are made throughout the array.
Of course, the outermost photomultiplier tube is connected to only three or four photomultiplier tubes, whereas the inner photomultiplier tubes are connected to six.
The communication circuitry is identical for each inner photomultiplier tube and is shown in detail in FIG. 1A.

It is shown schematically in FIG. 1A that the photomultiplier tube N has output and input communication circuits. A portion of circuitry 18 is provided that collects signals from adjacent photomultiplier tubes when they record a scintillation event. for example,
When photomultiplier tube N2 records a scintillation event, this information is transmitted to circuit 1 via input line 19.
By sending a signal to 8, the photomultiplier tube N is informed. Similarly, each of the other photomultiplier tubes N1
and N3-N6 have input lines connected to circuit 18 as shown. Similarly, the output bus 21
is provided, and when a photomultiplier tube N records a scintillation event, it sends that information to an adjacent photomultiplier tube. Although each output line from the output bus is shown in FIG. 1A, only one output line for optical power multiplier N2 is labeled with the reference numeral "22".

A communication line was set up to inform each photomultiplier tube of the status of its neighboring photomultiplier tubes, but also to inform the neighboring photomultiplier tubes of each photomultiplier tube for further processing in a coordinated manner. Means is provided for transferring the output signal to. For example, assume that photomultiplier tube N is a regulator and controls the processing of associated signals, and further assume that photomultiplier tubes N1-N6 each recorded one scintillation event. The validity of the signal from each photomultiplier tube is then determined locally by circuitry to be described later. Assuming that the scintillation event is determined to be valid, the local busbar 23 and the local busbars associated with other surrounding photomultiplier tubes are closed to send their respective output signals to adjacent photomultiplier tubes. I'll do what I can. The local bus bar 23 is the first
As shown in more detail in the figure, it has a two-way switch that performs an AND function. That is, to close the circuit, for example, each of photomultiplier tubes N and N2 must close its switch to allow the output signal to pass from photomultiplier tube N2 to photomultiplier tube N. Similarly, photomultiplier tubes N1 and N3
-N6 closes its switch and sends its output to the adjacent photomultiplier tube. One photomultiplier in the cluster is connected to the processing circuitry via the detector busbar shown in FIG. 1A (indicated by dashed lines in FIG. 1). The method will be explained in more detail later.

It will be appreciated in FIG. 1 that the detector bus bar is coupled to each individual photomultiplier tube, and that any photomultiplier tube can be connected to the processing circuitry. In this respect, for any one scintillation event, any one photomultiplier tube can become a controlling photomultiplier tube that adjusts the output of an adjacent photomultiplier tube. Please be careful. Furthermore, although this specification describes a cluster as being composed of seven photomultiplier tubes, the cluster may be composed of a greater or lesser number (but at least three) of photomultiplier tubes. Please be aware that it is okay to do so. The point to note here is that for any one scintillation event, one photomultiplier tube synchronizes the outputs of all photomultiplier tubes related to this scintillation event, and subsequent processing and It is to be connected to the main detector bus for display purposes.

Figures 1B and 1C illustrate two configurations that can be used as bidirectional switches for use in the configurations described above. In FIG. 1B, a pair of open collector NAND gates 15, 20 are connected as shown to create a digital two-way latch connection between adjacent photomultiplier tubes. In the embodiment of FIG. 1C, a pair of switches 25, 30 are connected to provide either analog or digital interconnection.

FIG. 2 shows the circuit of the system for one photomultiplier tube N. It should be appreciated that each of the other photomultiplier tubes also has a corresponding circuit.
The analog signal from the photomultiplier tube N is applied via line 24 to a conventional preamplifier 26. The output of preamplifier 26 is applied to an integrator or peak detector 27 and processed in the conventional manner, but in response to logic control circuitry to be described below. The output of prior amplifier 26 is also applied to signal detection and mitigation circuit 28 . This circuit acts as a buffer, preserving the integrity of the preamplifier output for subsequent measurements while deriving a digital signal for use in the validation process.

Signal detection and mitigation circuit 28 is shown in detail in FIG. The output from preamplifier 326 is applied to the positive terminal of voltage follower operational amplifier 327 with diode 328 and feedback loop 329. A capacitor 331 and a resistor 332 are provided at the output to set a relaxation time constant having a predetermined value. This circuit acts as a peak detector and its output is applied to the positive terminal of comparator 333. A threshold voltage V _T is applied to the negative terminal of this comparator. At its output, a digital signal is generated representing that a scintillation event has been detected by the associated photomultiplier, in this case photomultiplier N, this signal being hereinafter referred to as "SGNL".

As shown in FIG. 2, the signal SGNL is applied to adjacent photomultiplier tubes N1-N6 as previously described. Similarly, the digital signals from the adjacent photomultiplier tubes N1-N6 are the signals output from the photomultiplier tube N.
Signal validity judgment and prohibition logic circuit 3 along with SGNL
4.

Signal validation and inhibit logic circuit 34 is shown in detail in FIG. 4 and includes a plurality of AND gates G1-G6. Each gate receives input from an adjacent pair of photomultipliers N1-N6 in the cluster. for example,
In order for gate G1 to turn on, it is necessary to receive signals from both photomultiplier tubes N1 and N6. The outputs of gates G1-G6 are applied to OR gate G7, whose output is applied to AND gate G8. The signal number and signal SGNL from relaxation circuit 28 are also applied to AND gate G8. Therefore, a signal SGNL is generated by a scintillation event from the photomultiplier tube N, and an associated signal is also generated from any two adjacent photomultiplier tubes in the cluster surrounding the photomultiplier tube N. If so, the signal SGNL is asserted and gate G8 has a positive output indicating this. However, as shown in FIG. 4, there is an inhibit terminal at the input of gate G8, which may still invalidate the signal SGNL.

The inhibit circuit at the bottom of FIG.
It is established to invalidate the This can occur when the preamplifier becomes saturated, or when the photomultiplier tube fails, or when, for example, a pair of scintillation events are recorded very close together. OR gate G9 is an arbitrary one photomultiplier tube N
It turns on when it receives a signal from 1-N6. The output of gate G9 is applied to three parallel paths leading to AND gate G10. One input line 434 is a directly connected line, another line 436 has a delay τ ₁ added, and a third line 437
A time window M ₁ is added to . If all three inputs are high, the output of gate G10 is high.
, which inhibits the output of gate G8 and invalidates the signal SGNL. As can be seen in FIG. 4A, time window M ₁ is such that point C is "low", but the signal from the first adjacent photomultiplier tube (in this case appearing at point A) is "low". high (but delayed by the gate delay shown). The signal SGNL of the photomultiplier tube in question becomes "high" when it is close to matching the signal from the first adjacent photomultiplier tube (<M ₁ ), and the two adjacent photomultiplier tubes operate simultaneously. If the condition is recorded, ie, the "2N" signal is "high", the output of gate G8 is "high" for the remainder of the validation period (M ₁ ).
The delay τ ₁ is included in line 436 to ensure that time window M ₁ has sufficient time to operate. The logic circuit of FIG. 4 operates as shown in the typical time diagram shown in FIG. 4B. In this example,
Signals are output from photomultiplier tubes N3, N2 and N in this order. M ₁ by the signal of photomultiplier tube N3
becomes "high", ie the time window begins. 2
When the signal of the th adjacent photomultiplier tube N2 is received, both the "2N" and "valid" signals go "high". It can be seen that at the end of time window M ₁ all three photomultiplier tube signals remain. Therefore, at this time the "inhibit" signal is initiated or goes "high" and the "enable" signal goes "low" disabling this process. When the signal of photomultiplier tube N3 drops to zero, the "2N" signal also drops to zero. When the signals of both photomultiplier tubes N3 and N2 drop to zero, the "inhibit" signal also drops to zero, Reset the circuit.

Returning again to FIG. 2, assuming that gate G8 has a positive output, indicating that signal "SGNL" is valid, a positive "valid" signal is transmitted via line 38 to the timing shown in FIG. and is applied to the control circuit 39. The portion of the timing and control circuit 39 that is active at this time is shown in FIG.

When a "valid" signal pulse is applied to latched flip-flop 541, a "connect" signal is applied to the local busbar switches, indicated generally at 42 in FIG. N1
-N6 is connected to local energy bus 42 (using the circuit of Figure 1C). The outputs of the individual photomultiplier tubes are thus summed for window discrimination, which will be explained later.

The flip-flop 541 in FIG.
It also outputs a ``sampling'' signal for . This signal acts to release the signal measurement circuit from the clamp condition and initiates the signal measurement process by conventional methods such as integration, peak detection, etc. When the measurement is completed,
The “ready” signal is the timing and control circuit 39
(Figure 2). The "ready" signal is
To operate the logic circuit of FIG. 5, a signal is first applied to time delay circuit 544. The time delay circuit generates a "request to send" signal, which is applied as will now be described. A "ready" signal is applied to start a timeout monostable or timer 546 to reset the system's internal logic. The output of timer 546 is “send request”
The signal is applied to an AND gate G11, and the output of this gate is applied to a NOR gate G12. Also applied to NOR gate G12 is the output of AND gate G13, which has inverted inputs for both the signal SGNL and the "ready" signal. The third input to NOR gate G12 is the "reset" signal, which is applied to the inverting terminal. This logic circuit can be activated by (1) a “reset” signal or (2)
(3) because the signal SGNL and the "ready signal" both go "low", or (3) because the "request to send" signal goes "high" and "time out";
It acts to reset flip-flop 541 and ultimately timer 546.

The time diagram of FIG. 5A shows that immediately after the ``signal'' is received, the ``valid'' signal goes ``high,'' and the ``sampling'' and ``connect'' signals also go ``high.''
When the sample has been taken and the measurements taken, it is “ready”
A signal is sent back which causes the "time out" signal to go "high". After a delay of a predetermined time τ ₂ , the “request to send” signal goes “high”. When the ``reset'' signal goes ``low,'' all other signals go ``low,'' thus resetting the circuit for the next signal.

The "send request" signal obtained by the circuit of FIG. 5 is applied as shown in FIGS. 2 and 6. The "request to transmit" signal indicates that the synchronized transmission of information from the interconnected photomultiplier tubes is now ready. This signal is generated by all photomultiplier tubes in the detector that have reached their proper state. The bus-related logic circuits shown in FIG. 6 (or FIG. (only one) is guaranteed to take on the role of synchronizing. X+ and X
-, Y+ and Y- and the respective resistors 47, 48, 49, 51 are of conventional type, to which the output signal of the photomultiplier tube is applied. will be explained later.

FIG. 6 shows bus acquisition and contention logic that controls access to the bus. A ``request to send'' signal is applied to AND gate G14, whose output clocks flip-flop 652, which generates a ``busy'' signal at its output. The ``busy'' signal is applied to a logic inverter 653 with an open collector output, which acts to connect the ``node busy'' line through resistor R to ground. This reduces the normal voltage V _B on the "node busy" line to 0.6 V _B as shown in Figure 6A. This causes the "node busy" line to become "busy" to all other interface circuits. That is, as long as the ``busy'' signal from flip-flop 652 remains, the voltage on the ``node busy'' line remains at 0.6V _B and no other circuitry can access this line. To explain what happens in other circuits, the "send request" signal is sent to gate G14 in Figure 6.
is applied, the “node in use” line is “in use”
Assume that Comparator 654 has a threshold higher than 0.6V _B (eg, 0.8V _B ), at which time the output will be "low" and AND gate G14 will not turn on. However, as soon as the ``node busy'' line becomes ``free,'' its voltage returns to V _B , which exceeds the 0.8 V _B threshold of comparator 654.
The output of the comparator 654 becomes "high" and the gate G1
4 is turned on, clocking flip-flop 652 and generating the ``busy'' signal. The voltage levels of the comparator and the "node busy" line, respectively, are shown in FIG. 6A.

In addition to generating a "busy" condition, means are also provided to handle a race condition in which two circuits act to acquire the bus at the same time. This tends to occur in circuits that are in the same interconnected cluster for a single scintillation event. When this happens, the voltage on the "node busy" line drops to 0.3V _B , which is lower than the match threshold of comparator 656, 0.5V _B (see Figure 6A), thus causing inverting NOR gate G15 to drop. The flip-flop 652 is reset via the The same thing happens with any other circuit that produces a match condition. When the flip-flop is reset, the voltage on the ``node busy'' line is raised again to level _VB , attempting to clock the flip-flop a second time. Since the thresholds and propagation delays of the circuits are often different due to the inherent properties of the circuit, only one photomultiplier circuit will fail on the second attempt to access the "node busy" line. considered to have priority.
However, if one wishes to avoid the risk of sustained oscillations until timeout occurs, bus race conditions may cause the entire cluster of photomultiplier circuits to "reset"; Alternatively, a somewhat more complex "daisy-chain" scheme may be used, as shown in FIG. 7 and discussed below.

Returning to the "in use" signal from the flip-flop 652, this is used as the "permit" signal (see FIGS. 2 and 6) by the energy window detection circuit 5.
5. The energy window detection circuit 55 is of the conventional type and has an upper and lower range, and if the measured energy does not fall within that range, no further processing is performed. As can be seen in Figure 2, the energy to be measured is the local energy bus 4
It is the sum of the outputs of all photomultiplier tubes N1-N6 appearing in 3. It is important to note that since this bus is a current summing line, there is only one photomultiplier circuit in the cluster that measures the common activity of the local energy bus 43 at a particular time.

As seen in FIG. 6, a "busy" signal is also applied to delay circuit 657 and then to AND gate G16. Therefore, after the "busy" signal is continuously activated for a predetermined period of time τ ₃ or more,
The window measurement results are applied to gate G16. When the sum of the outputs from all photomultiplier tubes is determined to be outside the expected energy window(s), the "window" signal goes "low". At this time, the logic inverter 658 "rejects" the "acknowledge" line ACK.
Generates signal REJ, which is AND gate G18
to reset all circuits in the cluster (all with ``send'' set to ``high'').

As previously mentioned, the "grant" signal causes the energy window detection circuit 55 to measure the sum of the outputs of adjacent interconnected photomultiplier tubes within a particular cluster. The second function of the window discriminator is to initiate the delivery of energy to the Anger matrix. For this reason, the local energy bus 43 is first brought to ground potential. This state is the "sending" comparator 59
(Fig. 2). This comparator has previously received a "send request" signal via voltage divider 61 at its positive terminal. This "send" comparator is activated in each photomultiplier associated with the cluster, so that each comparator connects the output of its respective photomultiplier to the amplifier node X+ via matrix resistors 47-51. , X-, Y+, Y-. For example, the output of the photomultiplier tube N at this time is from the measuring device 27 to the line 6
0, Anga node X+ via switch 62,
Sent to X-, Y+, Y-. Similarly, the outputs of photomultiplier tubes N1-N6 are similarly applied to the anger nodes via their respective switching devices. In this way, the processing circuit of the control photomultiplier tube, in the case of the above embodiment photomultiplier tube N, first measures the combined output of the adjacent photomultiplier tubes, and
Making sure that the sum is within an acceptable threshold (window), we then synchronize the application of these outputs to the anga node by bringing the local energy bus to zero potential. The processing circuitry then operates in the normal manner to display the scintillation event on a CRT or the like. Once the signal processing circuit has acquired the signal, a "confirm" signal is applied via NOR gate G12 and AND gate G18 to "send".
All photomultiplier tube circuits with active signals are reset.

In FIGS. 7 and 7A, a so-called "daisy chain" scheme is shown for a coincident situation in which two circuits attempt to acquire the bus bar at the same time. A plurality of such circuits are connected in series in a ring, and the inhibit output of one circuit is connected to the inhibit input of the next circuit. It is not necessary for each photomultiplier tube to have such circuitry, and because of the nature of the validation logic, one photomultiplier tube acts as a "send synchronizer" that is representative of all photomultiplier tubes. It is necessary to be chosen. For example, if the validity criterion requires that at least two adjacent photomultiplier tubes receive matched signals as mentioned above, then 1/2 of the total number of photomultiplier tubes 3 only needs to be equipped with the circuit of FIG. 7 so as to act as a send synchronizer. It is preferable to make the connection order irregular rather than systematic.

As can be seen in FIG. 7, each circuit includes a flip-flop 763 which controls the continuation of the daisy chain.
have. Initially, all flip-flops are reset except one, which cuts the ring in one place. The "inhibit" output signal from the circuit in which the flip-flop is set is always high, indicating that the following circuit has the highest priority when a bus access match occurs.

Assuming that a similar circuit with a flip-flop set is directly below the circuit of FIG. 7, and that the inhibit (input) of FIG. 7 is "high" (not active), then the circuit of FIG. works as follows.
“Send request” is applied to AND gate G21,
Assuming the node busy signal applied to OR gate G22 is ``high'', the output of AND gate G21 is ``high'', providing a ``permit'' signal. This "high" signal is applied to inverter 764, causing the "node busy" line to go "low".
become a state. OR Gate G22 is ("send request"
persists and the ``inhibit'' input is ``high'' (not activated)), it latches onto the ``allow'' state. The inverted output of AND gate G21 is applied to AND gate G23 along with the "high" signal from the "inhibit" input. The output of AND gate G23 is applied to OR gate G24,
This OR gate will remain active unless flip-flop 763 is set to indicate the end of the chain.
Set the inhibition output signal to "low". The signal path from the ``inhibit'' input through gates G23, G24 to the ``inhibit'' output assures other circuitry that the inhibit signal is passed through the rest of the ring.

The "grant" signal indicates to the logic circuits that the bus has been acquired, and the node busy signal acts to prevent all circuits from acquiring the bus until the bus is released. This release is accomplished by applying the "ACK" signal to AND gate G26 through inverter 766, resetting the logic circuitry. The "ACK" signal also acts to latch the "grant" signal of flip-flop 763, so that the last circuit to synchronize the sending of data is the one with the lowest priority on the next sending cycle. Reconfigure the ring as shown. Such a chain configuration means that within a very short period of time (at most the propagation delay time for the inhibit signal to pass through the entire chain), the first circuit in the chain will again have priority and send the inhibit signal back up the ring. The busbar is obtained by transmitting a signal to the circuit and thus ensuring that all "grant" signals of the circuits downstream in the ring are set to zero by gate 21. As previously mentioned, the "inhibit" signal passes through the circuit via gates G21, G23 until the end of the ring.

Referring to FIG. 7A, the left-hand portion shows the timing for the photomultiplier tube circuit for synchronizing the information output in question. The sending cycle is
ACK signal becomes "low" and "end" signal becomes "high"
Complete by indicating that the circuit in question is now terminating the ring. 7th A
The right part of the diagram shows the timing of the signal to the circuit in question when another higher priority photomultiplier circuit in the ring is synchronizing the output of information from the cluster of photomultiplier tubes. show. The bus control signals represented by the ``node busy'' and ACK signals act as before, but there are inhibit inputs and outputs that give higher priority to active circuits. The sending cycle ends when the ACK signal is issued. The ACK signal now resets the ``end'' signal of the circuit in question (since this circuit was not a synchronization circuit). Therefore, the ring end position moves to the last activated synchronization circuit.

"Allow" for lower priority circuits to be very short
I would like to mention that there may be a signal, and if necessary, this will be suppressed by appropriate means. However, since the ``grant'' signal does not last very long, the ``reset'' signal is not received when the ACK signal is issued. Therefore, no means is provided to suppress such short signals.

Although the invention has been described with particular embodiments and examples, other modifications will occur to those skilled in the art in light of the foregoing description. It is therefore to be understood that within the scope of the appended claims, the invention may be practiced otherwise than as specifically described.

[Brief explanation of the drawing]

1 and 1A are schematic configuration diagrams showing a plurality of photomultiplier tubes and mutual communication circuits therein used in a preferred embodiment of the present invention, and FIGS. 1B and 1C are digital and analog type photomultiplier tubes, respectively. FIG. 2 is a circuit diagram of the validity determination and synchronization portion of the present invention; FIG. 3 is a circuit diagram of the signal detection and mitigation circuit in the circuit of FIG. 2; FIG. 4 is a logic circuit diagram of a signal validity determination and inhibition circuit, FIGS. 4A and 4B are time diagrams in the circuit of FIG. 4, and FIG. 5 is a logic circuit diagram of a timing and control circuit used in the present invention. Figure 5A is a time diagram of the circuit of Figure 5, Figure 6 is a circuit diagram of a bus acquisition and competition logic circuit of one embodiment used in this invention, and Figure 6A is a comparison of the circuit of Figure 6. 7 is a waveform diagram showing voltage levels, FIG. 7 is a circuit diagram of a bus acquisition and contention logic circuit of another embodiment used in the present invention, and FIG. 7A is a time diagram in the circuit of FIG. 7.

Claims (1)

Claims: 1. Receiving photons from an adjacently disposed scintillator crystal in response to a scintillation event occurring in the crystal and processing it to indicate the location and magnitude of the scintillation event. A scintillation camera circuit having a plurality of light sensing devices arranged in a cluster that generates an output signal indicative of a scintillation event, wherein one of the plurality of light sensing devices in said cluster
transceiver means for transmitting a signal to and receiving signals from other light sensing devices directly surrounding the one light sensing device in the cluster when a light sensing device records a scintillation event; determining means for determining the validity of the scintillation event, the at least one other light sensing device of the plurality of light sensing devices in the cluster also determining the effectiveness of the scintillation event; determining means for determining that the scintillation event is valid when there is at least one output signal indicating that the scintillation event has been recorded; 1. A scintillation camera circuit comprising: output signal processing means for processing an output signal representing the signal. 2. A scintillation camera circuit as claimed in claim 1, wherein said transmitting and receiving means includes circuitry for generating a digital signal in response to an analog output from a light sensing device. 3. A scintillation camera circuit according to claim 1, wherein the determining means includes a plurality of logic gates. 4. In the scintillation camera circuit according to any one of claims 1 to 3, the determining means is configured to select one of the other light sensing devices surrounding the one light sensing device. A scintillation camera circuit comprising means for disabling said scintillation event when a received signal persists for a predetermined threshold period. 5. The scintillation camera circuit according to claim 1, wherein the output signal processing means comprises a plurality of nodes arranged in a matrix so that output signals representing the scintillation event are applied; A scintillation camera circuit including synchronization means for applying output signals from a plurality of light sensing devices to the nodes of said matrix substantially simultaneously. 6. In the scintillation camera circuit as set forth in claim 1, the transmitting/receiving means is extended from the one light-sensing device to each of the other surrounding light-sensing devices, one pair at a time. a plurality of conductive wires, a plurality of busbars extending one from the one light sensing device to each of the other lightsensing devices, and attached to each of the busbars;
selectively closing a busbar circuit between the associated other light sensing device and the one light sensing device to produce an output signal indicative of a scintillation event when the other light sensing device responds to the scintillation event; and bidirectional communication means for transmitting a signal to said one light sensing device. 7. A scintillation camera circuit according to any one of claims 1 to 6, wherein the light sensing device is comprised of a photomultiplier tube. 8. In the scintillation camera circuit according to claim 6, the transmitting/receiving means is further attached to the plurality of conductive wires,
sending a signal to the other light sensing device when the one light sensing device responds to a scintillation event; and transmitting a signal from the other light sensing device when the other light sensing device responds to a scintillation event. A scintillation camera circuit having means for receiving. 9. In the scintillation camera circuit according to claim 6, the output signal processing means is further provided in association with the plurality of busbars, and the output signal processing means is further provided in association with the plurality of busbars, and A scintillation camera circuit having summing means for summing signals representative of scintillation events. 10. A scintillation camera circuit according to claim 6, wherein said bidirectional communication means includes means for communicating a signal representative of a scintillation event from said one light sensing device to said other light sensing device. Scintillation camera circuit. 11. A scintillation camera circuit according to any one of claims 1 to 10, wherein said other light sensing device is adjacent to said one light sensing device. 12. A scintillation camera circuit according to claim 11, wherein the determining means generates an output signal only when at least one pair of adjacent light sensing devices is displaying an associated scintillation event. scintillation camera circuit. 13. In the scintillation camera circuit according to claim 5, the output signal processing means further outputs the outputs of the one light sensing device and the other light sensing device to the nodes of the plurality of matrices. a scintillation camera circuit including switching means selectively adjacent to the scintillation camera circuit; 14. In the scintillation camera circuit as set forth in claim 13, the switching means and the synchronization means include a multiplex switch device attached to each of the one light sensing device and the other light sensing device. , a common actuating means for closing a multiple switch device in response to a control signal from said light sensing device. 15. In the scintillation camera circuit according to claim 1, the output signal processing means selectively adds the outputs of the other light sensing devices and adds the resulting sum to at least one schedule. A scintillation camera circuit that includes a summing circuit that compares the output signal to a threshold value to determine whether the output signal should be processed.