JPH0562842B2 - - Google Patents
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- Publication number
- JPH0562842B2 JPH0562842B2 JP60090327A JP9032785A JPH0562842B2 JP H0562842 B2 JPH0562842 B2 JP H0562842B2 JP 60090327 A JP60090327 A JP 60090327A JP 9032785 A JP9032785 A JP 9032785A JP H0562842 B2 JPH0562842 B2 JP H0562842B2
- Authority
- JP
- Japan
- Prior art keywords
- voltage
- capacitor
- circuit
- bias
- resistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- Amplifiers (AREA)
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、増幅器に動作点を設定し、あるい
は帰還回路に特定の直流レベルを設定するバイア
ス回路に係り、特に、バイアス電圧の立ち上がり
スピードの高速化に関する。[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a bias circuit that sets an operating point in an amplifier or a specific DC level in a feedback circuit, and particularly relates to a bias circuit that sets an operating point in an amplifier or a specific DC level in a feedback circuit. Regarding speeding up.
第4図に示すように、バイアス回路は、電源電
圧VCCを分圧抵抗2,4で分圧し、半導体集積回
路で構成される場合、その分圧点に形成された端
子6に電源電圧VCCに含まれるノイズやリツプル
成分を除去するためのコンデンサ8が接続され、
抵抗2,4の分圧点に発生させた特定の電圧、た
とえば、電圧VCC/2は、低インピーダンス化を
図るための増幅利得Gvを持たないバツフア増幅
器10を介して出力端子12から取り出され、図
示してない増幅器の入力バイアスや増幅器の帰還
回路の直流レベルを設定する帰還バイアスに供給
される。
As shown in FIG. 4, the bias circuit divides the power supply voltage V CC with voltage dividing resistors 2 and 4, and when it is configured with a semiconductor integrated circuit, the power supply voltage V CC is applied to the terminal 6 formed at the voltage dividing point. A capacitor 8 is connected to remove noise and ripple components included in CC .
A specific voltage, for example, voltage V CC /2, generated at the voltage dividing point of the resistors 2 and 4 is taken out from the output terminal 12 via a buffer amplifier 10 that does not have an amplification gain Gv to achieve low impedance. , is supplied to an input bias of an amplifier (not shown) and a feedback bias for setting the DC level of a feedback circuit of the amplifier.
このようなバイアス回路に付加されているコン
デンサ8に容量の大きなものを用いて抵抗との時
定数を大きくすれば、電源からのノイズやリツプ
ル成分の除去比を高くできるが、その分だけ電源
の投入からバイアス電圧出力の立ち上がりに時間
がかかり、定常電圧値への到達が遅くなる欠点が
ある。
If the capacitor 8 added to such a bias circuit has a large capacitance and the time constant with the resistor is increased, the rejection ratio of noise and ripple components from the power supply can be increased, but the power supply will be reduced accordingly. There is a drawback that it takes time for the bias voltage output to rise after power-on, and that the steady voltage value is delayed.
そこで、この発明は、電源からのノイズやリツ
プル成分の除去比を向上させるとともに、バイア
ス電圧出力の立ち上がりを急速化しようとするも
のである。 Therefore, the present invention aims to improve the rejection ratio of noise and ripple components from the power supply and to speed up the rise of the bias voltage output.
この発明のバイアス回路は、特定の電圧を分圧
する分圧抵抗の接続点にコンデンサが接続されて
一定のバイアス電圧を発生し、このバイアス電圧
を増幅器に与えるバイアス回路であつて、前記電
圧の印加に応じて瞬時に立ち上がるとともに前記
コンデンサが定常電圧に充電されたときその充電
電圧より一定電圧だけ低い分圧点を持つ抵抗分圧
回路と、この抵抗分圧回路の前記分圧点の電圧と
前記コンデンサの電圧とを比較する比較器と、電
源ラインと前記コンデンサとの間に抵抗を介して
接続されて前記コンデンサの充電電圧が前記抵抗
分圧回路の前記分圧点より低いとき、前記比較器
が発生する出力をベースに受けて導通し、前記コ
ンデンサに前記抵抗を介して充電電流を流すトラ
ンジスタとを備えたことを特徴とする。
The bias circuit of the present invention is a bias circuit in which a capacitor is connected to a connection point of a voltage dividing resistor that divides a specific voltage to generate a constant bias voltage, and this bias voltage is applied to an amplifier. a resistive voltage divider circuit having a voltage dividing point that instantaneously rises in response to the current voltage and is lower than the charging voltage by a constant voltage when the capacitor is charged to a steady voltage; a comparator that compares the voltage of the capacitor with the voltage of the capacitor; and a comparator connected through a resistor between the power supply line and the capacitor, when the charging voltage of the capacitor is lower than the voltage division point of the resistor voltage divider circuit. and a transistor that receives an output generated by the capacitor at its base and becomes conductive, and causes a charging current to flow through the resistor to the capacitor.
したがつて、この発明は、電源の投入時、コン
デンサにプリチヤージ回路によつて充電電流を補
充し、コンデンサの充電時間を短縮することによ
つて、バイアス電圧出力の立ち上がりを速めてい
る。
Therefore, in the present invention, when the power is turned on, the capacitor is supplemented with charging current by the precharge circuit, thereby shortening the charging time of the capacitor, thereby speeding up the rise of the bias voltage output.
したがつて、コンデンサの容量を大きくでき、
電源からのノイズおよびリツプル成分の除去比を
高めることが可能である。 Therefore, the capacity of the capacitor can be increased,
It is possible to increase the rejection ratio of noise and ripple components from the power supply.
以下、この発明の実施例を図面を参照して詳細
に説明する。
Embodiments of the present invention will be described in detail below with reference to the drawings.
第1実施例
第1図はこの発明のバイアス回路の実施例を示
し、第4図に示すバイアス回路と同一部分には同
一符号を付してある。First Embodiment FIG. 1 shows an embodiment of the bias circuit of the present invention, and the same parts as the bias circuit shown in FIG. 4 are given the same reference numerals.
第1図に示すように、このバイアス回路には、
電源の投入時、すなわち、電圧VCCの印加時、コ
ンデンサ8を急速に充電するプリチヤージ回路2
0が付加されている。このプリチヤージ回路20
には、ダイオード22を介在させた分圧抵抗2
4,26によつて分圧回路が構成されている。 As shown in Figure 1, this bias circuit includes:
A precharge circuit 2 that rapidly charges the capacitor 8 when the power is turned on, that is, when the voltage V CC is applied.
0 is added. This precharge circuit 20
is a voltage dividing resistor 2 with a diode 22 interposed therebetween.
4 and 26 constitute a voltage dividing circuit.
この実施例の場合、分圧抵抗2,4の抵抗値
R2,R4は、電源電圧VCCの中点バイアスを得るた
め、R2=R4に設定されており、分圧抵抗24,
26の抵抗値R24,R26も同様に、R24=R26に設
定されている。このとき、ダイオード22のカソ
ードにおける分圧点電位は、分圧抵抗2,4の分
圧点電位に比較し、定常状態ではダイオード22
の順方向降下VFの1/2の値(VF/2)だけ低い値
に設定されている。 In this example, the resistance values of voltage dividing resistors 2 and 4 are
R 2 and R 4 are set to R 2 = R 4 in order to obtain the midpoint bias of the power supply voltage V CC , and the voltage dividing resistor 24,
Similarly, the resistance values R 24 and R 26 of No. 26 are set to R 24 =R 26 . At this time, the voltage dividing point potential at the cathode of the diode 22 is compared with the voltage dividing point potential of the voltage dividing resistors 2 and 4, and in a steady state, the voltage dividing point potential at the cathode of the diode 22 is
The value is set to a value that is 1/2 (V F /2) lower than the forward drop V F of .
これら分圧点電位を比較するため、電圧比較器
28がダイオード22のカソード側を反転入力端
子(−)側にして設置され、その比較出力はコン
デンサ8に充電電流を流すためのスイツチング素
子としてのトランジスタ30のベースに加えられ
ている。トランジスタ30のコレクタ側には、電
流制限用抵抗32が挿入され、その導通時にはコ
ンデンサ8にプリチヤージ電流が流れるようにな
つている。 In order to compare these voltage division point potentials, a voltage comparator 28 is installed with the cathode side of the diode 22 facing the inverting input terminal (-), and its comparison output is used as a switching element to flow charging current to the capacitor 8. It is added to the base of transistor 30. A current limiting resistor 32 is inserted on the collector side of the transistor 30, and when the resistor 32 is conductive, a precharge current flows through the capacitor 8.
以上の構成に基づき、その動作を第2図を参照
して説明する。 Based on the above configuration, its operation will be explained with reference to FIG.
電源の投入時、C点の電位は瞬時に立ち上が
り、一方、B点の電位はコンデンサ8が未充電で
あるため、C点の電位より低くなり、比較器28
の出力はL(低電位)レベルとなる。この出力に
よつて、トランジスタ30が導通し、電源電圧
VCCから抵抗32を通じてコンデンサ8にプリチ
ヤージ電流が流れる。 When the power is turned on, the potential at point C rises instantaneously, while the potential at point B becomes lower than the potential at point C because capacitor 8 is not charged, and comparator 28
The output becomes L (low potential) level. This output makes the transistor 30 conductive and the power supply voltage
A precharge current flows from V CC to capacitor 8 through resistor 32 .
この結果、第2図に示す充電特性Xの区間aの
ように、コンデンサ8は急速に充電される。この
充電は、B点の電位VBが、中点電位VCC/2より
ダイオード22の順方向降下VFの1/2だけ低い電
位VC(=VCC/2−VF/2)に到達するまで行わ
れる。 As a result, the capacitor 8 is rapidly charged as shown in section a of the charging characteristic X shown in FIG. In this charging, the potential V B at point B becomes a potential V C (=V CC /2−V F /2) lower than the midpoint potential V CC /2 by 1/2 of the forward drop V F of the diode 22. is carried out until it is reached.
また、このとき、トランジスタ30の導通によ
つて、抵抗2に対して抵抗32が並列に接続され
ることになり、たとえば、抵抗2の抵抗値をR2、
抵抗32の抵抗値をR32とし、R2>R32のとき、
R2・R32/(R2+R32)<R32となり、コンデンサ
8の充電電流をより大きくすることができ、B点
の電位VBは、中点電位VCC/2よりダイオード2
2の順方向降下VFの1/2、すなわちVF/2だけ低
い電位VCに速やかに到達させることができる。 Further, at this time, due to the conduction of the transistor 30, the resistor 32 is connected in parallel to the resistor 2, and for example, the resistance value of the resistor 2 is set to R 2 ,
Let the resistance value of the resistor 32 be R 32 , and when R 2 > R 32 ,
R 2 · R 32 / (R 2 + R 32 ) < R 32 , and the charging current of the capacitor 8 can be made larger, and the potential V B at point B is smaller than the midpoint potential V CC /2.
It is possible to quickly reach a potential V C lower by 1/2 of the forward drop V F of 2, that is, V F /2.
この結果、比較器28の出力はH(高電位)レ
ベルとなり、トランジスタ30は非導通状態とな
り、この時点からコンデンサ8の充電は、抵抗2
のみを介して行われ、第2図の充電特性Xの区間
bの充電となる。この場合、コンデンサ8は予め
プリチヤージされるので、定常電圧に移行する時
間はその分だけ速くなり、プリチヤージ回路20
を設置しないで抵抗2のみで充電する場合(第2
図の充電特性Yによる充電電圧Vy)に比較し、
定常のバイアス電圧出力に移行する全時間はtPだ
け速くなる。 As a result, the output of the comparator 28 becomes H (high potential) level, the transistor 30 becomes non-conductive, and from this point on, the charging of the capacitor 8 is stopped by the resistor 2.
The charging is carried out only through the charging section b of the charging characteristic X in FIG. 2. In this case, since the capacitor 8 is precharged in advance, the time for transition to a steady voltage is correspondingly faster, and the precharge circuit 20
When charging only with resistor 2 without installing
Compared to the charging voltage V y ) due to the charging characteristic Y shown in the figure,
The total time to transition to steady bias voltage output is faster by tP .
なお、第2図に示す充電特性Xの区間a,bの
電圧をそれぞれVxa,Vxbとすると、これらは、
次の通りである。 Note that if the voltages in sections a and b of charging characteristic X shown in FIG. 2 are V xa and V xb , respectively, these are as follows.
It is as follows.
Vxa≒R4/(R0+R4)・VCC
・{1−exp(−t/C8・R0)} ……(1)
Vxb≒Vy=R4/(R2+R4)・VCC
・{1−exp(−t/C8・R2)} ……(2)
ただし、式(1)、(2)において、R4は抵抗4の抵
抗値、C8はコンデンサ8の容量、R0は抵抗2,
32の並列回路の合成抵抗値{=R2・R32/(R2
+R32)}である。 V xa ≒ R 4 / (R 0 + R 4 )・V CC・{1−exp(−t/C 8・R 0 )} ……(1) V xb ≒V y =R 4 /(R 2 +R 4 )・V CC・{1−exp(−t/C 8・R 2 )} ……(2) However, in formulas (1) and (2), R 4 is the resistance value of resistor 4, and C 8 is the capacitor. 8 capacitance, R 0 is resistance 2,
Combined resistance value of 32 parallel circuits {=R 2・R 32 /(R 2
+R 32 )}.
第2実施例
第3図はプリチヤージ回路20の具体的な実施
例を示しており、電圧比較器28はトランジスタ
34,36、抵抗38および定電流源40からな
る差動増幅型比較器で構成され、前記トランジス
タ30は、トランジスタ42,44および抵抗4
6からなるダーリントン接続回路で構成されてい
る。第3図において、B,Cは、第2図のB点、
C点に対応する。したがつて、このような回路に
よれば、極めて簡単な構成で、バイアス電圧出力
の立ち上がりの急速化が容易に実現される。Second Embodiment FIG. 3 shows a specific embodiment of the precharge circuit 20, in which the voltage comparator 28 is composed of a differential amplification type comparator consisting of transistors 34, 36, a resistor 38, and a constant current source 40. , the transistor 30 includes transistors 42, 44 and a resistor 4.
It consists of 6 Darlington connection circuits. In Figure 3, B and C are point B in Figure 2,
Corresponds to point C. Therefore, according to such a circuit, rapid rise of the bias voltage output can be easily realized with an extremely simple configuration.
〔発明の効果〕
以上説明したように、この発明によれば、電源
の投入時、コンデンサにプリチヤージ回路によつ
て充電電流を補充し、コンデンサの充電時間を短
縮してバイアス電圧出力の立ち上がりを高速化で
きることにより次のような効果が得られる。[Effects of the Invention] As described above, according to the present invention, when the power is turned on, the precharge circuit replenishes the capacitor with charging current, shortens the capacitor charging time, and speeds up the rise of the bias voltage output. By being able to do this, the following effects can be obtained.
(a) 電源の投入と同時的に安定したバイアス電圧
出力を得ることができる。(a) A stable bias voltage output can be obtained at the same time as the power is turned on.
(b) プリチヤージによつて電圧の立ち上がりを速
くすることができるので、コンデンサの容量や
分圧抵抗の抵抗値を大きくすることができ、電
源からのノイズおよびリツプル成分の除去比を
高めることができる。(b) Precharging can speed up the voltage rise, making it possible to increase the capacitance of the capacitor and the resistance value of the voltage dividing resistor, increasing the rejection ratio of noise and ripple components from the power supply. .
第1図はこの発明のバイアス回路の実施例を示
す回路図、第2図はその充電特性を示すグラフ、
第3図はプリチヤージ回路の具体的な回路構成を
示す回路図、第4図は従来のバイアス回路を示す
回路図である。
2,4,24,26……分圧抵抗、8……コン
デンサ、20……プリチヤージ回路、22……ダ
イオード、28……電圧比較器、30……トラン
ジスタ、32……抵抗。
FIG. 1 is a circuit diagram showing an embodiment of the bias circuit of the present invention, and FIG. 2 is a graph showing its charging characteristics.
FIG. 3 is a circuit diagram showing a specific circuit configuration of the precharge circuit, and FIG. 4 is a circuit diagram showing a conventional bias circuit. 2, 4, 24, 26... voltage dividing resistor, 8... capacitor, 20... precharge circuit, 22... diode, 28... voltage comparator, 30... transistor, 32... resistor.
Claims (1)
ンデンサが接続されて一定のバイアス電圧を発生
し、このバイアス電圧を増幅器に与えるバイアス
回路であつて、 前記電圧の印加に応じて瞬時に立ち上がるとと
もに前記コンデンサが定常電圧に充電されたとき
その充電電圧より一定電圧だけ低い分圧点を持つ
抵抗分圧回路と、 この抵抗分圧回路の前記分圧点の電圧と前記コ
ンデンサの電圧とを比較する比較器と、 電源ラインと前記コンデンサとの間に抵抗を介
して接続されて前記コンデンサの充電電圧が前記
抵抗分圧回路の前記分圧点より低いとき、前記比
較器が発生する出力をベースに受けて導通し、前
記コンデンサに前記抵抗を介して充電電流を流す
トランジスタと、 を備えたことを特徴とするバイアス回路。[Claims] 1. A bias circuit that generates a constant bias voltage by connecting a capacitor to a connection point of a voltage dividing resistor that divides a specific voltage, and applies this bias voltage to an amplifier, the circuit comprising: a resistive voltage divider circuit having a voltage dividing point that instantaneously rises in response to the voltage and is lower by a constant voltage than the charging voltage when the capacitor is charged to a steady voltage; a comparator that compares the voltage of the capacitor with a voltage of the capacitor; 1. A bias circuit comprising: a transistor that receives an output generated by the transistor at its base, conducts it, and supplies a charging current to the capacitor through the resistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60090327A JPS61248604A (en) | 1985-04-26 | 1985-04-26 | Bias circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60090327A JPS61248604A (en) | 1985-04-26 | 1985-04-26 | Bias circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61248604A JPS61248604A (en) | 1986-11-05 |
| JPH0562842B2 true JPH0562842B2 (en) | 1993-09-09 |
Family
ID=13995428
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60090327A Granted JPS61248604A (en) | 1985-04-26 | 1985-04-26 | Bias circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61248604A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005107515A (en) * | 2003-09-12 | 2005-04-21 | Semiconductor Energy Lab Co Ltd | Semiconductor device and driving method thereof |
| JP2008203890A (en) * | 2003-09-12 | 2008-09-04 | Semiconductor Energy Lab Co Ltd | Semiconductor device and electronic equipment |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007158584A (en) * | 2005-12-02 | 2007-06-21 | Matsushita Electric Ind Co Ltd | Semiconductor integrated circuit |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5721885A (en) * | 1980-07-15 | 1982-02-04 | Fujitsu Ltd | Method of forming printed board circuit with jumpber wire |
-
1985
- 1985-04-26 JP JP60090327A patent/JPS61248604A/en active Granted
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005107515A (en) * | 2003-09-12 | 2005-04-21 | Semiconductor Energy Lab Co Ltd | Semiconductor device and driving method thereof |
| JP2008203890A (en) * | 2003-09-12 | 2008-09-04 | Semiconductor Energy Lab Co Ltd | Semiconductor device and electronic equipment |
| US8350785B2 (en) | 2003-09-12 | 2013-01-08 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and driving method of the same |
| US9385704B2 (en) | 2003-09-12 | 2016-07-05 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and driving method of the same |
| US9825624B2 (en) | 2003-09-12 | 2017-11-21 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and driving method of the same |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS61248604A (en) | 1986-11-05 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |