JPH056343B2 - - Google Patents
Info
- Publication number
- JPH056343B2 JPH056343B2 JP59188102A JP18810284A JPH056343B2 JP H056343 B2 JPH056343 B2 JP H056343B2 JP 59188102 A JP59188102 A JP 59188102A JP 18810284 A JP18810284 A JP 18810284A JP H056343 B2 JPH056343 B2 JP H056343B2
- Authority
- JP
- Japan
- Prior art keywords
- diffusion region
- oxide film
- region
- emitter
- conductivity type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000009792 diffusion process Methods 0.000 claims description 57
- 238000010438 heat treatment Methods 0.000 claims description 19
- 239000004065 semiconductor Substances 0.000 claims description 14
- 239000000758 substrate Substances 0.000 claims description 11
- 238000004519 manufacturing process Methods 0.000 claims description 9
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical group [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 8
- 239000012535 impurity Substances 0.000 claims description 8
- 229910052698 phosphorus Inorganic materials 0.000 claims description 8
- 239000011574 phosphorus Substances 0.000 claims description 8
- 238000000034 method Methods 0.000 claims description 6
- 230000002093 peripheral effect Effects 0.000 claims description 5
- 238000000605 extraction Methods 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 238000007796 conventional method Methods 0.000 description 4
- 238000002474 experimental method Methods 0.000 description 3
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 230000001590 oxidative effect Effects 0.000 description 2
- 238000004886 process control Methods 0.000 description 2
- 230000003321 amplification Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- RLOWWWKZYUNIDI-UHFFFAOYSA-N phosphinic chloride Chemical compound ClP=O RLOWWWKZYUNIDI-UHFFFAOYSA-N 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
- H10D62/133—Emitter regions of BJTs
Landscapes
- Bipolar Transistors (AREA)
Description
【発明の詳細な説明】
（産業上の利用分野）
この発明は半導体装置の製造方法に関し、詳し
くは、バイポーラトランジスタの製造方法に関す
る。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a bipolar transistor.
（従来の技術）
従来の方法により製造されたバイポーラトラン
ジスタを第３図に示し、図中１はＰ型シリコン基
板、２はN+埋め込み層、３はＮ型エピタキシヤ
ル層、４はP+分離領域、５はP+ベース拡散領域、
６はN+エミツタ拡散領域、７はN+コレクタ取り
出し領域である。(Prior Art) A bipolar transistor manufactured by a conventional method is shown in Fig. 3, in which 1 is a P-type silicon substrate, 2 is an N + buried layer, 3 is an N-type epitaxial layer, and 4 is a P + isolation layer. area, 5 is P + base diffusion area,
6 is an N + emitter diffusion region, and 7 is an N + collector extraction region.
（発明が解決しようとする問題点）
この第３図に示すように、従来の方法でバイポ
ーラトランジスタを製造すると、拡散の拡がりに
よりエミツタ拡散領域６の底面角部（円ａで囲つ
て示す）が丸くなる。その結果、エミツタ面積が
小さいトランジスタにおいては、hFE（エミツタ接
地静順方向電流増幅率）のエミツタ面積依存性が
理想曲線より大きく傾くという現象がみられる。(Problems to be Solved by the Invention) As shown in FIG. 3, when a bipolar transistor is manufactured by the conventional method, the bottom corner of the emitter diffusion region 6 (encircled by a circle a) is Become round. As a result, in transistors with small emitter areas, a phenomenon is observed in which the dependence of h FE (grounded emitter static forward current amplification factor) on emitter area slopes more than the ideal curve.
第４図は、hFEのエミツタ面積依存性を実験し
た結果を示す。いま、エミツタ面積AEOの時のhFE
をβ0（IE＝I0＝一定）とすると、エミツタ面積を変
化させると、β／β0は
１＋αlog（AE／AEO） …(1)
となる。ここで、αは拡散の深さによる係数で、
エミツタ拡散領域の底面角部に丸みがなく、底面
が平坦な場合はα≒０であり、その結果、β／β0
は１（理想値：第４図破線）となる。一方、従来
の方法でバイポーラトランジスタを製造した場合
は、エミツタ拡散領域の底面角部の丸みによりα
は0.3〜0.7の値をとる。その結果、β／β0は、第
４図に実線で示すように、理想値（第４図破線）
より大きく傾くことになる。 Figure 4 shows the results of an experiment on the emitter area dependence of h FE . Now, h FE when emitter area A EO
Assuming that β 0 (I E =I 0 =constant), when the emitter area is changed, β/β 0 becomes 1+αlog(A E /A EO )...(1). Here, α is a coefficient depending on the depth of diffusion,
If the bottom corner of the emitter diffusion region has no roundness and the bottom is flat, α≈0, and as a result, β/β 0
is 1 (ideal value: broken line in Figure 4). On the other hand, when bipolar transistors are manufactured using the conventional method, α
takes a value between 0.3 and 0.7. As a result, β/β 0 is the ideal value (dashed line in Figure 4), as shown by the solid line in Figure 4.
It will tilt more.
そして、hFEのエミツタ面積依存性が理想曲線
より大きく傾く結果、エミツタ面積の違いにより
hFEを考慮してパターン設計を行わなければなら
ないというパターン設計上の問題点が生じる。ま
た、極端にエミツタ面積の違うトランジスタを形
成する場合は、エミツタ面積の大なるトランジス
タのhFEを最適値に設定すると、面積小なるトラ
ンジスタのhFEが小さくなりすぎて回路動作しな
いから、両者が適当な値をとるようにするため、
プロセスコントロールが難しくなつてしまう。 As a result of the emitter area dependence of h FE becoming more sloped than the ideal curve, due to the difference in the emitter area,
A problem arises in pattern design that the pattern must be designed taking h FE into consideration. Also, when forming transistors with extremely different emitter areas, if you set the h FE of the transistor with a large emitter area to the optimal value, the h FE of the transistor with a small emitter area will become too small and the circuit will not operate. In order to take an appropriate value,
Process control becomes difficult.
そこで、この発明では、hFEのエミツタ面積依
存性の少ない、エミツタ拡散領域底面の平坦なバ
イポーラトランジスタを形成する。 Therefore, in the present invention, a bipolar transistor with a flat bottom surface of the emitter diffusion region and which has less dependence of h FE on the emitter area is formed.
（問題点を解決するための手段）
この発明では、リンドープとウエツトO2雰囲
気での第１の熱処理により、ベース拡散領域内に
エミツタ拡散領域を形成するとともに、その表面
に酸化膜を形成した後、その酸化膜に、エミツタ
拡散領域より小さく開孔部を形成した上で、酸化
性雰囲気で第２の熱処理を行なう。(Means for Solving the Problems) In the present invention, an emitter diffusion region is formed in the base diffusion region by phosphorus doping and a first heat treatment in a wet O 2 atmosphere, and an oxide film is formed on the surface of the emitter diffusion region. After forming an opening smaller than the emitter diffusion region in the oxide film, a second heat treatment is performed in an oxidizing atmosphere.
（作用）
すると、表面に酸化膜が残存するエミツタ拡散
領域の周辺部は、前記酸化膜形成時にその酸化膜
にとり込まれたリンの再拡散により通常より深く
拡散される。その結果、丸味を帯びたエミツタ拡
散領域の底面角部は角型に修正され、底面は平坦
となる。(Function) Then, the periphery of the emitter diffusion region where the oxide film remains on the surface is diffused deeper than usual due to rediffusion of phosphorus taken into the oxide film when the oxide film was formed. As a result, the bottom corner of the rounded emitter diffusion region is modified to a square shape, and the bottom surface becomes flat.
（実施例）
この発明の一実施例を第１図を参照して説明す
る。(Example) An example of the present invention will be described with reference to FIG.
第１図Ａは、Ｐ型シリコン基板１１にN+埋め
込み層１２を形成した後、Ｐ型シリコン基板１１
上にＮ型エピタキシヤル層１３を形成し、そのエ
ピタキシヤル層１３をP+分離領域１４により複
数の領域に分離し、所望のエピタキシヤル領域１
３1にP+ベース拡散領域１５を形成し、その上で
エピタキシヤル層１３の表面のSiO2膜（酸化膜）
１６にエミツタ用開孔部１７およびコレクタ取り
出し領域用開孔部１８を形成した状態を示す。こ
こで、エミツタ用開孔部１７はベース拡散領域１
５上で開けられており、コレクタ取り出し領域用
開孔部１８はコレクタとしてのエピタキシヤル領
域１３1上において開けられている。また、N+埋
め込み層１２はエピタキシヤル領域１３1の底部
において設けられる。さらに、ベース拡散領域１
５は、拡散深さ2μｍで形成される。 FIG. 1A shows the P-type silicon substrate 11 after forming the N + buried layer 12 on the P-type silicon substrate 11.
An N-type epitaxial layer 13 is formed thereon, and the epitaxial layer 13 is separated into a plurality of regions by a P + isolation region 14, and a desired epitaxial region 1 is formed.
3. A P + base diffusion region 15 is formed in 1 , and a SiO 2 film (oxide film) on the surface of the epitaxial layer 13 is formed on the P + base diffusion region 15.
16 shows a state in which an emitter opening 17 and a collector extraction region opening 18 are formed. Here, the emitter opening 17 is the base diffusion region 1.
5, and the collector extraction region opening 18 is opened above the epitaxial region 131 serving as the collector. Further, the N + buried layer 12 is provided at the bottom of the epitaxial region 13 1 . Furthermore, base diffusion region 1
5 is formed with a diffusion depth of 2 μm.
このような構造を製造した後、まず、エミツタ
用開孔部１７およびコレクタ取り出し領域用開孔
部１８を介してベース拡散領域１５およびエピタ
キシヤル領域１３1に950℃程度の温度でリンドー
プを行い、続いて、900℃のウエツト雰囲気で５
分間の熱処理（第１の熱処理）を行う。すると、
第１図Ｂに示すように、ベース拡散領域１５中に
拡散深さ約1.0μｍでN+エミツタ拡散領域１９が
形成されるとともに、N+コレクタ取り出し領域
２０がエピタキシヤル領域１３1中に形成される。
さらに、エミツタ拡散領域１９とコレクタ取り出
し領域２０の表面部に酸化膜２１が形成される。 After manufacturing such a structure, first, the base diffusion region 15 and the epitaxial region 131 are doped with phosphorus at a temperature of about 950° C. through the emitter opening 17 and the collector extraction region opening 18. Next, in a wet atmosphere at 900℃,
A heat treatment (first heat treatment) is performed for 1 minute. Then,
As shown in FIG. 1B, an N + emitter diffusion region 19 is formed in the base diffusion region 15 to a diffusion depth of about 1.0 μm, and an N + collector extraction region 20 is formed in the epitaxial region 13 1 . Ru.
Further, an oxide film 21 is formed on the surface portions of the emitter diffusion region 19 and the collector extraction region 20.
次に、第１図Ｃに示すように、ホトレジスト２
２を用いたホトリン工程で、エミツタ拡散領域１
９より2μｍ内側に追い込んで開孔部２３をエミ
ツタ拡散領域１９上の酸化膜２１に形成する。こ
れにより、酸化膜２１は、エミツタ拡散領域１９
上については、その周辺部上にのみ残る。 Next, as shown in FIG.
In the photorin process using 2, the emitter diffusion region 1
An opening 23 is formed in the oxide film 21 on the emitter diffusion region 19 by 2 μm inward from the opening 9 . As a result, the oxide film 21 becomes the emitter diffusion region 19
As for the top, it remains only on the periphery.
次に、ホトレジスト２２を除去した上で、酸化
性雰囲気で1000℃、100分の熱処理（第２の熱処
理）を行う。すると、エミツタ拡散領域１９は、
第１図Ｄに示すように、ベース拡散領域１５中に
深く再分布するが、この時、表面に酸化膜２１が
残存している周辺部は、酸化膜２１形成時にこの
酸化膜２１中にとり込まれたリンの再拡散によ
り、表面から酸化膜２１が除去された部分より拡
散速度が見かけ上速くなり、深く拡散される。 Next, after removing the photoresist 22, heat treatment (second heat treatment) is performed at 1000° C. for 100 minutes in an oxidizing atmosphere. Then, the emitter diffusion region 19 becomes
As shown in FIG. 1D, it is redistributed deeply into the base diffusion region 15, but at this time, the peripheral area where the oxide film 21 remains on the surface is incorporated into the oxide film 21 when the oxide film 21 is formed. Due to the rediffusion of the removed phosphorus, the diffusion rate appears to be faster than in the area where the oxide film 21 has been removed from the surface, and the phosphorus is diffused deeper.
その結果、丸味を帯びたエミツタ拡散領域１９
の底面角部は、同第１図Ｄに円ｂで囲つて示すよ
うに角型に修正され、エミツタ拡散領域１９の底
面は平坦となる。 As a result, a rounded emitter diffusion region 19
The bottom corner of the emitter diffusion region 19 is modified into a square shape as shown by the circle b in FIG. 1D, and the bottom surface of the emitter diffusion region 19 is made flat.
この様子を拡大して第２図に示す。この図に示
すように、表面から酸化膜２１が除去されたエリ
アは矢印ｃの拡散速度であるが、表面に酸化膜２
１が残存する周辺部は、酸化膜２１よりのリンの
再拡散により矢印ｄのように見掛け上速い拡散速
度となり、その結果、破線で示す形状ではなく、
実線の形状の底面平坦なエミツタ拡散領域１９が
形成される。 This situation is enlarged and shown in FIG. As shown in this figure, the area where the oxide film 21 has been removed from the surface has a diffusion rate of arrow c, but the oxide film 21 is removed from the surface.
In the peripheral area where 1 remains, due to the re-diffusion of phosphorus from the oxide film 21, the diffusion rate is apparently high as shown by the arrow d, and as a result, the shape is not the shape shown by the broken line,
An emitter diffusion region 19 having a flat bottom surface is formed in the shape of a solid line.
なお、エミツタ拡散領域１９を再分布させる前
記第２の熱処理時に、エミツタ拡散領域１９の露
出表面に第１図ｄおよび第２図に示すように酸化
膜２４が形成される。また、この第２の熱処理に
より、同時に、コレクタ取り出し領域２０がエピ
タキシヤル領域１３1中に深く再分布される。 Incidentally, during the second heat treatment for redistributing the emitter diffusion region 19, an oxide film 24 is formed on the exposed surface of the emitter diffusion region 19, as shown in FIG. 1d and FIG. This second heat treatment also causes the collector extraction region 20 to be redistributed deeply into the epitaxial region 13 1 at the same time.
なお、以上の一実施例では、リンドープ直後の
第１の熱処理を900℃で行つたが、この温度とし
ては800℃〜1000℃が適当である。また、エミツ
タ拡散領域１９を再分布させる第２の熱処理を
1000℃で行つたが、この温度としては1000℃〜
1100℃が適当である。さらに、一実施例では、エ
ミツタ拡散領域１９上の酸化膜２１にエミツタ拡
散領域１９より2μｍ内側に追い込んで（各辺部
で2μｍ小さくして）開孔部２３を形成したが、
追い込み幅は0.5μｍ〜3μｍが適当である。また、
一実施例では、バイポーラトランジスタを作る半
導体基部としてエピタキシヤル層１３を用いた
が、半導体基板（シリコン基板１１）に直接トラ
ンジスタを形成することもできる。 In the above example, the first heat treatment immediately after phosphorus doping was performed at 900°C, but a suitable temperature is 800°C to 1000°C. In addition, a second heat treatment to redistribute the emitter diffusion region 19 is performed.
It was conducted at 1000℃, but this temperature ranges from 1000℃ to
1100℃ is suitable. Furthermore, in one embodiment, the opening 23 was formed in the oxide film 21 on the emitter diffusion region 19 by driving it 2 μm inward from the emitter diffusion region 19 (making the hole 23 smaller by 2 μm on each side).
The width of the drive-in is suitably 0.5 μm to 3 μm. Also,
In one embodiment, the epitaxial layer 13 is used as a semiconductor base for forming a bipolar transistor, but the transistor can also be formed directly on the semiconductor substrate (silicon substrate 11).
（発明の効果）
以上詳述したように、この発明の方法によれ
ば、底面が平坦なエミツタ拡散領域を形成し得る
ので、hFEのエミツタ面積依存性の少ないバイポ
ーラトランジスタを形成することができる。本発
明者らの実験によれば、ベース拡散領域の深さや
追い込みの幅および第２の熱処理の温度や時間を
適当に選ぶことにより、(1)式のαが０に近い値の
バイポーラトランジスタを製造することができ
た。より具体的に述べると、不純物ドープを950
℃で10分POCl3を用いて行い、次いで900℃ウエ
ツトO25分の第１の熱処理を行い、開孔部を形成
した後1000℃70分のO2雰囲気での第２の熱処理
を行つたところα≒0.05となつた。そして、この
ようにhFEのエミツタ面積依存性の少ないバイポ
ーラトランジスタを形成することができるので、
この発明の方法によれば、パターン設計上の制約
やプロセスコントロールに制約を与えることな
く、バイポーラ集積回路を製造することができ
る。(Effects of the Invention) As detailed above, according to the method of the present invention, it is possible to form an emitter diffusion region with a flat bottom surface, so it is possible to form a bipolar transistor with less dependence of h FE on the emitter area. . According to experiments conducted by the present inventors, by appropriately selecting the depth of the base diffusion region, the width of the driving-in region, and the temperature and time of the second heat treatment, a bipolar transistor in which α in equation (1) is close to 0 can be produced. could be manufactured. To be more specific, impurity doping is 950
A first heat treatment at 900 °C for 10 min in POCl 3 is carried out, followed by a first heat treatment at 900 °C for 5 min in wet O 2 , followed by a second heat treatment at 1000 °C in an O 2 atmosphere for 70 min after forming the openings. Eventually, α≒0.05. In this way, it is possible to form a bipolar transistor with less dependence on the emitter area of h FE , so
According to the method of the present invention, bipolar integrated circuits can be manufactured without imposing restrictions on pattern design or process control.
第１図はこの発明の半導体装置の製造方法の一
実施例を示す断面図、第２図は第２の熱処理後の
状態における要部を拡大して示す断面図、第３図
は従来の方法により製造されたバイポーラトラン
ジスタの断面図、第４図はhFEのエミツタ面積依
存性を実験した結果を示す図である。
１１……Ｐ型シリコン基板、１３……Ｎ型エピ
タキシヤル層、１３……エピタキシヤル領域、１
５……P+ベース拡散領域、１６……SiO2膜、１
７……エミツタ用開孔部、１９……N+エミツタ
拡散領域、２１……酸化膜、２３……開孔部。
FIG. 1 is a cross-sectional view showing an embodiment of the method for manufacturing a semiconductor device of the present invention, FIG. 2 is a cross-sectional view showing an enlarged main part in a state after the second heat treatment, and FIG. 3 is a conventional method. FIG. 4 is a cross-sectional view of the bipolar transistor manufactured by the method, and is a diagram showing the results of an experiment on the emitter area dependence of h FE . 11... P-type silicon substrate, 13... N-type epitaxial layer, 13... epitaxial region, 1
5...P + base diffusion region, 16...SiO 2 film, 1
7... Emitter opening portion, 19... N + emitter diffusion region, 21... Oxide film, 23... Opening portion.
Claims (1)
る半導体基板を準備する工程と、 前記第１の第１導電型拡散領域内に第２導電型
のベース領域を形成する工程と、 前記ベース領域内に開口部を有する拡散マスク
層を前記半導体基板の一主面上に形成する工程
と、 前記開口部を通して前記ベース領域内に第１導
電型不純物を拡散し、かつ第１の熱処理を行なう
ことにより、第２の第１導電型拡散領域を形成す
ると共に、この第２の拡散領域上に酸化膜を形成
する工程と、 この形成された酸化膜を前記第２の第１導電型
拡散領域の周辺部を残して除去する工程と、 この後第２の熱処理を行なうことにより第２の
第１導電型拡散領域をさらに深く拡散させ、エミ
ツタ領域とする工程とを有することを特徴とする
半導体装置の製造方法。 ２ 前記周辺部は、前記第２の第１導電型拡散領
域の外周部より0.5μｍ〜3μｍの幅を有する特許請
求の範囲第１項記載の半導体装置の製造方法。 ３ 前記拡散マスク層は酸化膜である特許請求の
範囲第１項記載の半導体装置の製造方法。 ４ 前記第１導電型不純物はリンである特許請求
の範囲第１項記載の半導体装置の製造方法。 ５ 開口部を有するマスク層を一主面上に形成し
た半導体基板を準備する工程と、 前記開口部を介して前記半導体基板に不純物を
ドープし、第１の熱処理を行なうことにより、不
純物拡散層を前記半導体基板の一主面に形成する
と共に、この不純物拡散層上に酸化膜を形成する
工程と、 この酸化膜を選択的に除去し、前記不純物拡散
層周辺部上にのみ酸化膜を残す工程と、 この後、第２の熱処理を行なうことにより、前
記不純物拡散層をさらに深く拡散させる工程とを
有することを特徴とする半導体装置の製造方法。[Claims] 1. A step of preparing a semiconductor substrate having a first diffusion region of the first conductivity type on one main surface; and a base region of the second conductivity type in the first diffusion region of the first conductivity type. forming a diffusion mask layer having an opening in the base region on one main surface of the semiconductor substrate; and diffusing a first conductivity type impurity into the base region through the opening. and forming a second diffusion region of the first conductivity type by performing a first heat treatment and forming an oxide film on the second diffusion region; 2, a step of removing the first conductivity type diffusion region leaving only the peripheral portion; and a step of further diffusing the second first conductivity type diffusion region to become an emitter region by performing a second heat treatment. A method of manufacturing a semiconductor device, comprising: 2. The method of manufacturing a semiconductor device according to claim 1, wherein the peripheral portion has a width of 0.5 μm to 3 μm from the outer peripheral portion of the second first conductivity type diffusion region. 3. The method of manufacturing a semiconductor device according to claim 1, wherein the diffusion mask layer is an oxide film. 4. The method of manufacturing a semiconductor device according to claim 1, wherein the first conductivity type impurity is phosphorus. 5. A step of preparing a semiconductor substrate in which a mask layer having an opening is formed on one main surface, doping an impurity into the semiconductor substrate through the opening, and performing a first heat treatment to form an impurity diffusion layer. forming an oxide film on one main surface of the semiconductor substrate, and forming an oxide film on the impurity diffusion layer; and selectively removing the oxide film, leaving the oxide film only on the periphery of the impurity diffusion layer. A method for manufacturing a semiconductor device, comprising: a step of further diffusing the impurity diffusion layer deeper by performing a second heat treatment.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59188102A JPS6167266A (en) | 1984-09-10 | 1984-09-10 | Manufacturing method of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59188102A JPS6167266A (en) | 1984-09-10 | 1984-09-10 | Manufacturing method of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6167266A JPS6167266A (en) | 1986-04-07 |
| JPH056343B2 true JPH056343B2 (en) | 1993-01-26 |
Family
ID=16217733
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59188102A Granted JPS6167266A (en) | 1984-09-10 | 1984-09-10 | Manufacturing method of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6167266A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0728308U (en) * | 1994-09-26 | 1995-05-30 | 株式会社クボタ | Riding rice transplanter |
| JP2633515B2 (en) * | 1996-05-31 | 1997-07-23 | 株式会社クボタ | Riding rice transplanter |
-
1984
- 1984-09-10 JP JP59188102A patent/JPS6167266A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6167266A (en) | 1986-04-07 |
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| EXPY | Cancellation because of completion of term |