JPH0569312B2 - - Google Patents

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Publication number
JPH0569312B2
JPH0569312B2 JP60215320A JP21532085A JPH0569312B2 JP H0569312 B2 JPH0569312 B2 JP H0569312B2 JP 60215320 A JP60215320 A JP 60215320A JP 21532085 A JP21532085 A JP 21532085A JP H0569312 B2 JPH0569312 B2 JP H0569312B2
Authority
JP
Japan
Prior art keywords
film
barrier film
resistance
atoms
insulating film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP60215320A
Other languages
Japanese (ja)
Other versions
JPS6273756A (en
Inventor
Shuji Kishi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP21532085A priority Critical patent/JPS6273756A/en
Publication of JPS6273756A publication Critical patent/JPS6273756A/en
Publication of JPH0569312B2 publication Critical patent/JPH0569312B2/ja
Granted legal-status Critical Current

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  • Electrodes Of Semiconductors (AREA)
  • Semiconductor Integrated Circuits (AREA)

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置に関し、特にアルミニウム
アロイスパイク防止用のために電極部に使用され
るバリアメタル膜を利用した抵抗素子を有するバ
イポーラ集積回路に関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and more particularly to a bipolar integrated circuit having a resistive element using a barrier metal film used in an electrode part to prevent aluminum alloy spikes. It is something.

〔従来の技術〕[Conventional technology]

従来、バイポーラ集積回路に搭載されてきた抵
抗素子には、エピタキシヤル単結晶膜を利用した
抵抗素子(拡散抵抗と呼ぶ)及び、酸化膜等の絶
縁膜上に堆積した多結晶シリコン膜を用いる抵抗
素子(多結晶シリコン抵抗)等がある。
Conventionally, resistance elements that have been installed in bipolar integrated circuits include resistance elements that use an epitaxial single crystal film (called a diffused resistance), and resistance elements that use a polycrystalline silicon film deposited on an insulating film such as an oxide film. There are elements (polycrystalline silicon resistors), etc.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上述した従来の拡散抵抗の場合、通常はn型導
電領域内に、p型導電領域を設けて抵抗素子を形
成するため、(1)n型導電領域をpn接合又は絶縁
膜で他領域に分離する必要がある。(2)n型導電領
域を最高電位に保つ必要がある。(3)pn接合容量
による動作速度の遅れがある。などの欠点を持ち
集積回路の性能及び集積密度の向上に制限を与え
るとともに、パターンレイアウトに大きな制約を
与えていた。
In the case of the conventional diffused resistor described above, a p-type conductive region is usually provided within an n-type conductive region to form a resistance element, so (1) the n-type conductive region is separated into other regions with a pn junction or an insulating film. There is a need to. (2) It is necessary to maintain the n-type conductive region at the highest potential. (3) There is a delay in operating speed due to pn junction capacitance. These drawbacks have limited improvements in integrated circuit performance and integration density, and have placed significant restrictions on pattern layout.

一方、多結晶シリコン抵抗の場合は、絶縁膜上
に形成出来ることから前記(1),(2),(3)の欠点は取
り除かれるが、抵抗の温度係数を持つことが重大
な欠点となつている。層抵抗の上昇に伴い、温度
係数は急激な増大を示し、回路上種々の抵抗を使
用する場合、温度変化に対して動作マージンを取
るかあるいは温度補償回路を設けるなどしなけれ
ばならず、回路設計の自由度を大幅に落としてい
る要因となつている。
On the other hand, in the case of polycrystalline silicon resistors, the disadvantages of (1), (2), and (3) above are eliminated because they can be formed on an insulating film, but a significant disadvantage is that they have a temperature coefficient of resistance. ing. As the layer resistance increases, the temperature coefficient rapidly increases, and when using various resistances in a circuit, it is necessary to take an operating margin against temperature changes or provide a temperature compensation circuit. This is a factor that significantly reduces the degree of freedom in design.

また、抵抗素子へ電極配線を取り付ける場合、
従来は抵抗素子上の酸化膜または窒化膜等の絶縁
膜にコンタクト穴を開口した後、Al配線を接続
していたが、本構造ではウエーハ製造工程および
組立工程における熱処理のためにアルミニウムア
ロイスパイクが生じてしまい、コンタクト抵抗の
増大、抵抗値の変動を引き起こすことがある。こ
の抵抗値変動は特性変動に直結してしまうことか
らIC,LSIの品質面から問題となつている。
Also, when attaching electrode wiring to a resistance element,
Conventionally, Al wiring was connected after opening a contact hole in an insulating film such as an oxide film or nitride film on a resistor element, but in this structure, aluminum alloy spikes are used for heat treatment in the wafer manufacturing process and assembly process. This may cause an increase in contact resistance and a fluctuation in resistance value. This variation in resistance value is directly linked to variation in characteristics, posing a problem from the quality perspective of ICs and LSIs.

本発明は上述した従来の欠点を除去し、アルミ
ニウムアロイスパイクを防止する構造を有し、絶
縁膜上に温度係数が極めて小さく、pn接合等の
寄生容量を持たない抵抗素子を実現するととも
に、層抵抗を大幅に変化させることが出来、回路
設計及びパターンレアウトの自由度を大幅に増す
ことができる半導体装置を提供することを目的と
する。
The present invention eliminates the above-mentioned conventional drawbacks, has a structure that prevents aluminum alloy spikes, has an extremely small temperature coefficient on an insulating film, and realizes a resistive element without parasitic capacitance such as a pn junction. It is an object of the present invention to provide a semiconductor device in which the resistance can be changed significantly and the degree of freedom in circuit design and pattern layout can be greatly increased.

〔問題点を解決するための手段〕[Means for solving problems]

本発明の半導体装置は、半導体基板上の絶縁膜
に設けられた電極用コンタクト開口部と、該電極
用コンタクト開孔部を覆つて形成された電極配線
金属のコンタクト面への進入を防止するためのバ
リア膜と、該バリア膜に連続して絶縁膜上に設け
られた該バリア膜と同一金属膜にバリア膜主構成
原子と異なる原子を導入して構成した抵抗素子と
を具備することにより構成される。
In the semiconductor device of the present invention, an electrode contact opening provided in an insulating film on a semiconductor substrate and an electrode wiring metal formed to cover the electrode contact opening are prevented from entering the contact surface. and a resistive element formed by introducing atoms different from the main constituent atoms of the barrier film into the same metal film as the barrier film, which is provided on an insulating film in succession to the barrier film. be done.

また、バリア膜の抵抗素子領域に酸素原子をイ
オン注入した後熱処理することにより層抵抗を大
幅に変化させ、所定の抵抗値を有する抵抗素子を
容易に得ることができる。
Further, by ion-implanting oxygen atoms into the resistive element region of the barrier film and then performing heat treatment, the layer resistance can be significantly changed, and a resistive element having a predetermined resistance value can be easily obtained.

〔実施例〕〔Example〕

次に、本発明について図面を参照して説明す
る。第1図乃至第3図は本発明の一実施例および
その製造方法を説明するための主要工程の模式図
で、第1図は断面図、第2図、第3図は平面図で
ある。本実施例ではエミツタ結合型論理回路にお
けるコレクタ負荷抵抗を例にとつて説明する。
Next, the present invention will be explained with reference to the drawings. 1 to 3 are schematic diagrams of main steps for explaining an embodiment of the present invention and its manufacturing method, in which FIG. 1 is a sectional view, and FIGS. 2 and 3 are plan views. In this embodiment, a collector load resistance in an emitter-coupled logic circuit will be explained as an example.

まず、第1図乃至第3図を用いて一実施例の製
造方法を説明する。第1図において、シリコン基
板1表面を覆う酸化膜2にコレクタコンタクト用
開孔部4を設ける。次いでバリア膜として窒化チ
タン(TiN)膜5を0.2μm厚で全面にスパツタ被
着させる。なお3は既に形成されているコレクタ
拡散層である。
First, a manufacturing method of one embodiment will be explained using FIGS. 1 to 3. In FIG. 1, a collector contact opening 4 is provided in an oxide film 2 covering the surface of a silicon substrate 1. As shown in FIG. Next, a titanium nitride (TiN) film 5 is sputtered to a thickness of 0.2 μm over the entire surface as a barrier film. Note that 3 is a collector diffusion layer that has already been formed.

次に、第2図に示すように、TiN膜5を通常
のフオトリソグラフイ技術を用いて、まずレジス
ト膜を形成し、そのレジスト膜をマスクとして
H2O2液中で不要のTiN膜をエツチング除去する
ことにより所定の抵抗素子形状6を得る。
Next, as shown in FIG. 2, a resist film is first formed on the TiN film 5 using a normal photolithography technique, and the resist film is used as a mask.
A predetermined resistance element shape 6 is obtained by etching and removing unnecessary TiN film in H 2 O 2 solution.

次に、第3図に示すように、コレクタコンタク
ト4部分のみを覆うように約1μm厚のアルミニ
ウム膜7を形成し、全面に酸素原子をイオン注入
したのち、400〜500℃の熱処理を施す。次にアル
ミニウム膜7を除去すると抵抗素子8が完成し本
実施例の半導体装置が得られる。
Next, as shown in FIG. 3, an aluminum film 7 with a thickness of about 1 μm is formed so as to cover only the collector contact 4 portion, oxygen atoms are ion-implanted over the entire surface, and then heat treatment is performed at 400 to 500°C. Next, by removing the aluminum film 7, the resistor element 8 is completed and the semiconductor device of this embodiment is obtained.

このようにして得られる抵抗素子の層抵抗は、
酸素原子の注入量によつて変化し、1016〜1018cm
−2の注入量で、数百Ω/□〜数十KΩ/□の層抵
抗が実現される。また電極部に酸素原子を注入し
ないのは、コンタクト抵抗を増大させないためで
ある。
The layer resistance of the resistive element obtained in this way is
Varies depending on the amount of oxygen atoms implanted, 10 16 to 10 18 cm
With an implantation dose of −2 , a layer resistance of several hundred Ω/□ to several tens of KΩ/□ is achieved. Further, the reason why oxygen atoms are not implanted into the electrode portion is to prevent contact resistance from increasing.

また、得られる抵抗素子の温度係数は、拡散抵
抗や多結晶シリコン抵抗に比して極めて小さく、
数十ppm/℃程度である。
In addition, the temperature coefficient of the resulting resistance element is extremely small compared to diffused resistance or polycrystalline silicon resistance.
It is about several tens of ppm/℃.

〔発明の効果」 以上説明したように、本発明を用いれば、アル
ミニウムアロイスパイクを防止する構造を有し、
絶縁膜上に温度係数が極めて小さくpn接合等の
寄生容量を持たない抵抗素子が実現されるととも
に、層抵抗を大幅に変化させられるため、回路設
計及びパターンレイアウトの自由度を大幅に増す
ことが出来るという効果が得られる。
[Effect of the invention] As explained above, if the present invention is used, it has a structure that prevents aluminum alloy spikes,
A resistor element with an extremely small temperature coefficient and no parasitic capacitance such as a pn junction can be realized on an insulating film, and the layer resistance can be changed significantly, greatly increasing the degree of freedom in circuit design and pattern layout. You can get the effect that you can.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図乃至第3図は本発明の一実施例およびそ
の製造方法を説明するための主要工程の模式図
で、第1図は断面図、第2図、第3図は平面図で
ある。 1……シリコン基板、2……酸化膜、3……コ
ンタクト拡散層、4……コレクタコンタクト用開
孔部、5……窒化チタン膜、7……アルミニウム
膜、8……抵抗素子。
1 to 3 are schematic diagrams of main steps for explaining an embodiment of the present invention and its manufacturing method, in which FIG. 1 is a sectional view, and FIGS. 2 and 3 are plan views. DESCRIPTION OF SYMBOLS 1... Silicon substrate, 2... Oxide film, 3... Contact diffusion layer, 4... Opening part for collector contact, 5... Titanium nitride film, 7... Aluminum film, 8... Resistance element.

Claims (1)

【特許請求の範囲】 1 半導体基板上の絶縁膜に設けられた電極用コ
ンタクト開口部と、該電極用コンタクト開口部を
覆つて形成された電極配線金属のコンタクト面へ
の進入を防止するためのバリア膜と、該バリア膜
に連続して絶縁膜上に設けられた該バリア膜と同
一金属膜にバリア膜主構成原子と異なる原子を導
入して構成した抵抗素子とを具備することを特徴
とする半導体装置。 2 バリア膜が窒化チタンであり、バリア膜主構
成原子と異なる原子が酸素原子である特許請求の
範囲第1項記載の半導体装置。
[Scope of Claims] 1. An electrode contact opening provided in an insulating film on a semiconductor substrate, and a method for preventing an electrode wiring metal formed covering the electrode contact opening from entering the contact surface. It is characterized by comprising a barrier film, and a resistance element formed by introducing atoms different from the main constituent atoms of the barrier film into the same metal film as the barrier film, which is provided on an insulating film in succession to the barrier film. semiconductor devices. 2. The semiconductor device according to claim 1, wherein the barrier film is made of titanium nitride, and the atoms different from the main constituent atoms of the barrier film are oxygen atoms.
JP21532085A 1985-09-27 1985-09-27 Semiconductor device Granted JPS6273756A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP21532085A JPS6273756A (en) 1985-09-27 1985-09-27 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP21532085A JPS6273756A (en) 1985-09-27 1985-09-27 Semiconductor device

Publications (2)

Publication Number Publication Date
JPS6273756A JPS6273756A (en) 1987-04-04
JPH0569312B2 true JPH0569312B2 (en) 1993-09-30

Family

ID=16670354

Family Applications (1)

Application Number Title Priority Date Filing Date
JP21532085A Granted JPS6273756A (en) 1985-09-27 1985-09-27 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS6273756A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04114464A (en) * 1990-09-04 1992-04-15 Matsushita Electron Corp Semiconductor device

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5437360A (en) * 1977-08-29 1979-03-19 Kansai Paint Co Ltd Method of treating drainage at electrodepositing step
US4380259A (en) * 1981-01-12 1983-04-19 The Coe Manufacturing Company Veneer lathe apparatus and method using independently adjustable powered back-up roll

Also Published As

Publication number Publication date
JPS6273756A (en) 1987-04-04

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