JPH056943B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a delay detector for demodulating a signal subjected to phase modulation, and particularly to a delay detector suitable for mobile communications.

(Prior art) A delay detector uses a signal one time slot before as a reference phase signal necessary for phase detection, and does not require a carrier recovery circuit, so it is suitable for mobile communications where the phase fluctuations of the received signal are large. It is known as a suitable wave detector.

In addition, in mobile communications, one of the error correction methods is
As one means, the received electric field strength is observed every baud, and when the value is less than a certain value, the received data obtained at that time is determined to be invalid as so-called erasure.

(Problem to be Solved by the Invention) However, in situations where fading is severe and the phase of the received signal fluctuates greatly even within a short period of time, such as the baud interval, even if a delay detector is used, It is impossible to avoid errors in data judgment due to phase fluctuations.

In addition, in situations where the received electric field strength does not decrease and only severe phase fluctuations occur even when attempting to determine erasure, the conventional method that focuses only on the magnitude of electric field strength may not be able to accurately determine erasure. It is possible.

SUMMARY OF THE INVENTION An object of the present invention is to provide a delay detector that is capable of reducing errors in data determination and correctly determining erasure even in an environment where phase fluctuations due to fading or the like are large.

(Means for Solving the Problem) The present invention includes a first delay circuit that delays an input signal by Ts/2, where Ts is a baud interval, and a link between the input signal and the first delay circuit. a multiplier circuit that multiplies the output, a low-pass filter that receives the output of the multiplier circuit and has a bandwidth of 1/Ts, and a timing extraction circuit that extracts a change point in the baud interval of the input signal from the input signal. a second delay circuit that delays the output of the timing extraction circuit by Ts/4; and a third delay circuit that delays the output of the timing extraction circuit by 3/4·Ts.
a first sampling circuit that samples the output of the low-pass circuit at a timing that corresponds to the output of the second delay circuit; and a first sample circuit that samples the output of the low-pass circuit at a timing that corresponds to the output of the third delay circuit. a second sample circuit that samples at
A data output signal is obtained from the output of the second sample circuit, and a data valid signal is obtained from the output of the second sample circuit.

(Function) The present invention uses the above-mentioned means to provide 2 points per baud interval.
output. The signal obtained from the first sample circuit is a correlation over half the baud interval between the second half of the signal from one time slot ago and the first half of the signal from the current time slot, and is used as the data output signal. In conventional delay detectors, the correlation over the baud interval is used as the data output signal, and therefore, when there is a phase fluctuation with a period shorter than the baud interval, it is difficult to obtain correct data output. However, in the present invention, since the time for observing the correlation is half that of the conventional method, it is possible to withstand more severe phase fluctuations, and therefore it is possible to fluctuate the so-called irreducible errors peculiar to mobile communications. .

The signal obtained from the second sample circuit is a correlation over half the baud interval between the first half and the second half of the signal of the current time slot, and when there is no phase variation, a large value is obtained, but when the phase variation is severe and the second half is present, a large value is obtained. When the data output signal obtained from one sample circuit is unreliable, only a small value is obtained and can therefore be used as a signal to determine whether the data output signal is valid.

(Embodiment) FIG. 1 is a diagram showing an embodiment of the present invention.
The input signal is delayed by half the baud interval Ts in the delay circuit 1, and the input signal is multiplied by the delayed input signal in the multiplier circuit 2. Multiplier circuit 2
The output of is input to a low-pass filter 3 whose bandwidth is equal to the reciprocal of Ts. On the other hand, the input signal is also given to the timing extraction circuit 4, and the change point of the baud interval of the input signal is extracted. The output of the timing extraction circuit 4 is delayed by Ts/4 and 3/4·Ts by delay circuits 5 and 6, respectively.
The output of low-pass circuit 3 is sampled by sample circuits 7 and 8 at timings corresponding to the outputs of delay circuits 6 and 7, respectively. A data output signal is obtained from the output of the sample circuit 7, and a data valid signal is obtained from the output of the sample circuit 8.

FIG. 2 is a waveform explanatory diagram, where a is the input signal,
b is an output signal of delay circuit 1, c is an output signal of low-pass filter 3, d is an output signal of timing extraction circuit 4, and e and f are output signals of delay circuits 6 and 7, respectively.

(Effects of the Invention) As described above, according to the present invention, a delay detector that has fewer errors in data determination and is capable of correctly determining erasure is obtained.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a first embodiment of the present invention, and FIG.
The figure is a waveform diagram for explaining the operation of the present invention. In the figure, 1, 5, and 6 are delay circuits, 2 is a multiplication circuit, 3 is a low-pass filter, 4 is a timing extraction circuit, and 7 and 8 are sample circuits.

Claims (1)

[Claims] 1 When input signal is baud interval Ts,
a first delay circuit that delays by Ts/2, a multiplier circuit that multiplies the input signal by the output of the first delay circuit, and a bandwidth of which the output of the multiplier circuit is input is 1/Ts. a low-pass filter; a timing extraction circuit for extracting a change point in the baud interval of the input signal from the input signal; a second delay circuit for delaying the output of the timing extraction circuit by Ts/4; 3/4 output
a third delay circuit that delays the output of the low-pass circuit by Ts; a first sample circuit that samples the output of the low-pass circuit at a timing corresponding to the output of the second delay circuit; and a second sample circuit that samples at a timing corresponding to the output of the third delay circuit, and receives a data output signal from the output of the first sample circuit and a data valid signal from the output of the second sample circuit. Obtain delay detector.