JPH0570986B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a signal processing device for receiving encrypted video and/or audio in a device for encrypting and transmitting video and/or audio on CATV, pay television, etc.

Conventional configuration and its problems In pay TV, etc., the video signal is encrypted and transmitted to prevent it from being eavesdropped on by anyone other than the subscriber, and the normal video signal is displayed only after the subscriber decrypts it. I have to. Several methods have been considered for encrypting this video, but all of them have had problems.

For example, in the case of a method in which only the video signal is always inverted in black and white, a method in which the synchronization signal is compressed, and a method in which the synchronization signal is inverted, all of them have the disadvantage that they are easy to decode and easily intercepted. Furthermore, in the case of the method in which the synchronization signal is removed, jitter in the reproduced synchronization signal remains and the screen becomes unstable. In the case of the method of removing the color burst signal, the phase of the reproduced color burst was inaccurate and the color was unstable.

In addition, when the audio is encrypted using a method that scrambles PCM audio, the band becomes wider when using a different carrier, making it difficult to use FM such as satellite broadcasting.
It was not suitable for decoding, and the decoding unit was also expensive. When audio is randomly switched between multiple carriers, there are problems in that the decoding section becomes complicated and it is difficult to maintain stereo balance.

OBJECTS OF THE INVENTION It is an object of the present invention to provide a device in which eavesdropping is difficult and the decoding section is suitable for LSI implementation. A further object of the present invention is to provide a signal processing device that can stably reproduce a synchronization signal.

Structure of the Invention In the present invention, a vertical trigger signal and a horizontal trigger signal in a television signal consisting of a video signal, a digital audio signal arranged in chronological order, and encrypted information are used to perform synchronized playback of a video signal. The audio signal and encrypted information are sampled, the encrypted video signal and audio signal are decoded, and normal video and audio signals are output.

At this time, a circuit is provided that detects a vertical trigger signal using the vertical burst signal, extracts the color burst signal as the output of an amplifier tuned to the color burst signal, detects the color burst signal connected in multiple cycles, and generates a pulse. Generates a pulse with a horizontal scanning period. This pulse is delayed to reset the frequency divider that divides the signal with a frequency that is an even number multiple of the color burst signal, generates a gate pulse that extracts the color burst signal, and uses the extracted color burst signal to activate the color subcarrier oscillator. A PLL circuit is formed by synchronizing the frequency and phase and dividing the synchronized color subcarrier and a frequency that is an even multiple of the color burst signal. A signal having a frequency that is an even number multiple of the color burst signal thus locked is divided to form a vertical synchronization signal and a horizontal synchronization signal.

DESCRIPTION OF THE EMBODIMENTS Fig. 1 shows a block diagram according to an embodiment of the present invention, in which 1 is a tuner of a television receiver, 2 is a VIF circuit, 3 is a detection circuit, and 4 is a synchronizer for reproducing a synchronization signal. Reproduction circuit, 5 is data processing circuit 6
This is a video processing circuit that switches whether or not to invert a video signal based on the data processing result. The data processing circuit 6 processes data, converts digital audio into analog, and outputs a determination signal (switching signal) indicating whether or not to invert the video signal. 7
is the RF remodulation circuit, and the audio is successfully decoded,
This is a circuit that takes video as input and forms an RF (VHF) signal.

FIG. 2 is a waveform diagram of the signal during the horizontal blanking period of the signal processing device of the present invention, where φ ₀ is the normal
Shows the horizontal retrace period of the video signal of the NTSC television signal and the period before and after it. φ ₁ indicates the horizontal retrace period (including audio data) of the video signal in the embodiment of the present invention, and the period before and after it.

Figure 3 is a waveform diagram of the signal during the vertical blanking period of the same device, where _φ20 indicates the vertical retrace period of the video signal of a normal NTSC television signal, and _φ21 indicates the horizontal synchronizing pulse of an even field. show. _φ23 indicates the odd field horizontal synchronization pulse. _φ21 ,
_φ23 is synchronized with H _T (horizontal trigger signal) shown in _φ1 . φ ₂₂ and φ ₂₄ indicate the video signal and audio signal during the vertical retrace period in the embodiment of the present invention. _φ22 is an even field signal, and _φ24 is an odd field signal.
_φ25 is a vertical synchronization signal formed from the vertical trigger V _T , _φ26 is the horizontal synchronization signal of the 4th H, and _φ1 ,
It is a narrow pulse starting from t ₂ shown in φ ₁₁ ,
φ ₂₇ is the 267H horizontal synchronizing signal, which is a narrow pulse starting from t ₂ also shown at φ ₁ and φ ₁₁ in FIG. _φ26 is the output of the detection circuit 22 in FIG.
It is used to match the leading edge of the vertical synchronizing signal _φ25 with the leading edge of the horizontal synchronizing signal. Below, Figures 2 and 3
The operation will be explained with reference to the figures.

The output of the detection circuit 3 does not have a horizontal synchronization signal and a vertical synchronization signal, as shown in φ ₁ in FIG. 2 and φ ₂₂ and φ ₂₄ in FIG. 3, but instead has a vertical trigger signal V _T and a horizontal trigger signal H. _T is inserted. Further, the shaded portions of φ ₂₂ and φ ₂₄ in FIG. 3 have the same configuration as φ ₁ from t ₂ to t ₆ in FIG. 2. The polarity of the video signal is repeatedly inverted and non-inverted at random intervals for each horizontal scanning line or for each screen. Note that changing the polarity of the color burst signal causes problems such as hue shift, so the color burst signal is not inverted.

Synchronous playback, video playback, and audio playback will be described below. First, an outline of the operation will be described with reference to FIG.

Assuming that synchronous playback is performed normally, the output of the video buffer amplifier 8 is sliced by the slicing circuit 12, shaped into a binary signal, sampled by the sampling circuit 13, and stored in the buffer memory 18 during the horizontal scanning period (hereinafter referred to as "H"), the delta demodulator 19 demodulates the delta modulation, transfers it to the buffer memory 20, and outputs the buffer memory 20 to the D/A converter 21.
D/A conversion at a speed of 2f _H , sample rate 2f _H ,
The high quality audio of the highest frequency _fH is output from the D/A converter 21, and two outputs, right and left, are obtained.

On the other hand, in Fig. 3, _φ22 5H~7H, _φ24 268H~
Write 270H data to buffer memory 14,
Then, it is read out and decoded by the decryption circuit 15, a signal indicating whether or not to invert the video signal is output, and a pulse is formed by the inversion switching circuit 16 to determine the inversion period.
Add to the synthesis circuit 10. On the other hand, the output of the clamp circuit 9 is inverted by the inverting amplifier 17.
The output of is also added to the synthesis circuit 10, and the inversion switching circuit 16
The output of the synthesis circuit 10 is output from the clamp circuit 9.
and the output of the inverting amplifier 17.
The output of the inverting switching circuit 16 is also added to the inverting amplifier 17, and when inversion is not required, the output of the inverting amplifier 17 is suppressed to reduce crosstalk in the combining circuit 10. Then, by clamping the output of the synthesis circuit 10 with a clamp circuit 11, a normal video signal can be obtained.

Next, synchronized playback will be described in detail with reference to FIG. Further, FIG. 6 shows the procedure of synchronous playback and data processing. In FIG. 5, 22 is a detection circuit for the vertical trigger signal V _T and horizontal trigger signal H _T shown at φ ₂₄ and φ ₂₄ in FIGS. 3 and 8, 23 is a reproduction circuit for the color subcarrier f _sc , and 24 is a 12f _sc and f _sc of VCO25
PLL circuit that applies PLL, 26 is a 1/5 frequency divider circuit, 2
7 is a 1/3 frequency dividing circuit, and 28 is the output of the 1/3 frequency dividing circuit 27, that is, a 1/455 frequency dividing circuit of 4f _sc , and the output is 2f _H. 29 is a 1/2 frequency divider circuit, and its output is _fH .
30 is a 2f _H 1/525 frequency divider circuit whose output is approximately 60Hz
It is. 31 is an equalization pulse generation circuit, and 32 is a vertical synchronization signal generation circuit. 28 to 32 are circuits known as television signal synchronization circuits.

33 is a sampling clock forming circuit, and assuming the data transmission rate is 12/5f _sc , the 1/5 frequency dividing circuit 2
6 output 12/5f _sc is used to form the sampling clock. Sampling clock formation circuit 3
3 is supplied to the data extraction processing circuit 6B to sample the input audio data and process the data. 6A is an audio reproduction circuit that generates analog audio.

34 is a burst gate forming circuit that forms a burst gate from the output of the 1/2 frequency divider circuit 29.
Then, in the synchronization reproducing circuit 35, a composite synchronization signal is formed by the outputs of the 1/2 frequency divider circuit 29, the equalization pulse generation circuit 31, and the vertical synchronization signal generation circuit 32,
The composite synchronization signal output of the synchronization reproduction circuit 35 and the output of the video clamp/inversion circuit 36 are combined by a video synthesis circuit 37 to create a video signal. The video clamp/inversion circuit 36 clamps the video signal,
According to the output of the data extraction processing circuit 6B, the video signal is inverted only for a necessary period.

Establishment of a synchronization signal, data processing, and audio processing are performed in the order shown in FIG. 6 below.

Here, FIG. 7 is a block diagram of the synchronizing signal reproducing section, and FIGS. 8 and 9 are operational waveform diagrams.

In FIG. 8, φ ₂₁ to φ ₂₄ are the same as those in FIG. 3. _φ28 is the vertical synchronization signal of _φ21 and _φ24 ( _T28 to _T29
This is the vertical synchronization pulse obtained by integrating the In Figures 8 and 9, φ ₃₇ is the gate pulse that extracts H _T shown in φ ₁ in Figure 2, and φ ₃₁ is φ ₃₇
φ 31 ′ is the pulse of H _T at T ₃₁ extracted by φ 37 and φ ₃₁ ′ is the pulse of H _T at T ₃₁ ′ extracted by φ ₃₇
This is the pulse of φ ₃₃ and φ ₃₃ ′ are synchronizing pulses of horizontal period, which are synchronized with the trailing edges of φ ₃₁ and φ ₃₁ ′. below,
The operation will be explained using FIG. 7, FIG. 8, and FIG. 9.

First, in conjunction with FIG. 7, the horizontal trigger signal H _T ,
The vertical trigger signal V _T sampling circuit will be described in detail. 2.2MHz bandpass amplifier in Figure 7
BPA38, shown in φ ₂₂ and φ ₂₄ in Figures 3 and 8.
Extract the 2.2MHz vertical burst signal. next,
The vertical burst detection circuit 39 detects the 22MHz waveform as n
Generates pulses only when 3 or more consecutive pulses occur. This is φ ₃₅ in Figure 8, from time T ₁₆ to T ₁₆₁ to T ₂₄
For example, a _2.2 MHz sine wave becomes 5.5
There are cycles (one cycle of 2.2MHz is approximately 450ns)
So, if T ₁₆ to _{T 161} (the same goes for T ₂₄ to _{T 241} ) is 2.5 μs, it will be 5.5 cycles).

The above n is set to 5, and the vertical burst detection circuit 3 is a circuit (for example, a 5-times voltage rectifier circuit) that generates an output pulse only when 5 or more 2.2MHz sine waves are consecutive.
9, and its output makes T ₁₆₁ (and T ₂₄₁ )
This triggers the retriggerable monostable multivibrator in the vertical burst detection circuit 39. The outputs of this monostable multivibrator are φ ₃₆ and φ ₃₆ ' in FIG. φ ₂₂ indicates the vertical retrace period of the even field video signal and audio signal, T ₁₁ to T ₂₁ indicate the 2H, T ₂₁ to _{T 31} indicate the 3H,
φ ₂₄ indicates the vertical retrace period of the odd field video signal and audio signal, T ₁₁ ′ to _{T 21} ′ are the 265th H,
T ₂₁ ′ to T ₃₁ ′ indicate the 266th H. ₃₅ is for an even field, in which case the monostable multivibrator in the vertical burst detection circuit 39 mentioned above is
Trigger on T ₁₇₁ and T ₂₅₁ . Therefore, the output of the monostable multivibrator ends at T _X ' of φ ₃₆ in FIG. T _X ′ only needs to be after T ₂₉₁ , and preferably before T ₃₁ . Just as ₃₅ is a high level in T ₁₆₁ , ₃₅ is a high level in T ₂₄₁ .
The same applies to T ₁₆₁ ′.

The V _T extraction circuit 40 in FIG. 7 gates the output of the video buffer circuit 8 at φ ₃₆ and further integrates it by a sufficiently large specific number to obtain the signal φ ₂₈ in FIG. This waveform is sliced at the level of the alternate long and short dash line in FIG. 8 to obtain a waveform of _φ29 . _φ29 is the vertical trigger pulse. T ₂₈₁ varies depending on the temperature characteristics of the slicer, but does not change over short periods of time, such as seconds. Therefore, there is no practical problem and there is no need to consider a special circuit. The output of the V _T extraction circuit 40 is the 8th
The shape is shown in the figure φ ₂₉ , and as is clear from φ ₂₂ and φ ₂₄ ,
_φ29 starts from T ₂₈₁ for both odd and even fields. Then, at the end of φ ₂₉ , the monostable multivibrator 41 is triggered to obtain a clamp pulse φ ₃₀ . On the other hand, the flip-flop 42 is reset at _φ30 .

Since the output ₃₉ of monostable multivibrator 43 is triggered at the end of φ ₃₇ as shown in FIG. 9, the output of AND gate 44 does not occur before the next portion of the horizontal trigger signal at T ₃₁ . Therefore,
It is only necessary to consider the output of the NOR gate 45 to be ₃₀ .

On the other hand, the output of the video buffer circuit 8 is
6, the width of H _T shown in Figure 2 φ ₁ (approximately
0.4μs) is removed. In addition,
If t ₁ is further shifted by about 0.5 μs and the width of H _T is made to be about 0.9 μs, noise can be further removed.

The output of the NOR gate 45 is ₃₀ or _φ28 , but
For vertical synchronization, consider ₃₀ .

Next, in the clamp circuit 47, φ ₂₂ and φ ₂₄ are set by φ ₃₀ .
Clamp a little in front of T ₃₁ . If the discharge time constant is made a little longer, the clamping effect will continue even at T ₃₁ ' of φ ₂₄ .

The thus clamped signal is sliced by a slicing circuit 48. Its slice output is φ ₄₀
It is indicated by. A flip-flop (FF) 42 reads its previous state at the falling edge (terminating edge) of the horizontal trigger pulse. Therefore, the output of FF42 is of the form _φ37 . In even field, the end of _φ37 is 1/2H
Extends backwards. ₃₇ and the slice output φ ₄₀ are formed by the AND gate 49, the output becomes φ ₃₁ (or φ ₃₁ ′). When the monostable multivibrator (MM) 50 is triggered at φ ₃₁ and its output is applied to the reset terminal of the flip-flop (FF) 51, it is set at the falling edge of φ ₃₁ (φ ₃₁ ') and immediately reset by the output of MM 50. , a narrow width pulse is obtained from the Q, output of FF51.

The output of this FF51 is sent to the vertical synchronization phase monitoring circuit 5.
Supply to 3. This monitoring circuit 53 compares the phase with a vertical pulse obtained by dividing the output of the 12f _sc oscillation circuit 25 by 1/3 in the 1/3 frequency dividing circuit 27. In addition, the monitoring circuit 53 uses the output of BPA38 or _φ35 ,
Only φ ₃₁ is compared, and φ ₃₁ ′ is not compared. Of course, for φ ₃₁ ′, the 527th, or second pulse (this is φ ₃₃ and φ ₃₃ ′, and can be formed from the output of the 1/525 frequency divider 30 and the output of the 1/455 frequency divider 28 ) may be compared. If the output of the vertical synchronization signal generation circuit 32 and the output of the FF 51 do not match, the output of the FF 51 is given priority. At this time, the output of the FF 51 is supplied from the monitoring circuit 53 to 28 to 31 via the phase monitoring switching circuit 52. The operation of the phase monitoring switching circuit 52 will be described later. In this case, in order to exclude cases where the output of the FF51 happens to shift due to noise during normal operation, only when the output of the FF51 and the output of the vertical synchronization signal generation circuit 32 do not match for several consecutive frames (or several fields) , for the first time, the output of FF51 divides the circuit 28~
30. Configure the monitoring circuit 53 to reset the vertical synchronization signal generation circuit 32. The pulse width of the output of the vertical synchronization signal generating circuit 32 is one cycle of 4f _sc , that is, about 70 ns.

On the other hand, when estimating the delay of _φ31 from the output of the video buffer circuit 8, we assume that the delay of the integration circuit 46 is 50 ns.
The fundamental wave component with a pulse width of 400 ns for (H _T (φ ₃₁ )) is
The frequency is 1.25MHz, and the delay of about 50ns means that the pulse waveform remains almost the same.) If the other circuits are formed with shot key TTL circuits (MM50 uses delay time, low power consumption shot key TLL series will suffice), the amount of delay will be reduced.
It can be estimated that it is about 100ns or less. Therefore, when the output of FF51 and the output of vertical synchronization signal generation circuit 32 are in phase, the output of FF51 and the output of generation circuit 32 are one cycle of 4f _sc from the fall of H _T of the output of video buffer circuit 8. Delayed by ~2 cycles. However, as is clear from φ ₁ in FIG. 2, the falling edge T ₄ of H _T (φ ₃₁ ) is approximately 1.1 smaller than the rising edge t ₅ of the normal horizontal synchronizing signal.
It is ~1.2μs faster, so there is plenty of room even if it is delayed by 0.1μs. Therefore, the output of FF51 is delayed by about 14 cycles of 4f _sc , and the _frequency dividing circuit 28~
30 and the vertical synchronizing signal generating circuit 32 may be reset. In this case, the phase difference between the signal obtained by delaying H _T (φ ₃₁ ) (corresponding to the leading edge of the horizontal synchronization signal in FIG. 2) and the output of the vertical synchronization signal generation circuit 32 is always
It takes less than one cycle of 4f _sc .

However, when noise enters, _φ31 itself causes jitter, so for example, in the case of a phase difference of ±2f _sc ,
The frequency divider circuits 28 to 30 are reset by the output of the frequency divider circuit of the vertical synchronization signal generation circuit 32, and only when the phase difference of ±3f _sc or more continues for several fields, the output of the FF 51 is delayed and the frequency divider circuits 28 to 30 are reset with a pulse. Generation circuit 3
Reset 2.

In this way, the frequency dividing circuits 27 to 31 in FIG.
and vertical synchronization is established. For horizontal synchronization, φ ₃₁ alone is not sufficient;
This will be discussed later. In this case as well, the pulse that delayed the output of _φ31 or FF51 changes over time, but it does not move quickly enough to be visible, so it is not visible as movement on the TV screen.

From the vertical pulses obtained in this way, horizontal and vertical synchronizing signals are obtained as frequency-divided outputs, and based on this, the burst gate pulse forming circuit 3
4, a burst gate pulse is formed, and an equalization pulse forming circuit 31 forms an equalization pulse. The output of the burst gate pulse forming circuit 34 is applied to the video synthesis circuit 37. φ ₃₉ is T ₃₁ as shown in Figure 9
Since the level becomes low immediately after (T ₃₁ ′), the clamp pulse (burst gate pulse) is not output from the AND gate 44 only at the 4th and 267th H.
From the 5th H (and 268th H), the output of the video buffer circuit 8 is clamped at a position where a color burst occurs every H, and the color burst signal is extracted from the output of the video buffer circuit 8 using _φ38 . Using this color burst signal, the _fsc reproducing circuit 23 shown in FIG. 5 reproduces the _fsc . f _sc is synchronized with the color burst signal of the transmission signal by the AFPC circuit. The output thereof and the output of the 12f _sc oscillation circuit 25 are locked by the PLL circuit 24. The PLL circuit 24 consists of a phase comparison circuit and a low pass filter (LPF). f _sc
AFPC circuit pull-in of regeneration circuit 23, PLL circuit 2
Assuming that it takes several tens of fields to pull in each of the four fields, the output of the VCO 25 matches the phase of the color burst signal output from the video buffer circuit 8 within about two seconds.

After such phase synchronization pull-in, a gate for extracting the horizontal trigger signal is operated.

Regarding the operation of the horizontal trigger signal H _T detection circuit,
This will be explained using FIGS. 10 and 11. As described above, after detecting the vertical trigger signal V _T and resetting the vertical period, the horizontal phase monitoring circuit 52 is operated.

In FIG. 7, in the output of a bandpass amplifier (BPA) 55 tuned to f _sc , a component of f _sc appears at the position of the color burst signal, as indicated by φ ₂ in FIG. Color burst detection rotation 56
Detection is performed to form a pulse of _φ74 in Fig. 11.
The color burst detection circuit 55 has a configuration as shown in FIG. 10, and when φ ₂ is transmitted to the capacitor 65 via the diode 64, a voltage shown as φ ₆₅ in FIG. 11 is generated across the capacitor 65. When this voltage exceeds the level of _VX , transistor 67 becomes conductive and an output with a waveform of _φ67 appears at its collector. At t ₁₀ , this φ ₆₇ falls, but this is inverted by the inverter 69,
An integral circuit consisting of a resistor 70 and a capacitor 71 removes minute (pulse width) pulses, and a monostable multivibrator (MM) 73, via an AND gate 72,
Trigger 74. If a slow-response monostable multivibrator is used as MM73, its output will be delayed by _Δt . The output is supplied to the AND gate 72, and the pulse width is maintained far behind the color burst signal as shown at φ ₇₃ in FIG. 11, so that _the narrow pulse after t ₁₁ is
Prevent it from being transmitted to 74.

On the other hand, monostable multivibrator (MM) 76
A pulse φ ₇₆ starting from the trailing edge of φ ₇₄ is formed at , making transistor 78 conductive and discharging the charge in capacitor 65 . Therefore, the pulse shown by the dashed line after t ₁₁ of φ ₆₇ does not appear. This output _φ74 is sent to the pulse generation circuit 57.
In addition, a narrow pulse (with a width of one cycle of 4 f _sc or less) starting from the leading edge t ₁₀ of φ ₇₄ is formed and supplied to the horizontal phase monitoring switching circuit 52 . This circuit 52 is
It is a circuit composed of hard logic or high-speed CPU. As is clear from FIG. 7, when the vertical periodic trigger pulse _φ31 is obtained, the frequency dividing circuit 28~
30 and the equalization pulse generation circuit 31 are reset. At this time, the horizontal phase monitoring switching circuit 52 passes the output of the vertical phase monitoring circuit 53 as is.
Here, the subsequent operation will be described assuming that vertical synchronization has been established as described above.

Next, the color burst detection output pulse of the pulse generation circuit 57 is judged by the horizontal phase monitoring switching circuit 52, and the difference from the above-mentioned φ ₃₁ (near t ₃ to _{t 4} in FIG. 2) is approximately 2.
At times equal to t ₃ , t ₄ to _{t 10} in the figure, a gate pulse is taken out from the decoder 54 as φ ₃₈ in FIG. 9, and φ ₃₈ is output as a burst gate pulse from the next horizontal period (5H onwards). This _φ38 is supplied to the AND gate 44 and the burst extraction circuit 62, and the color burst signal output from the burst extraction circuit 62 is
It is supplied to the AFPC circuit 63. The AFPC circuit 63 is similar to the AFPC circuit of the color subcarrier oscillation circuit of a color television. When the AFPC circuit 63 is synchronized with the color burst signal output from the video buffer circuit 8, the output of the VCO 25 is also synchronized with the color burst signal via the PLL circuit 24. 12f _sc of VCO25
When the oscillation output is synchronized, the 4f _sc of the 1/3 frequency divider circuit 27
Since the output is also synchronized, _φ31 is connected to each frequency dividing circuit 28 to 3.
When reset to 0, in the next frame, the output obtained by dividing 4f _sc by 1/455 x 2 x 525 ignores the delay of each frequency divider circuit 28 to 30, and from about 70 ns before the trailing edge of _φ31 , It is obtained up to the trailing edge of φ ₃₁ , and its phase is the same every frame. Vertical phase monitoring circuit 53
This kind of phase difference information is also transmitted to the horizontal phase monitoring switching circuit 52, and the horizontal phase monitoring switching circuit 52
The frequency division output of the 525 frequency divider circuit 30 is also monitored, and when the phase difference between the vertical trigger signal V _T and the output of the 1/525 frequency divider circuit 30 becomes constant as described above, the output of the decoder 54 φ ₄ ′ is output as a burst gate pulse. φ ₄ ′ in FIG. 2 is determined as shown in FIG. 2 based on the phase of φ ₃₁ or 1/525. This results in
The accuracy of burst gate pulse will be better than _φ4 .

On the other hand, the horizontal phase monitoring switching circuit 52 generates an H _T sampling _gate pulse having a pulse width of approximately t ₁ to _{t 5} in FIG _. pull out. This horizontal trigger signal H _T is extracted by the AND gate 49.
This is possible with the same configuration as MMO50 and FF51.
From the output of the H _T extraction circuit 58, a horizontal synchronizing signal is generated by a pulse generation circuit 59. This pulse generating circuit 59 can be composed of two monostable multivibrators. The output is transmitted to the horizontal AFC oscillation circuit 60,
Pull in the horizontal oscillation phase. The output of the horizontal AFC oscillator circuit 60 generates a narrow pulse in the pulse generation circuit 61, which is compared with the horizontal frequency f _H signal output from the 1/2 divider circuit 29, and when the difference between them becomes a constant value, horizontal scanning is performed. When f _H stops changing on a line-by-line basis,
If we extract only the portions before and after the horizontal trigger signal H _T in Figure 2 with reference to the gate pulse (for example, t ₂ ~
t ₄ width) from the decoder 54 and transmitting it to the H _T sampling circuit 58
Prevents noise other than H _T from entering.

As described above, once synchronization is established, it will not easily collapse, and the negative effects of noise will be reduced. In addition, the horizontal phase monitoring and vertical phase monitoring circuits monitor phase deviations, and when a phase deviation between the normal phase (after synchronization is established) and the input signal occurs for a short period of time, the signal of the phase before the deviation occurs is detected. (In other words, by using a signal in a synchronized state that has already been established), it is possible to eliminate adverse effects such as phase disturbance caused by accidental noise.

Here, after establishing synchronization, as shown in FIG. 6, a data sampling gate pulse is formed, data is sampled, and a sampling clock is formed based on the framing code at the beginning of the data.
Sample and process data. This procedure may be a technique common to teletext receivers and the like. The same applies to audio data processing, and instead of the framing code, the _fH pulse output from the 1/2 frequency divider circuit 29 may be used as the time reference.

In addition, the horizontal synchronization signal and the vertical synchronization signal are obtained by dividing the output of the 1/3 frequency divider circuit 27 and dividing the output of the frequency divider circuit 28 to 3.
It is formed from the output of 1, but as mentioned above, horizontal and
Since the frequency-divided output is used as the vertical period operation reference pulse unless there is a large phase difference with the horizontal/vertical trigger signal, there is an advantage that jitter does not occur.

Note that the configuration of each phase monitoring circuit 53, 52 may be a high-speed CPU or a hard logic.

Effects of the Invention As described above, according to the present invention, the following effects can be obtained.

(1) After detecting the vertical trigger signal, the color burst signal is gated by a gate pulse created based on the color burst signal itself, so it is resistant to noise.

(2) Since the synchronization signal is reproduced by combining the output of the frequency dividing circuit and the output of the vertical synchronization signal generation circuit, the amount of jitter is extremely small compared to when the synchronization generation circuit is driven by an ordinary LSI. , can reproduce stable synchronization signals.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an overview of a receiving device that can use a signal processing device according to an embodiment of the present invention, FIG. 2 is a waveform diagram of a signal during the horizontal blanking period of the same device, and FIG. 4 is a block diagram showing the signal decoding section of the same device, FIG. 5 is a block diagram showing the synchronous reproducing section of the same device, and FIG. 6 is a block diagram showing the signal decoding section of the same device. 7 is a block diagram showing details of the synchronous playback section in the same device, FIGS. 8 and 9 are waveform diagrams showing signals of each part in the same device, and FIG. 10 is a flowchart showing the synchronous playback procedure in the same device. FIG. 11 is a circuit diagram showing the burst gate pulse generation circuit of the device, and FIG. 11 is a waveform diagram of each part thereof. 1... Tuner, 2... VIF circuit, 3... Detection circuit, 4... Synchronous playback circuit, 5... Video processing circuit, 6... Data processing circuit, 7... RF remodulation circuit, 8... Video Buffer, 9, 11... Clamp circuit, 10... Synthesis circuit, 12... Slice circuit, 13... Sampling circuit, 14, 18, 2
0... Buffer memory, 21... D/A converter, 15... Code decoding circuit, 16... Inverting switching circuit, 17... Inverting amplifier, 19... Demodulator, 22
...H _T , V _T ...detection circuit, 23 ...f _sc regeneration circuit,
24...PLL circuit, 25...12f _sc /VCO, 26
...1/5 frequency divider circuit, 27...1/3 frequency divider circuit, 28...
...1/455 frequency divider circuit, 29...1/2 frequency divider circuit, 30...
...1/525 frequency divider circuit, 31...equalization pulse generation circuit,
32...Vertical synchronization signal generation circuit, 33...Sampling clock generation circuit, 34...Burst gate formation circuit, 35...Synchronization playback circuit, 36...Video clamp and inversion circuit, 37...Video synthesis circuit, 38 ... Band pass amplifier, 39 ... Vertical burst detection circuit, 40 ... V _T sampling circuit, 41 ...
... Vertical clamp pulse generation circuit, 42 ... Flip-flop, 43 ... Monostable multivibrator, 44 ... AND gate, 45 ... OR gate,
46...Integrator circuit, 47...Clamp circuit, 48
...Slice circuit, 49...AND gate, 50
... Monostable multivibrator, 51 ... Flip-flop, 52 ... Horizontal phase monitoring switching circuit, 5
3... Vertical phase monitoring circuit, 54... Decoder,
55...Band pass amplifier, 56...Color burst detection circuit, 57...Pulse generation circuit, 58...
...H _T extraction circuit, 59...Pulse generation circuit, 60
...Horizontal AFC oscillation circuit, 61...Pulse generation circuit, 62...Burst extraction circuit, 63...f _sc・
AFPC circuit.

Claims (1)

[Claims] 1. A video signal whose polarity is randomly inverted or non-inverted and encrypted, and a video signal which is inserted in different numbers of groups in odd and even fields during the vertical retrace period and which is 10 times the horizontal scanning frequency. a vertical burst signal with a frequency equal to or higher than that, a vertical trigger signal and a horizontal trigger signal inserted during the vertical retrace period, audio data and decryption data inserted during the vertical retrace period, and a horizontal A circuit that receives a television signal from which a synchronization signal, a vertical synchronization signal, and a horizontal equalization pulse during a vertical retrace period have been removed, and detects the vertical burst signal, and a vertical trigger using the vertical burst signal output from this detection circuit. The signal detection circuit and the output of an amplifier tuned to the color subcarrier generate a pulse of the horizontal scanning period using a continuous multi-cycle color subcarrier, and this pulse is delayed to generate an even number of color subcarrier burst signals. A circuit that resets the frequency divider that divides the signal of twice the frequency and forms a gate pulse to extract the color subcarrier burst signal, and synchronizes the frequency and phase of the color subcarrier oscillator with the extracted color subcarrier burst signal. a circuit that divides the frequency of the synchronized color subcarrier and an even multiple of the color subcarrier burst signal to generate a vertical synchronization signal reproduced from the vertical trigger signal and a horizontal synchronization signal reproduced from the horizontal trigger signal. a circuit for synchronizing a phase with a phase of a color subcarrier.