JPH0572781B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Prior Art] The present invention relates to a timing matching circuit, and particularly to a timing matching circuit with a simple configuration for adjusting timing deviations of a plurality of binary signals.

[Prior art]

In digital communications, it is often necessary to align the timing of multiple digital signals. For example, two signals transmitted separately may be switched in synchronization, or a plurality of time-divided signals may be combined and multiplexed after timing adjustment. As an example of the latter,
There is a signal transmitting/receiving circuit for a time division multi-directional multiplex communication system disclosed in Japanese Patent Application Laid-Open No. 57-143953.
This circuit is a circuit that directly connects communication between slave stations in a multi-directional multiplex wireless communication system without going through the terminal device of the master station, and as a timing matching circuit for this purpose, as will be described in detail later, Conventionally, a circuit consisting of a random access memory (RAM), a write address signal generation circuit, a read address signal generation circuit, and a selection circuit has been used, which has the disadvantage that the configuration is somewhat complicated.

[Purpose of the invention]

An object of the present invention is to eliminate the drawbacks of the conventional circuits described above and provide a timing matching circuit with a simple configuration.

[Structure of the invention]

The timing matching circuit of the present invention includes a first-in, first-out buffer memory (abbreviated as FIFO memory) that temporarily stores an input signal consisting of a binary code string and a timing pulse that provides a time reference for this input signal in parallel, and a first-in, first-out buffer memory (abbreviated as FIFO memory) that reads data from the FIFO memory. A read control that logically processes the output of the timing pulse and a reference pulse that is a reference for timing alignment, stops reading from the FIFO memory when the two do not match, and restarts the read operation when the two match. and a circuit.

〔Example〕

Next, the present invention will be explained in detail with reference to the drawings.
Before describing embodiments of the present invention, a conventional timing matching circuit exemplified in the above-mentioned Japanese Unexamined Patent Publication No. 57-143953 will be described first. FIG. 1 is a block diagram of the conventional circuit described above, which consists of a RAM 1, a write address signal generation circuit (W-ASG) 2, a read address signal generation circuit (R-ASG) 3, and a selection circuit (SEL) 4. has been done. In FIG. 1, a frame synchronization pulse 102 extracted from a time division input signal 101 by a frame synchronization circuit (F-SYNC) 5 is added to a W-ASG 2 for write control, and the input signal is 101 is written to RAM1. On the other hand, the signal written in this RAM1 is the frame synchronization pulse 104 of the other time-division signal to be combined.
The signal is read out using the read address 105 from the R-ASG 3 controlled by the R-ASG 3, and a timing-aligned signal output 106 is obtained. SEL4 is a switching circuit that alternately selects the address signal 103 for writing to RAM1 and the address signal 105 for reading within one time slot and supplies it to RAM1.
7 is a clock signal.

FIG. 2 is a block diagram of an embodiment of the present invention.
It consists of a FIFO memory (FIFO) 6 and a control circuit (CONT) 7 that controls reading of the FIFO 6. An input input signal 101 and a frame synchronization pulse 102 branched from this input signal by F-SYNC5 are written to FIFO6 by a clock signal 107, and a read pulse 108 from CONT7 is written.
It is designed to be read by. CONT7
is the frame synchronization pulse output 109 of FIFO6,
This is a circuit that logically processes the frame synchronization pulse 104 of the other party's signal to perform timing alignment, stops the readout pulse 108 if they do not match, and sends out the readout pulse again when they match, for example as shown in FIG. It can be constructed with a simple circuit.

In FIG. 3, AND gate 71 has an opening/closing gate that opens and closes clock pulse 107, and FIFO
When frame sync pulse output 109 from 6 is applied, if frame sync pulse 104 is not present, flip-flop 72 is set and AND gate 71 is closed to stop read pulse 108 and readout. When reading is stopped, the frame synchronization pulse output 109 from the FIFO 6 is held as it is, so when the frame synchronization pulse 104 comes, the flip-flop 72 is reset and the AND gate 71 is opened to resume reading. AND gate 73 and EX-OR gate 74 are circuits to prevent a set signal from being applied to flip flip 72 when both pulses match, and after reading resumes, normal operation will occur unless the timing of both pulses deviates. The read operation continues. As is clear from the above description, the circuit shown in FIG. 2 has a much simpler configuration than the conventional circuit shown in FIG. 1, and has a similar timing matching function.

In the explanation of the above embodiment, a case has been described in which timing alignment is performed using a frame synchronization pulse in order to synthesize and multiplex time-division signals. It is not limited to synchronous pulses. In addition, the embodiment shown in Fig. 2 has FIFO6
The reading and writing of CONT is performed at the same clock frequency.
If the read clock frequency applied to 7 is n times the write clock frequency, the continuous input signal of FIFO 6 at the same time as timing alignment is 1/n.
Burst conversion can be performed to compress the signal into a burst signal of time. Furthermore, the input timing pulse and the reference pulse are not necessarily limited to a one-to-one correspondence; for example, the input timing pulse and the reference pulse may have an m-to-one correspondence (m<n) in a circuit equipped with the above-mentioned burst conversion function. Third
If the control circuit shown in the figure is configured by adding a circuit that does not set the flip-flop 72 for the next m-1 timing pulses when the first pulse matches, the continuous signal can be made m/n with timing matching with the reference pulse. A timing matching circuit with a burst conversion function that compresses the signal into a burst signal of time can be obtained.

〔Effect of the invention〕

As explained in detail above, according to the timing matching circuit of the present invention, the timing pulse is temporarily stored in the FIFO together with the input signal, and reading from the FIFO memory is stopped until the output of the timing pulse matches the reference pulse. This has the advantage that a timing matching circuit can be configured with a simple configuration.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a conventional timing matching circuit, FIG. 2 is a block diagram of an embodiment of the present invention, and FIG. 3 is a block diagram of an embodiment of the control circuit of FIG. 1...Random access memory (RAM), 2
...Write address signal generation circuit (W-
ASG), 3... Read address signal generation circuit (R-ASG), 4... Selection circuit (SEL), 5... Frame synchronization circuit (F-SYNC), 6... First-in first-out buffer memory (FIFO), 7... ...Control circuit (CONT), 71, 73...AND gate, 72
...Flip-flop, 74...EX-OR gate.

Claims (1)

[Claims] 1. A first-in, first-out buffer memory that temporarily stores two systems of signals in parallel: an input signal consisting of a binary code string and a timing pulse that provides a time reference for this input signal, and the output and timing of the timing pulse read from this first-in, first-out buffer memory. The present invention is characterized by comprising a read control circuit which logically processes a reference pulse serving as a reference for matching, stops reading from the first-in first-out buffer memory when the two do not match, and restarts the read operation when the two match. timing matching circuit.