JPH057353A - Video display device - Google Patents

Abstract

PURPOSE:To save power consumption equal to that a fringe display circuit is eliminated when fringing is not performed in spite of having the fringe display circuit. CONSTITUTION:An address selecting circuit 26 receives a fringe presence/absence signal F and if the instruction which indicates no fringing is given by the signal F, an address signal L is generated only once during the period T0. If a serial conversion circuit 28 receives the signal F which indicates no fringing, a shift registers 8a and 8c stop receiving set signals SPH and PSL and a dot clock D.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video display device, and more particularly to a video display device such as a television, a VTR, a video camera or the like which superimposes a pattern of bordered characters and titles.

[0002]

2. Description of the Related Art FIG. 3 is a block diagram centering on a character video signal generating circuit portion of a conventional video display device. The character video signal generation circuit 13 includes a display data RAM 5 that can store codes (hereinafter referred to as character codes) of all characters that are temporarily displayed on the screen.

In order to write the character code "W" sent from the microcomputer 1 into the display data RAM 5, this circuit comprises a write address register 2, a write data register 3, a write synchronizing circuit 4 and an address selecting circuit 6. Is equipped with. Upon receiving the control and data signal B from the microcomputer 1, the write address register 2 holds the address "A" and the write data register 3 holds the character code "W". The write synchronization circuit 4 generates a write synchronization signal S, and in response to this write synchronization signal S, the address selection circuit 6 displays data RAM.
Address signal U to 5 is generated.

The character code "G" to be displayed
In order to read from the display data RAM 5, the character video signal generation circuit 13 includes a vertical address counter 12, an oscillation circuit 11, and a horizontal address counter 10. The vertical address counter 12 receives a vertical synchronizing signal V for synchronizing with a scanning line and a horizontal synchronizing signal H to generate a row selecting signal R, and a row selecting signal for determining a vertical position on a display screen. R is sent to the address selection circuit 6. The oscillation circuit 11 receives the horizontal synchronizing signal H and generates a dot clock D in which the phase of the generated signal is synchronized with the horizontal synchronizing signal H in order to take timing during horizontal scanning. The horizontal address counter 10 receives the horizontal synchronizing signal H and the dot clock D and generates a digit selecting signal C for determining the horizontal position on the display screen. The digit selecting signal C is sent to the address selecting circuit 6 and the write synchronizing circuit 4. To send.

Furthermore, the selected character code "
The character video signal generation circuit 13 includes a character generator 7 and a serial conversion circuit 8 for displaying the G "pattern.
Receives the address signal L generated by the address selection circuit 6 and the selected character code "G", and the character pattern for one line of the pattern for one character "
Further, the serial conversion circuit 8 sequentially outputs the character pattern "P" consisting of a plurality of bits for one row, one dot at a time, in accordance with the dot clock D.

The serial conversion circuit 8 further has a circuit 8d (see FIG. 2B) for generating a framed pattern "Y", and synthesizes the framed character pattern with another video signal E. It can also be displayed on the CRT 9.

The operation of writing the character code "W" sent from the microcomputer 1 in the display data RAM 5 in the character video signal generating circuit 13 having such a configuration will be described.

When the microcomputer 1 sends the character code "W" to be written in the display data RAM 5 to the write data register 3 according to the control and data signal B, the write data register 3 holds the character code "W" in response to this. Output. Character code ”
Address "A" of display data RAM5 where W "is to be written
Is sent to the write address register 2 according to the control and data signal B, the write address register 2 holds the address "A" and outputs it on the address signal A. The microcomputer 1 sends a control signal indicating that the write address register 2 holds the address "A" and the write data register 3 holds the character code "W" to the write synchronizing circuit 4 according to the control and data signal B, Upon notifying that the writing is ready, the writing synchronizing circuit 4 tries to output the writing synchronizing signal S for writing the writing.

However, at this time, the character code "G" for display selected by the address signal U generated by the address selection circuit 6 which receives the row selection signal R and the digit selection signal C is read from the display data RAM 5. Is performed in synchronization with the horizontal sync signal H and the vertical sync signal V, the write sync circuit 4 avoids the timing at which the character code "G" is read and avoids the character code "
During unnecessary horizontal blanking and vertical blanking of G ",
The write synchronization signal S is output. In response to the write synchronization signal S, the address selection circuit 6 selects the address signal A, outputs the address "A" on this signal A as the address signal U to the display data RAM 5, and sets it to the address "A" in the display data RAM. The character code "W" is written.

The operation of the circuit for selecting and reading the character code "G" to be displayed from the display data RAM 5 will be described. The vertical address counter 12 receives the vertical synchronizing signal V to initialize the count value, receives the horizontal synchronizing signal H to advance the count value, and outputs the row selection signal R for determining the vertical position of the scanning line. . The oscillator circuit 11 is
Upon receiving the horizontal synchronization signal H, the oscillation phase is synchronized, and the dot clock D having a frequency corresponding to the horizontal scanning speed of the scanning line is generated and output. Horizontal address counter 10
Receives the horizontal synchronizing signal H, the count value is initialized,
Upon receiving the dot clock D, the count value is advanced, and the digit selection signal C for determining the horizontal position of the scanning line is output. The row selection signal R and the digit selection signal C thus generated are input to the address selection circuit 6, and the address signal U to the display data RAM and the character generator 7 are input.
And the address signal L to the memory cell are calculated and generated and output according to the respective storage forms.

The display data RAM 5 receives the address signal U, reads the character code "G" stored in advance at the address designated thereby, and outputs it to the character generator 7. Character generator 7
May be a ROM storing a character pattern, which receives the character code "G" and corresponds to the code 1
A character pattern (matrix-shaped configuration) is selected, and further, in response to the address signal L, a character pattern "P" for one line of the pattern for one character is output.

In order to generate the edging pattern, the patterns of the upper and lower rows are also required, and the patterns for the three rows are required in total. Therefore, for example, when the value of the address signal L is "N", the character pattern to be displayed is displayed. If it indicates, the value of the address signal L within the time for scanning the width of one character is "N", "1" is calculated, and "(N-1)", "
N "and" (N + 1) "are changed, and the character patterns for three lines of the pattern for one character are read (see FIG. 2).
(See (a)).

To do so, the address selection circuit 6 receiving the digit selection signal C scans the width of one character pattern as T0, and the time of T0 is T0.
1, T2, T3, T4. During the period T1, the address selection circuit 6 sends the read address "Q" generated from the row selection signal R and the digit selection signal C to the display data RAM 5 as the address signal U. As a result, the character code "G" stored in the address "Q" of the display data RAM 5 is read.

In the period of T2, the character pattern of the row adjacent to the row "N" to be scanned is read in order to generate the framing pattern "Y". Therefore, during this period, the address selection circuit 6 changes the address signal L to "(N-
1) "is output. In response to this and the character code" G ", the character generator 7 outputs" (N-1) ".
Use the character code "G" for the character pattern on the line
Is read from the matrix pattern. During the period T3, the character pattern "P" of the row "N" to be scanned is read in order to generate the rimming pattern "Y" and display the original character pattern "P". Therefore, during this period, the address selection circuit 6 outputs "N" to the address signal L at this timing. In response to this and the character code "G", the character generator 7
The character pattern of the Nth row, that is, the character pattern "P" is read from the matrix pattern of the character code "G". During the period of T4, the row "N" to be scanned is generated to generate the edging pattern "Y". The character pattern of the line next to is read, so during this period,
The address selection circuit 6 receives the address signal L at this timing.
"(N + 1)" is output to. In response to this and the character code "G", the character generator 7
The (N + 1) "th line character pattern is read from the matrix pattern of the character code" G ".

The serial conversion circuit 8 is a circuit mainly composed of a shift register for converting parallel data into serial data (see FIG. 2B).
However, 28e, 28f, 28g and 28h gates are excluded). This circuit has three shift registers 8a, 8b and 8c for processing the character patterns of three lines required for generating the edging pattern. In each of the shift registers 8a, 8b, 8c, the character pattern sent from the character generator 7 at the timing of T2, T3, T4 is converted into each of the timing signals SPH,
Latches in parallel according to SPM and SPL. Then, in response to the dot clock D, the character pattern "
P "and the edging pattern" Y "generated by the edging generation circuit 8d are serially output dot by dot as the signal p and the signal y. In this manner, the edging generated from the pattern without edging is added. The pattern is displayed on the screen.

The video signal generated by the character video signal generation circuit 13 and sequentially output dot by dot is combined with another video signal E and displayed on the CRT 9. In the combined and displayed screen, for example, when the character pattern is displayed in white and the background is also white, it is difficult to distinguish the character pattern without edging, but the edging described above is black. When this is done, the character pattern is emphasized and becomes easy to see regardless of the state of the background.

Although the example of the character video signal generation circuit has been described in detail above, the title video signal generation circuit will be described. FIG. 5 is a block diagram centering on a title video signal generation circuit portion of a conventional video display device. The configuration of the title video signal generation circuit 53 of FIG. 5 is different from that of the character video signal generation circuit 13 of FIG. 3 in that there is no character generator 7 and that the display data RAM 55 is not a character code but title data (title image). (Pixel data of) is stored.
Correspondingly, the bit pattern WW of the title data replaces the character code W, and the address selection circuit 56 generates the address signal UL to the display data RAM 55 instead of generating the address signal L and the address signal U. Instead of the character pattern P, the title data GP output from the display data RAM 55 is sent to the serial conversion circuit 8.

The operation of the title video signal generation circuit 53 having such a configuration will be described in detail below, but is the same as the character video signal generation circuit 13 except for the operation related to the character generator 7. Address selection circuit 56 of this configuration
Receives the digit selection signal C, sets the period for scanning the width of one title data as T0, and the time of this T0 is T5, T6, T
Divide into 3 of 7. Here, the number of title data displayed in one horizontal line is m.

During the period of T5, the edging pattern "YY".
To read the title data of the line before the line "M" to be scanned. Therefore, during this period, the address selection circuit 56 changes the address signal UL to "
"(M-m)" generated by operating "m" on M "is output. In response to this, the display data RAM 55 displays" (M-m) ".
-M) The title data of the "row" is output. During the period of T6, the rimming pattern "YY" is generated and the row "M" to be scanned is displayed in order to display the original title data "GP".
The title data "GP" of the line is read. Therefore, during this period, the address selection circuit 56 outputs "M" to the address signal UL at this timing. In response to this, the display data RAM 55 displays the title data "G" in the "M" row.
P "is output. During the period of T7, the framing pattern" Y "is output.
The title data of the row after the row "M" to be scanned is read to generate Y ". Therefore, during this period, the address selection circuit 56 outputs the address signal UL at this timing.
, "M" is calculated by "m" to generate "(M +
m) ”is output. In response to this, the display data RAM 55
Outputs the title data of the "(M + m)" line.

Such a character video signal generation circuit 1
3 and the respective constituent elements of the title video signal generation circuit 53, CMOS ICs with low power consumption are frequently used to save the power consumption of the entire apparatus. However, as described above, in order to perform framing, the display data R
It is necessary to access the AM and the character generator at high speed. Therefore, the CMOS device which consumes power mainly at the time of switching is operated at a higher frequency than in the case where framing is not performed. Therefore, when a circuit for framing display is provided, the effect of using the CMOS IC is weakened, and there is a problem that the power consumption is not sufficiently saved in the image display device having the conventional structure.

[0021]

However, in order to maintain the commercial value of the image display device, the frame display function is essential, and the circuit for frame display cannot be omitted.
On the other hand, in a portable image display device, especially in a battery-operated integrated video camera, saving power consumption is an urgent task because it leads to a reduction in the weight of the device and a long-term operation, which increases the commercial value. An object of the present invention is to solve the above-mentioned problems of the prior art. Even when a circuit for framing display is provided, a circuit for framing display is omitted when framing is not performed. The present invention provides a video display device that saves power consumption as much as the conventional one and has high commercial value.

[0022]

To achieve this object, a video display device according to the present invention has an address selection circuit and a serial conversion circuit in a conventional character video signal generation circuit and title video signal generation circuit. Some of the circuits are not activated when framing is not performed. The address selection circuit for this purpose receives a framing presence / absence signal from the microcomputer, and when this signal is instructed not to perform framing, a value (“1”) to be added or subtracted to calculate the address of the adjacent (front and back) rows. Alternatively, "m") is fixed to "0" and the address signal is generated only once in a predetermined period (T0). When the serial conversion circuit receives the framing presence / absence signal and is instructed not to frame by the signal, the serial conversion circuit sends character pattern or title data to two sets of the three sets of shift registers. The operation is stopped by stopping the supply of the set signal or the clock signal.

[0023]

According to the above configuration, even if the circuit has a circuit for displaying the frame, it is possible to sufficiently save the power consumption as compared with the case where the frame is displayed. Show. First, the common operation of the character video signal generation circuit and the title video generation circuit will be shown. The address selection circuit in this circuit has three sets of addresses ("N-1", "N", "when performing framing.
N + 1 ”or“ M-m ”,“ M ”,“ M + m ”) is generated. However, when framing is not performed, a value (“ 1 ”or“ m ”) to be added or subtracted to calculate an address.
Is fixed to “0” and calculation is performed. Even if "0" is adjusted,
Since the value of the operation result does not change, only one set of addresses (“N” or “M”) is generated, that is,
The calculation for generating the address signal is performed only once in a predetermined period. Therefore, since the value of the element corresponding to the address calculation in the circuit changes only once during this period, the number of times of switching for address generation and output is 1
/ 3. Here, CMO which is often used for circuit elements
Since the IC of S mainly consumes power at the time of switching, the power consumption for address generation in the address selection circuit is almost 1/3 due to the reduction in the number of switching times.
Is reduced to.

In the serial conversion circuit in this circuit, when framing is performed, a set of three shift registers sets the character pattern from the character generator or the display data at respective timings according to the set signal from the address selection circuit. Receive title data from RAM. Then, in accordance with the dot clock from the oscillation circuit, the three parallel data are converted into three columns of serial data and sent to the edging generation circuit. The framing generation circuit receives the serial data of these three columns and generates a framing pattern. However, in the case of no framing, the above three columns of serial data are not all required, and only one column of serial data is required. Therefore, only one set of shift registers has the timing corresponding to the set signal.
It receives a character pattern or title data, converts one set of parallel data into one column of serial data according to the dot clock, and outputs it for display. During this period, supply of the set signal and the clock signal to the other two sets of shift registers is stopped. The shift register does not receive parallel data unless the set signal is supplied, and the held data is not shifted unless the clock signal is supplied.
The value is fixed and does not change. Therefore, 2 out of 3 sets
Since the pair of shift registers does not switch, and the circuit is mainly composed of CMOS that consumes power only at the time of switching, the power consumption in the serial conversion circuit is also reduced to about 1/3.

As described above, in the image display device of the present invention, when the framing presence / absence signal indicates that no framing is performed, the address selection circuit and the serial conversion circuit correspondingly perform extra framing. Since it does not operate properly, the power consumption in the character video signal generation circuit and the title video generation circuit having the circuit for framing is sufficiently reduced to the level of the power consumption of the circuit without the circuit for framing. be able to.

[0026]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a block diagram centering on a character video signal generation circuit portion of a video display device according to an embodiment of the present invention, and corresponds to FIG. 3 showing a conventional example. FIG. 2A shows a character pattern,
It is an example of a framing pattern that surrounds dots on the top, bottom, left and right.
FIG. 2B is one of the specific examples of the main part of the serial conversion circuit of the present invention. FIG. 4 is a block diagram centering on the title video signal generation circuit portion of the video display device of one embodiment of the present invention, and corresponds to FIG. 5 showing a conventional example.

In the configuration of the serial conversion circuit 28 of this embodiment, the input terminal LD of the shift register 8b directly receives the set signal SPM as in the conventional case. However, the input terminals LD of the shift registers 8a and 8c are connected to the set signal S
Instead of receiving the PH and SPL directly, the gate 28g,
28h output is received. The gate 28g receives the set signal SPH at one input terminal, the gate 28h receives the set signal SPL at one input terminal, the framing presence / absence signal F at the other terminal, and ANDs these signal values, that is, The set signal masked by the framing presence / absence signal F is output to the input terminal LD. Further, the input terminal CLK of the shift register 8b is the dot clock D
Receive directly. However, the input terminals CLK of the shift registers 8a and 8c do not receive the dot clock D directly, but receive the outputs of the gates 28e and 28f. Gate 2
8e and 28f receive the dot clock D at one input terminal, receive the framing presence / absence signal F at the other terminal, take the AND of these signal values, that is, the clock signal masked by the edging presence / absence signal F, Output to the input terminal CLK. (See FIG. 2 (b)).

With such a configuration, when the frame is not framed, the supply of the set signals SPH and SPL and the clock signal, that is, the dot clock D to the shift registers 8a and 8c is stopped by being masked by the frame presence / absence signal F. Therefore, two of the three shift registers do not switch, and the power consumption in the serial conversion circuit is reduced.

The operation of the character video signal generation circuit of the present invention will be described with reference to the configuration of FIG. When edging is performed, the operation is similar to that of the conventional example. Therefore, there will be described a part that is different from the conventional example even when the frame is not framed. The address selection circuit 26 of the present invention does not generate the addresses "N-1" and "N + 1" of the adjacent row when receiving the framing presence / absence signal F from the microcomputer and instructed by the signal F not to perform framing. Therefore, the address output on the address signal L in the period T0 is "N".
Only.

Therefore, during the period T1, the address selection circuit 26 sends the read address "Q" generated from the row selection signal R and the digit selection signal C to the display data RAM 5 as the address signal U. As a result, the character code "G" stored in the address "Q" of the display data RAM 5 is read.

During the period of T2, the address selection circuit 26
Outputs "N" to the address signal L. In response to this and the character code "G", the character generator 7 reads the character pattern "P" of the "N" th row from the matrix pattern of the character code "G". However, since the set signal SPH is masked by the framing presence / absence signal F, this character pattern "
P "is not received by the shift register 8a of the serial conversion circuit 28. During the period of T3, the address selection circuit 26 continues to output" N "to the address signal L. Therefore, the character generator 7 also outputs the character. The pattern "P" continues to be output, and only the character pattern "P" is received by the shift register 8b of the serial conversion circuit 28 according to the set signal SPM and used for image output. The address selection circuit 26 continues to output “N” to the address signal L. Therefore, the character generator 7 also continues to output the character pattern “P.” However, the set signal SPL is masked by the framing presence / absence signal F. Therefore, this character pattern "P" also shifts the serial conversion circuit 28. Not received by the register 8c. In this way, the frequency of operation of the address selecting circuit 26 and the character generator 7 is suppressed, power consumption is reduced.

The operation of the title video signal generation circuit of the present invention will be described with reference to the configuration of FIG. Also in this circuit, when framing is performed, the operation is similar to that of the conventional example. Therefore, there will be described a part that is different from the conventional example even when the frame is not framed. Address selection circuit 4 of the present invention
6 receives the framing presence / absence signal F from the microcomputer, and when this signal F is instructed not to perform framing, it does not generate the addresses "M-m" and "M + m" of the preceding and succeeding rows. The address output on the signal is only "M".

During the period of T5, the address selection circuit 46
Outputs "M" to the address signal UL. In response to this, the display data RAM 55 outputs the title data "GP" of the "M" line. Even during the period T6, the address selection circuit 46 continues to output "M" as the address signal UL. In response to this, the display data RAM 55 also continues to output the title data "GP" of the "M" line. Only the title data "GP" is received by the shift register of the serial conversion circuit 48 according to the set signal SPM and used for video output. Even during the period T7, the address selection circuit 46 continues to output "M" as the address signal UL. In response to this, the display data RAM 55 also
Continuing to output title data "GP" of the M "line,
This title data "GP" is not received by anything.
In this way, the address selection circuit 46 and the display data R
The frequency of operation of the AM 55 is suppressed, and power consumption is reduced.

As described above, in the character video signal generating circuit, the address selecting circuit generates the address signal to the character generator only once in the predetermined period when the framing presence / absence signal is not used. As a result, even in the character generator that receives this address signal, the control circuits such as the address decoder and the output buffer included in the character generator operate only once. Therefore, even in the character generator
The number of times of switching is reduced to 1/3, and as a result, the power consumption is reduced to almost 1/3.

Further, in the title video signal generation circuit, the address selection circuit generates the address signal to the display data RAM only once in a predetermined period when the frame is not framed by the frame presence / absence signal. As a result, in the display data RAM receiving this address signal, the control circuit such as the address decoder and output buffer included in the display data RAM operates only once. Therefore, even in the CMOS display RAM of the title video signal generation circuit, the number of switching times is reduced to 1/3, and as a result,
Power consumption is reduced to almost 1/3.

Although the character video signal generation circuit and the title video signal generation circuit have been described in detail above, the video display device of the present invention is not limited to having only one of these circuits, but both circuits. May be included.

[0037]

As described above, the video display device of the present invention has a circuit for framing display by simple modification of the circuit, but when the framing is not performed, the framing display is performed. It is possible to suppress unnecessary operations of related circuits. As a result, it is possible to save power consumption almost as much as the case where the circuit for framing display is omitted, and in particular, in the case of a battery-driven device, there is an effect that the weight can be reduced and the device can be driven for a long time.

[Brief description of drawings]

FIG. 1 is a block diagram centering on a character video signal generation circuit portion of a video display device according to an embodiment of the present invention.

FIG. 2 is an example (a) of a character pattern in an image display device, a framing pattern generated from the character pattern and surrounding upper, lower, left, and right dots, and a detailed block diagram (b) of a serial conversion circuit of the present invention.

FIG. 3 is a diagram showing a configuration of a conventional image display device, and particularly a block diagram of a character image signal generation circuit portion.

FIG. 4 is a block diagram centering on a title video signal generation circuit portion of the video display device of one embodiment of the present invention.

FIG. 5 is a diagram showing a configuration of a conventional video display device, and particularly a block diagram of a title video signal generation circuit portion.

[Explanation of symbols]

1 microcomputer 2 Write address register 3 Write data register 4 Write synchronization circuit 5 Display data RAM 6 Address selection circuit 7 character generator 8 Serial conversion circuit 9 CRT 10 Horizontal address counter 11 oscillator circuit 12 Vertical address counter 13 Character video signal generation circuit 23 Character video signal generation circuit 26 Address selection circuit 28 Serial conversion circuit 43 Title video signal generation circuit 46 Address selection circuit 53 Title video signal generation circuit 55 Display data RAM 56 address selection circuit

Claims (2)

[Claims] 1. A first address signal is generated once during a period in which a row selection signal for defining a vertical position on a display screen and a digit selection signal for defining a horizontal position are received and a width for one character is scanned. A CMOS address selection circuit that generates a second address signal three times, and a display that stores all displayed character codes and reads out and outputs the character code stored at the address indicated by the first address signal. A data generator and a character generator which receives the character code and selects a corresponding one-character matrix pattern, and receives a second address signal and outputs the corresponding one-row character pattern from the matrix pattern. And a set of three obtained in response to the three generations of the second address signal required to generate the edging pattern In a video display device, comprising: a serial conversion circuit that receives and holds the character pattern by at least a set of three CMOS shift registers, and sequentially outputs one dot for each dot clock, the address selection circuit includes a microcomputer. When a framing presence / absence signal from the device is received and the signal indicates that edging is not performed, the value to be adjusted to generate the second address signal is fixed, and the second address signal is generated only once. The serial conversion circuit receives the framing presence / absence signal, and when the signal is in a non-framing state, the operation of two shift registers of the three shift registers is stopped. 2. A CMOS address selection circuit which receives a row selection signal for defining a vertical position and a digit selection signal for defining a horizontal position on a display screen and generates an address signal three times during a period for scanning the width of one title data. A circuit, a CMOS display data RAM for storing all displayed title data and reading out and outputting the title data stored at the address indicated by the address signal from the circuit, and the address signal for generating the framing pattern. A serial conversion circuit that receives and holds at least three sets of the title data obtained in response to the three times of generation by one set of CMOS shift registers, and sequentially outputs one dot at every dot clock. In the image display device, the address selection circuit receives a framing presence / absence signal from a microcomputer, When it is instructed not to be framed by the signal of, the value to be adjusted for generating the address signal is fixed during the period for scanning the width of one title data, and the address signal is generated only once, The serial conversion circuit receives the framing presence / absence signal, and when the signal is in a non-framing state, the operation of two shift registers of the three shift registers is stopped. .