JPH0575113A - Insulated gate type thyristor - Google Patents

Abstract

(57) [Abstract] [Purpose] An object is to provide an insulated gate thyristor with improved turn-off capability. A p-type base layer 2 is formed on one surface of an n-type base layer 1, and a p-type emitter layer 4 is formed on the other surface. p
An n-type emitter layer 5 and an n-type source layer 6 adjacent to the n-type emitter layer 5 are formed on the surface of the type base layer 2. On the p-type base layer 2 in the region sandwiched by the n-type emitter layer 5 and the n-type source layer 6, a gate electrode 8 is formed via a gate insulating film 7 to form an n-channel MOSFET. The cathode electrode 9 is formed only in contact with the n-type emitter layer 5, and the control electrode 13 is formed on the p-type base layer 2. An anode electrode 10 is formed on the p-type emitter layer 4.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an insulated gate thyristor which is turned off by an insulated gate electrode.

[0002]

2. Description of the Related Art As one of the insulated gate thyristors, there has been proposed a structure in which a MOSFET is inserted between a cathode / emitter layer and a cathode electrode (BJ Balig).
a, Proceeding of 1990 Alternative Symposium
on Power Semiconductor Devices & ICs p117
-121). This insulated gate thyristor is
(Emitter Switched Thyrister).

FIGS. 10 (a) and 10 (b) are a cathode side layout and a sectional view taken along the line AA 'showing the structure of the main part of the EST. An n-type emitter layer 5 is formed on the surface of the p-type base layer 2, and an n-type source layer 6 is formed adjacent to the n-type emitter layer 5.
A gate electrode 8 is formed between the n-type emitter layer 5 and the n-type source layer 6 with a gate insulating film 7 interposed therebetween, and a MOS electrode is formed.
The FET is configured. The cathode electrode 9 is provided not in contact with the n-type emitter layer 5 but in contact with the n-type source layer 6. Below the n-type source layer 6,
A high-concentration p-type layer 11 is diffused to prevent the parasitic thyristor operation at the time of turn-off, and the cathode electrode 9 is in contact with the p-type layer 11 simultaneously with the n-type source layer 6.

To turn on this thyristor, a positive voltage is applied to the gate electrode 8 with respect to the cathode, and the MOSFE is turned on.
This is done by turning on T. As a result, the n-type emitter layer 5 has the n-type channel and the n-type channel under the gate electrode 8.
It is connected to the cathode electrode 9 via the mold source layer 6. The turn-off is performed by turning off the MOSFET and separating the n-type emitter layer 5 from the cathode electrode 9.

As described above, in the conventional structure shown in FIG. 10, turn-off is performed only by interrupting the current path when turned on by the MOSFET. Therefore, excess minority carriers in the element are not positively sucked out to the external circuit, and are consumed only as recombination current or diffusion current, so that the turn-off capability is low.

[0006]

As described above, the conventional E
The insulated gate thyristor called ST has a problem of low turn-off capability. The present invention has been made in view of the above points, and an object thereof is to provide an insulated gate thyristor having an increased turn-off capability.

[0007]

The present invention provides a high resistance first
Conductivity type base layer, second conductivity type base layer formed on the surface of the first conductivity type base layer, first conductivity type emitter layer formed on the surface of the second conductivity type base layer, and first conductivity type The base layer has a pnpn structure including a second conductivity type emitter layer formed apart from the second conductivity type base layer,
A first conductivity type source layer is formed on the surface of the second conductivity type base layer adjacent to the first conductivity type emitter layer, and the first conductivity type emitter layer and the first conductivity type source layer of the second conductivity type base layer are formed. In an insulated gate thyristor in which an insulated gate electrode is formed in a region sandwiched by, a first main electrode is formed in a first conductivity type source layer, and a second main electrode is formed in a second conductivity type emitter layer, The first main electrode is provided only in contact with the first conductivity type source layer, and the control electrode is provided separately from the second conductivity type base layer.

[0008]

According to the present invention, by applying a predetermined bias to the control electrode at the time of turn-off, excess minority carriers inside the element can be forcibly discharged to the outside, and thus an insulated gate type having a high turn-off capability. A thyristor is obtained.

[0009]

Embodiments of the present invention will be described below with reference to the drawings. In all the following examples, the first conductivity type is n.
The type and the second conductivity type are p-type, but they can be reversed.

FIG. 1 is a cathode side layout showing a main structure of an insulated gate thyristor according to an embodiment of the present invention and a sectional view taken along the line AA '. High resistance n-type base layer 1
The p-type base layer 2 is formed on one surface and n is formed on the other surface.
A p-type emitter layer 4 is formed via the type buffer layer 3. An n-type emitter layer 5 is diffused and formed on the surface of the p-type base layer 2, and an n-type source layer 6 is diffused and formed adjacent to the n-type emitter layer 5. On the p-type base layer 2 in the region sandwiched by the n-type emitter layer 5 and the n-type source layer 6, a gate electrode 8 is formed via a gate insulating film 7 to form an n-channel MOSFET.

The cathode-side surface on which each diffusion layer and the gate electrode are formed is covered with an oxide film 12, and a contact hole is opened in the oxide film 12 to contact the n-type source layer 6 with the cathode electrode 9 and the p-type base layer. The control electrode 13 that contacts the second electrode 2 is formed separately from each other. P
Below the n-type source layer 6 of the base layer 2 and the control electrode 13
A high-concentration p-type layer 11 is formed in the portion where is formed. An anode electrode 10 is provided on the p-type emitter layer 4 on the back surface.
Are formed.

The operation of the insulated gate thyristor thus constructed will be described with reference to FIG. In FIG. 2, VG is a voltage applied to the gate electrode 8, VB is a voltage applied to the control electrode 13, and IB is a base current. At the time of turn-on, a positive voltage is applied to the gate electrode 8 with respect to the cathode. As a result, the MOSFET becomes conductive and the n-type source layer 6 and the n-type emitter layer 5 are short-circuited. In this embodiment, a positive voltage is applied to the control electrode 13 to supply the base current, slightly after the gate voltage is applied. This allows for fast turn-on.

At the time of turn-off, before the bias of the gate electrode 8 is turned off, a negative voltage is applied to the control electrode 13 to extract the base current to some extent, the gate electrode 8 is set to zero, and the MOSFET is turned off. Fast pull-off is possible by pulling out the current.

Thus, in this embodiment, the MOSFET is
In addition to the voltage driving by, the current driving by the control electrode directly formed on the p-type base layer can be combined to turn on and off. Therefore, not only the turn-off ability can be improved, but also the high-speed turn-on operation becomes possible.

FIG. 3 is a cathode side layout of a more specific embodiment of the present invention, and FIGS. 4 and 5 are sectional views taken along lines AA 'and BB' of FIG. 3, respectively. The parts corresponding to those in the previous embodiment are designated by the same reference numerals as those in the previous embodiment, and detailed description thereof will be omitted. In this embodiment, a plurality of gate electrodes 8 are arranged in a stripe pattern, and a plurality of control electrodes 13 are arranged in a stripe pattern so as to intersect with the gate electrodes 8. In a region surrounded by the gate electrode 8 and the control electrode 13, a rectangular pattern n is formed.
The type emitter layers 5 and the n-type source layers 6 are alternately arranged along the longitudinal direction of the control electrode 13. That is,
Of the two pairs of opposite sides of the rectangular n-type emitter layer 5,
The MOSFET is formed adjacent to the pair of sides, and the control electrode 13 is formed adjacent to the other pair of sides. The contact portion 15 of the control electrode 13 with the p-type base layer 2 is arranged at a position adjacent to two opposite sides of the n-type emitter layer 5.

The cathode electrode 9 comprises a first layer electrode 91 and a second layer electrode
It has a two-layer structure of the layer electrode 92. First layer electrode 91
Are formed between the control electrodes 13 so as to run in parallel with the control electrodes 13. This first layer electrode 91 is an oxide film 1
It is connected to the n-type source layer 6 through a contact hole opened in 2. Then, with the control electrode 13 covered with the oxide film 14, a second layer electrode 92 (not shown in FIG. 3) is provided on the entire surface so as to connect the plurality of first layer electrodes 91. ..

According to this embodiment, the channel of the MOSFET is formed in contact with the two sides of the rectangular n-type emitter layer 5, and a sufficient channel width can be secured. As a result, low on-resistance and high-speed turn-on characteristics can be obtained. In addition, since the contact portion 15 of the control electrode 13 is arranged adjacent to the two sides of the rest of the rectangular n-type emitter layer, excess carriers are efficiently discharged at turn-off, and a high turn-off capability is obtained. The present invention can be implemented with various modifications. Corresponding to the cross section of FIG. 1B, FIGS. 6 to 9 show cross sectional structures of other embodiments.

FIG. 6 shows an embodiment in which the high concentration p-type layer 11 is formed so as not to be in direct contact with the n-type source layer 6. As a result, the pn junction breakdown voltage between the p-type base layer 2 and the n-type source layer 6 is increased, and a large reverse bias with respect to the n-type emitter layer 5 can be applied to the p-type base layer 2 by the control electrode 13. As a result, excess minority carriers can be efficiently discharged, and a higher turn-off capability can be obtained.

FIG. 7 shows an embodiment in which the breakdown voltage is improved by etching the junction end portions of the high-concentration p-type layer 11 and the n-type source layer 6 to form the groove 16. Also by this, the same effect as the embodiment of FIG. 6 can be obtained.

In FIG. 8, the diode 17 is inserted between the gate electrode 8 and the control electrode 13 with the polarity shown in FIG.
In this embodiment, the control electrode 13 and the control electrode 13 are integrated into one external control terminal T. In this case, as the diode 17, MOSF
If a device having a breakdown voltage smaller than the gate breakdown voltage of ET is used, when the gate electrode 8 is turned on and an excessive voltage is applied, the diode 17 is broken down to prevent the breakdown of the gate insulating film. At the time of turn-off, if a negative voltage is applied to the terminal T, the base current can be extracted through the diode 17. According to this embodiment, the external circuit is also simplified.

FIG. 9 shows an insulating film 18 under the n-type source layer 6.
It is an example in which the embedded structure is embedded. The insulating film 18 is, for example, a SIMOX film. According to this embodiment, the latch-up of the parasitic thyristor can be effectively prevented. Although not shown in the drawing, the present invention can be applied to a lateral thyristor in which the cathode emitter and the anode emitter are formed on the same surface of the substrate.

[0022]

As described above, according to the present invention, p
By providing the control electrode independent of the cathode electrode on the mold base layer, it is possible to provide an insulated gate thyristor with improved turn-off capability.

[Brief description of drawings]

FIG. 1 is a cathode side layout of an insulated gate thyristor according to an embodiment of the present invention and its AA ′ cross-sectional view.

FIG. 2 is a signal waveform diagram for explaining the operation of the insulated gate thyristor of the same example.

FIG. 3 is a cathode side layout view of an insulated gate thyristor of another embodiment.

4 is a sectional view taken along the line AA ′ in FIG.

5 is a sectional view taken along line BB ′ of FIG.

FIG. 6 is a sectional view of an insulated gate thyristor of another embodiment.

FIG. 7 is a sectional view of an insulated gate thyristor of another embodiment.

FIG. 8 is a sectional view of an insulated gate thyristor of another embodiment.

FIG. 9 is a sectional view of an insulated gate thyristor of another embodiment.

FIG. 10 is a cathode side layout of a conventional insulated gate thyristor and its AA ′ cross-sectional view.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... High resistance n-type base layer, 2 ... p-type base layer, 3 ... n-type buffer layer, 4 ... p-type emitter layer, 5 ... n-type emitter layer, 6 ... n-type source layer, 7 ... gate insulating film, 8 ... Gate electrode, 9 ... Cathode electrode, 10 ... Anode electrode, 11 ... High concentration p-type layer, 12 ... Oxide film, 13 ... Control electrode.

Claims (2)

[Claims] 1. A high resistance first conductivity type base layer, a second conductivity type base layer formed on a surface of the first conductivity type base layer, and a second conductivity type base layer formed on a surface of the second conductivity type base layer. A first conductive type emitter layer; a first conductive type source layer formed on a surface of the second conductive type base layer adjacent to the first conductive type emitter layer; and a second conductive layer on the first conductive type base layer. A second conductivity type emitter layer formed apart from the conductivity type base layer, and a region of the second conductivity type base layer sandwiched between the first conductivity type emitter layer and the first conductivity type source layer. An insulated gate electrode, a control electrode formed in contact with the second conductive type base layer, a first main electrode formed in contact with the first conductive type source layer, and a second conductive type emitter A second main electrode formed in contact with the layer, Insulated gate thyristor, characterized in that there was e. 2. The insulated gate electrode and the control electrode intersect each other and are formed in a plurality of stripes, and the first conductivity type emitter layer and the first conductivity type source layer are formed by:
2. The insulated gate thyristor according to claim 1, wherein the insulated gate thyristor is arranged in a region surrounded by the insulated gate electrode and the control electrode so as to be alternately dispersed along a longitudinal direction of the control electrode.