JPH0575132A - Vertical mos transistor and manufacture thereof - Google Patents

Abstract

PURPOSE:To provide a vertical MOS transistor, which can be easily fabricated without loss of the advantages of a vertical structure or the decrease in degree of freedom in pattern designing when gate width is increased. CONSTITUTION:A vertical MOS transistor includes a cylinder of silicon 31 perpendicular to the device plane A. The silicon cylinder includes a gate electrode 33 surrounded by a gate oxide 32. Source and drain regions 34 are formed on the respective ends of the cylinder of silicon. The width D of the silicon layer can be determined depending on the width of a depletion layer, irrespective of a desired gate width W, to make full use of a vertical structure.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of a vertical MOS transistor and a manufacturing method thereof.

[0002]

2. Description of the Related Art Conventionally, as a technique in such a field,
For example, "VLSI Process Data Handbook, 19
1990, Science Forum (SCIENCE F
ORUM) company, P47-48, P403-405, P1
09-113.

As a new attempt for a vertical MOS transistor, an SGT (S
urrounding Gate Transisto
r) is proposed. FIG. 10 is a diagram showing the structure of such a conventional STG, FIG. 10 (a) is a schematic perspective view of the SGT, and FIG. 10 (b) is a sectional view taken along line AA of FIG. 10 (a).

In the figure, 1 is a Si substrate, 2 is a p ^- well, 3 is an n ⁺ layer as a source, 4 is a polycrystalline silicon gate, 5 is a gate oxide film, and 6 is an n ⁺ layer as a drain. is there. The merit of such a vertical MOS transistor is
When the width of the pillar-shaped silicon is narrowed in addition to the large reduction of the area by installing the gate electrode in the vertical direction, the depletion layers from both sides stick to each other, and the pillar-shaped silicon can be completely depleted. For this reason, Thin-SOI (Silic
like on-on-insulator transistor, it can be completely controlled by the channel gate electric field.
As shown in FIG. 11, the subthreshold characteristic (sub
-Threshold) is improved, and further, suppression of short channel effect and improvement of current driving capability can be expected.

In FIG. 11, 11 is a Si substrate,
12 is a depletion layer region, 13 is a polycrystalline silicon gate, 14
Is a gate oxide film, 15 is a p ⁺ layer as a source, and 16 is a p ⁺ layer as a drain. That is, the vertical pMOS
And the length L of the polycrystalline silicon gate 13 is 1.5 μm.
m, the thickness _Tox of the gate oxide film is 20 nm, the drain voltage V _d is −4.0 V, and the substrate voltage V _sub is 0 V.

In FIG. 11, the horizontal axis represents the Si island size a (μm), and the vertical axis represents the subthreshold swing S. The subthreshold swing S means a subthreshold current (current flowing when the gate voltage is equal to or lower than the threshold voltage V _th and the Si surface is in the weak inversion state).
It refers to the amount of change in gate voltage (mV / decade) required to make a double change.

FIG. 12 shows a sectional image of the arrangement of the gate, the source and the drain. As shown in this figure, first, a silicon pillar 21 is installed vertically to the device surface A, and a gate insulating film 22 and a gate electrode 23 are arranged so as to surround the device surface A. The drain region 24 has a structure installed in the silicon pillar. Therefore, the gate length L is determined by the length of the silicon pillar, and the gate width W is determined by the peripheral length of the silicon pillar.

[0008]

However, the above conventional structure has the following problems. In order to control the current drive capability of a MOS transistor, a designer usually designs a pattern with the gate width W as a parameter. In the case of this structure, the gate width W is increased in the direction of increasing the diameter of the silicon pillar. Must. In this case, the depletion layer region is a cross-sectional view of FIG. 11 (a = 2 μm)
As described above, even if the subthreshold characteristic is deteriorated due to the existence of the depletion layer region end charge (depletion layer charge) in the silicon pillar, the level becomes the conventional lateral MOSFET level,
You will lose some of the advantages of the vertical structure.

In addition, a method of making the gate width W in the longitudinal direction with a constant interval between the surfaces where the depletion layers face each other is a lateral MOS.
In the actual pattern design, such as causing an increase tendency of the area similar to that of the FET, it results in sacrificing the significant reduction and high performance which are merits of the vertical transistor. Further, as a structural process problem expected from this structure, there is a method of extracting electrodes from each of the source and drain. First, in the case of drawing out the electrode from the columnar silicon upper diffusion layer, in order to take advantage of the vertical MOS transistor structure, in FIG. 11 (a = 1 μm)
As the diameter of the pillar-shaped silicon region is reduced,
The diameter of the electrode lead-out port formed for drawing out the electrode must also be made small, which requires fine patterning.

The present invention eliminates the above-mentioned obstructive factor in the device design of the vertical MOS transistor, that is, the loss of the merit of the vertical structure or the reduction in the degree of freedom in the pattern design by increasing the gate width W, and the manufacturing process is eliminated. Further, it is an object of the present invention to provide a vertical MOS transistor capable of avoiding an increase in manufacturing difficulty due to forced miniaturization of a pattern which is easily predicted, and a manufacturing method thereof.

[0011]

In order to achieve the above object, the present invention provides a vertical MOS transistor in which a tubular channel forming portion is buried perpendicularly to an element forming surface, and the tubular channel is formed. A gate electrode is provided inside the forming portion via a gate insulating film, and source / drain regions are formed above and below the gate electrode end of the tubular channel forming portion so as to sandwich the gate electrode. It is a thing.

Further, the extraction electrodes of the source / drain regions extend to the device surface, and the source electrodes are extracted to the device surface from a part of the source region provided at the bottom of the cylindrical channel forming portion. .. Further, the extraction electrodes of the source / drain regions extend to the device surface, and the source electrodes are extracted to the device surface from the entire area around the source region provided at the bottom of the tubular channel forming portion.

(A) In the method of manufacturing a vertical MOS transistor, a step of growing a first conductivity type epitaxial layer and a step of sequentially depositing a pad oxide film and a nitride film, and then removing the nitride film and the pad oxide film other than the active region. Then, a step of forming a field oxide film by selective oxidation, a reverse conductivity type impurity diffusion layer is formed in a part of the active region, and after converting a part of the surface of the active region into an oxide film, a nitride film on the entire surface is formed. And a step of removing the pad oxide film, and after forming a first polycrystalline silicon film on the entire surface and introducing a reverse conductivity type impurity,
A step of forming a nitride film and leaving the nitride film / polycrystalline silicon layer in an active region excluding a part of the active region and a desired region extending from the active region; and an active part other than a part of the active region. Forming a second opening in the center of the region and removing the first polycrystalline silicon film and the epitaxial layer by reactive ion etching; and performing thermal oxidation to form an oxide film in the second opening, A step of depositing a second polycrystalline silicon into which impurities have been introduced so as to cover the second opening and leave the polycrystalline silicon in a desired region extending to the field portion, and on the first opening. On the oxide film and on the desired portion of the first polycrystalline silicon layer to form a metal electrode.

(B) In the method of manufacturing a vertical MOS transistor, a field oxide film is formed on a first conductivity type substrate, an active region is opened, and then a reverse conductivity type diffusion layer is formed. To fill the active area with the first conductivity type single crystal silicon, and
A step of sequentially depositing polycrystalline silicon and a nitride film, and an active region on one side divided by the first opening and extending from the active region to the field region to divide the active region In the second opening as well as in the second opening, and a step of removing the nitride film and the polycrystalline silicon other than a desired area extending from the active area to the field area by reactive ion etching, and the first opening and the first opening The step of selectively removing the epitaxial layer in the second opening by reactive ion etching, and filling the first opening and the second opening with an oxide film by thermal oxidation, and at the same time also on the side wall of the first polycrystalline silicon. Generating an oxide film and nitriding the surface of the polycrystalline silicon, which is divided into two by the first opening and is connected to the active region where the second opening is not present. And removing an impurity of the opposite conductivity type, and after forming an oxide film on the surface of the polycrystalline silicon, the remaining nitride film is selectively removed and exposed by the ion implantation method. A step of introducing impurities of opposite conductivity type into the surface of the crystalline silicon, and a step of selectively removing the oxide film in the second opening and forming a relatively thin oxide film in the second opening and on the surface of the first polycrystalline silicon. Then, after depositing a second polycrystalline silicon layer into which impurities of opposite conductivity type are introduced on the entire surface, the second polycrystalline silicon other than the desired region which covers the second opening and extends to the field region is removed. And a step of forming an opening in a desired portion of the oxide film on the first polycrystalline silicon after forming an oxide film on the entire surface and forming a metal electrode.

(C) In the method of manufacturing a vertical MOS transistor, a field oxide film is formed on a first conductivity type substrate, an active region is opened, and then a reverse conductivity type diffusion layer is formed. To fill the active area with the first conductivity type single crystal silicon, and
A step of sequentially depositing a polycrystalline silicon layer and a nitride film, and a desired region extending from the active region to the field region in the first opening of the closed loop in which the center portion remains, which is present at equal intervals from the end of the active region Other than the nitride film and the first polycrystalline silicon by reactive ion etching, a step of selectively removing the epitaxial layer in the first opening by reactive ion etching, and a step of thermal oxidation by Filling the first opening with an oxide film and simultaneously forming an oxide film on the side wall of the first polycrystalline silicon; and forming a surface of the first polycrystalline silicon surface in the outer region in the active region separated by the first opening. A step of removing the nitride film and introducing impurities of the opposite conductivity type, and after forming an oxide film on the surface of the polycrystalline silicon, the remaining nitride film is selectively removed to form a second poly-oxide film on the entire surface. Generating a crystal silicon, after introducing the opposite conductivity type impurity in the second polycrystalline in silicon by ion implantation, a step of generating a nitride film on the entire surface, the first
The reactive ion etching removes the nitride film and the second polycrystalline silicon layer other than the desired region extending from the active region to the field region in the second opening and in the active region separated by the opening. The process of
A step of selectively removing the epitaxial layer in the second opening by reactive ion etching, and a relatively thin oxide film in the second opening and on the side wall of the second polycrystalline silicon by thermal oxidation, A step of producing a third polycrystalline silicon in which impurities of opposite conductivity type are introduced into the entire surface, and removing the third polycrystalline silicon except for a desired region which covers the second opening and extends to the field region. The steps of forming an oxide film on the entire surface, forming an opening in a desired portion of the oxide film on the first polycrystalline silicon and the second polycrystalline silicon, and forming a metal electrode are performed.

[0016]

The present invention is based on the vertical MO of the sectional image diagram (FIG. 1).
Like the S-transistor, the cylindrical silicon 31 is installed perpendicularly to the device surface A, the gate electrode 33 is embedded inside the cylinder through the gate insulating film 32, and the source / drain 34 is formed from the end of the gate electrode. Is cylindrical silicon 3
With the structure formed in No. 1, the silicon layer width D can be set according to the depletion layer width independently of the required gate width W, and the merit of the vertical structure can be fully utilized. ..

Further, the electrodes can be taken out from these thinned silicon layers without forcing fine patterning.

[0018]

Embodiments of the present invention will now be described in detail with reference to the drawings. 2 is a diagram showing the structure of a vertical MOS transistor showing the first embodiment of the present invention.
2A is a plan view thereof, and FIG. 2B is AA of FIG. 2A.
It is a line sectional view.

The first embodiment of the present invention will be described below with reference to FIG. An active region is opened in the thick oxide film 42 on the substrate 41, a source region 43 is buried in the opening bottom substrate 41, and a source extraction electrode 44, an insulating film 45, and a silicon layer 46 are sequentially provided from the side wall of the oxide film 42. Then, the gate electrode 48 is provided at the center with the gate oxide film 47 interposed therebetween. The drain region 49 is provided on the silicon layer 46 at a contact portion with the drain extraction electrode 44,
The upper end portion of the drain extraction electrode 50 is arbitrarily formed on the insulating film 4
5 and the oxide film 42.

Next, FIG. 3 is a diagram showing the structure of a vertical MOS transistor showing a second embodiment of the present invention.
(A) is the top view, FIG.3 (b) is AA of FIG.3 (a).
It is a line sectional view. The second embodiment of the present invention will be described below with reference to FIG. Here, the active region is opened in the thick oxide film 52 on the substrate 51, the source region 53 of the MOS transistor is buried in the opening bottom substrate 51, and the source region 53 is connected to a part of the side wall of the opening. The source electrode 54 is installed, and the insulating film 5 on the surface of the source electrode 54
5, a silicon layer 56 is internally provided, and a gate electrode 58 with a gate oxide film 57 interposed is provided at the center. The drain region 59 is provided at a contact portion with the drain extraction electrode 56a on the upper portion of the silicon layer 56, and the drain extraction electrode 56a and the source extraction electrode 60 have a structure extending arbitrarily on the insulating film 55 and the oxide film 52.

Next, advantages of the structure of the vertical MOS transistor according to the present invention will be described. First, what is commonly mentioned in the first and second embodiments is that
Since the thickness of the silicon layer serving as the channel portion of T can be arbitrarily set, it is possible to completely deplete the silicon layer during operation independently of setting the gate width W. Therefore, due to the increase in the gate width W, which has been a problem in the conventional structure, the diameter of the silicon pillar becomes large, the complete depletion layer formation between the source and drain becomes incomplete, and the desired performance improvement cannot be obtained, By extending the silicon layer in a plate shape in order to maintain the above, it is possible to suppress problems such as a reduction in the degree of freedom in pattern design.

Further features of the first and second embodiments will be described. First, a major structural difference is how to draw out the source electrode. In the first embodiment, the electrode is drawn from the entire area around the source diffusion region in the substrate, but in the second embodiment, it is arbitrarily set. Pulled out from the department. That is, in the first embodiment, the distance from the source diffusion region at the gate end to the source electrode is constant at any point, and a uniform source resistance is added. However, in the second embodiment, since it is drawn from a part of the periphery of the source region, the source resistance in the part facing the electrode connection becomes large, which may cause a slight disadvantage in performance. The reduction of the junction capacitance due to the smaller transistor occupation area and the smaller source region, on the other hand, contributes to the improvement of performance, and it is difficult to establish the superiority or inferiority.

Next, a method of manufacturing the vertical MOS transistor according to the present invention will be described. FIG. 4 is a sectional view of the first half vertical MOS transistor manufacturing process showing the first embodiment of the present invention, and FIG. 5 is a sectional view of the latter half vertical MOS transistor manufacturing process. First, as shown in FIG. 4A, an oxide film 62 is formed on the P-type substrate 61 by 4000 to 5000Å,
The active region 63 is opened, and As is an N-type impurity.
Is ion-implanted at 1 × 10 ¹⁶ / cm ² and then annealed to form the source region 64.

Next, as shown in FIG. 4B, the oxide film on the entire surface is removed and the P-type epitaxial layer 65 is controlled to have an impurity concentration of 1 × 10 ¹⁶ cm ^-3 to form a thickness of 1 μm. The oxide film 66 and the nitride film 67 are sequentially deposited by 200Å and 2000Å, respectively. Next, as shown in FIG. 4C, the source electrode lead portion 68 and the nitride film 67 and oxide film 66 other than the gate / drain portion 69 are sequentially removed, and selective oxidation is performed to form a field oxide film 70 of 2 μm. To do.

Next, as shown in FIG. 4D, the nitride film and the oxide film of the source electrode lead portion 68 are selectively removed, and thermal diffusion is performed by thermal decomposition of POCl ₃ , for example.
A high-concentration N ⁺ diffusion layer 71 is formed and connected to the buried N ⁺ layer (source region) 64. At this time, a new oxide film 72 of 2000 to 3000 Å is formed on the surface of the N ⁺ diffusion layer 71.

Next, the nitride film 6 of the gate / drain portion 69
7 and the oxide film 66 are selectively removed, and as shown in FIG. 5A, a polysilicon (polycrystalline silicon) layer 73 is formed on the entire surface at 4000 Å, and, for example, phosphorus is ion-implanted at 1 × 10 ¹⁶ / Cm ² It is implanted only in the polysilicon layer 73, and after a nitride film 74 of 2000 Å is formed on the entire surface,
Wiring patterning is performed to remove the nitride film and polysilicon other than the wiring portion.

Next, as shown in FIG. 5B, the nitride film 74, the polysilicon layer 73 and the epitaxial layer 65 in the gate region 75 are sequentially removed by reactive ion etching to fill the buried source diffusion layer. The surface of 64 is exposed. This step may be performed at the same time as the wiring patterning step in FIG. 5A if the etching selection ratio with respect to the surrounding oxide film can be sufficiently obtained. Then, thermal oxidation is performed to form a gate oxide film 76 on the side wall and bottom of the gate region opening.
Of 100 to 200 Å are generated, and, for example, polysilicon 77 to be a gate electrode is generated of 4000 to 5000 Å, phosphorus diffusion is performed, and then the gate electrode 77 is patterned. As a condition for performing the gate oxidation, a low temperature wet method is adopted, and the source / drain portion and the gate are formed by forming thicker than the side wall of the epitaxial layer 65 on the side wall of the drain extraction polysilicon electrode 73 and the surface of the source buried layer 64. Reduce the overlapping capacity.

Next, as shown in FIG. 5C, after depositing an oxide film 78 on the gate electrode 77 by thermal oxidation or a CVD method, metal electrodes are formed on the source electrode lead-out portion 71 and the drain electrode lead-out portion 73. The outlets 79 and 81 are opened, and the metal electrodes 80 and 82 are formed to complete the process.
Thus, the method of manufacturing the vertical MOS transistor of the present invention can be said to be a standard process in constructing the structure 1, and can be manufactured without using any technique having a particularly high degree of difficulty.

Furthermore, in the conventional structure, it is expected that the electrode extraction from the source region located at the bottom of the device due to the structure will be severely stepped. However, the manufacturing method of the present invention is generally used for manufacturing a bipolar device. Embedded technology and LO
By using the COS method together, there is no adverse effect on the electrode extraction from the source / drain (such as reduction in metal coverage due to increase in aperture aspect ratio).

As described above, the manufacturing method according to the first embodiment is low in technical difficulty and is a practical manufacturing method, but some improvements can be found, which will be described below. (1) Considering the alignment margin of the active region with respect to the buried N ⁺ layer (source diffusion region) and the amount of the bird's beak that is generated by the LOCOS method into the active region, the active area must be set large by that amount. (2) after implantation N ⁺ layer formed, by performing long heat treatment for generating a field oxide film, the buried N ⁺
It is difficult to control the effective gate length because the layer rises in the epitaxial layer and the channel length becomes short.

Next, a method of manufacturing a vertical MOS transistor showing a second embodiment of the present invention in consideration of the above points of improvement will be described. FIG. 6 is a sectional view of the first half vertical MOS transistor manufacturing process showing the second embodiment of the present invention, and FIG. 7 is a sectional view of the latter half vertical MOS transistor manufacturing process. First, as shown in FIG. 6A, a field oxide film 92 having a thickness of 1 μm is formed on the P-type substrate 91, and the active region 9 is formed.
3 is opened, an N ⁺ layer 94 to be an embedded source region is formed,
For example, 1 × 10 ¹⁶ cm ^{−2 of} As is implanted by the ion implantation method, and then annealing is performed.

Next, as shown in FIG. 6B, 1 × 10 ^{16 of} P-type epitaxial 95 is formed by the selective epitaxial method.
After growing a thickness of 1 μm in the active region at a concentration of cm ⁻³ , polysilicon 96 is deposited on the entire surface in a range of 3000 to 4000.
Å and the nitride film 97 are sequentially deposited by 2000Å. Then, as shown in FIG. 6C, a gate portion, a drain portion,
In order to separate the source portion, the nitride film 97 and the polysilicon layer 96 in the regions 98 and 99 are sequentially removed by reactive ion etching, the epitaxial layer 95 is also removed in the region 98, and the surface of the buried N ⁺ layer 94 is exposed. .. At this time, by adopting a condition having good selectivity with respect to the oxide film, the etching of the region 99 on the field oxide film 92 does not proceed. Then, thermal oxidation is performed to form the region (groove) 98 in the oxide film 100.
Embed with. In this case, for example, if a groove width of 0.5 μm is opened, the groove is completely filled with a generated film thickness of 5000 Å, and an oxide film layer having a width of 1 μm is formed.

Next, as shown in FIG. 6D, the nitride film of the source electrode portion 101 is removed, and the source electrode portion 101 of polysilicon is formed by, for example, the thermal decomposition phosphorus diffusion method of POCl _3.
Phosphorus is diffused into the epitaxial layer 95 through the via and is connected to the buried N ⁺ layer 94. Next, as shown in FIG. 7A, after a thermal oxide film 102 is formed on the source electrode portion 101, the nitride film on the polysilicon drain electrode portion 103 is selectively removed, and an ion implantation method is used. 1 x 10 ¹⁶ phosphorus
About cm ⁻² is injected into the electrode portion 103.

Next, as shown in FIG. 7B, the oxide film in the gate region 105 is selectively removed by, for example, wet etching and gate oxidation is performed, and the side wall and bottom of the epitaxial groove 95 of the opening groove are formed. After forming the gate oxide film 106 having a thickness of about 100 to 200 Å, the gate electrode 107
Embedded with, for example, phosphorus-doped polysilicon,
Pattern.

Next, as shown in FIG. 7C, after depositing an oxide film 108 on the gate electrode 107, the source electrode portion 10 is formed.
1 and the oxide film 102 of the drain electrode portion 103, an electrode extraction port 109 is opened, and a metal electrode 110 is formed to complete the process. According to the method of manufacturing the vertical MOS transistor, (1) N is formed after the long-time heat treatment step (field oxidation).
^{Since the +} buried layer is formed and the epitaxial growth is performed, the spread of the N ⁺ layer and the upward diffusion into the epitaxial layer are suppressed, and the controllability of the channel length is improved.

(2) Since the active region is composed of the epitaxial layer grown vertically along the side wall of the field oxide film (by reactive ion etching), the LO
It is not necessary to set an extra area corresponding to the bird's beak of the COS structure. (3) Since the N ⁺ buried layer is formed using the field oxide film as a mask, the N ⁺ buried layer has a self-aligned structure with the active region, and an alignment margin or the like is not necessary.

As described above, according to the manufacturing method of the second embodiment, although the technique of selective epitaxial growth, which still has a problem, is used, the controllability with the effective channel length (L) and the high integration are extremely high. This is an effective manufacturing method. Next, a third embodiment for manufacturing the transistor having the first structure (see FIG. 6) will be described.

FIG. 8 is a sectional view of a first half vertical MOS transistor manufacturing process showing a third embodiment of the present invention, and FIG. 9 is a sectional view of a second half vertical MOS transistor manufacturing process thereof. First, as shown in FIG. 8A, a field oxide film 122 having a thickness of 1 μm is formed on a P-type substrate 121, an active region 123 is opened, and an N ⁺ layer 1 to be a buried source region is formed.
24 is, for example, 1 × 10 ¹⁶ c of As by the ion implantation method.
Annealing is performed after m ⁻² implantation. Note that this step is the same as that in FIG. 6A of the second embodiment.

Next, as shown in FIG. 8B, 1 × 10 5 of P-type epitaxial 125 is formed by the selective epitaxial method.
After growing a thickness of 1 μm in the active region at a concentration of ¹⁶ cm ⁻³ , polysilicon 126 is deposited on the entire surface in a range of 3000 to 40.
00Å and nitride film 127 are sequentially deposited on 2000Å.
Note that this step is the same as that in FIG. 6B of the second embodiment.

Next, as shown in FIG. 8C, the isolation region 130 is selectively formed by reactive ion etching so as to surround the drain electrode portion 129 in order to isolate the source electrode portion 128 and the drain electrode portion 129. Opening to the nitride film 12
7, the polysilicon 126 and the epitaxial layer 125 are sequentially removed to form a groove, and then an oxide film 131 is formed by thermal oxidation.
To generate.

Then, the nitride film on the source electrode portion 128 is selectively removed and phosphorus diffusion using, for example, POCl ₃ is performed, so that N is formed in the epitaxial layer of the source electrode portion 128.
^{A +} layer 132 is formed and connected to the buried N ⁺ layer 124, and at the same time, a new oxide film 133 is formed on the surface of the source electrode polysilicon layer 126. Continuing with FIG. 9 (a)
As shown in FIG. 3, the nitride film on the drain electrode portion 134 is removed, and a polysilicon layer 135 is formed on the entire surface by 3000 to 4000.
Å is generated, and phosphorus is added by ion implantation to 1 × 10 ¹⁶ cm ^-2.
After being implanted into the polysilicon layer 135, a nitride film 136 is deposited to 2000 Å and wiring patterning is performed.

Subsequently, in the center of the drain electrode portion 134, as shown in FIG. 9B, the gate electrode opening 13 is formed.
7 is embedded by reactive ion etching into the N ⁺ layer 124.
Is formed to such an extent that it is exposed, and the gate electrode 138 is embedded and patterning is performed. Next, as shown in FIG. 9C, after depositing a new insulating film 139, metal electrode extraction openings 140 and 141 are formed from the source / drain, and then metal electrodes 142 and 143 are formed and completed. ..

With the above-described method of manufacturing a vertical MOS transistor, the source electrode can be taken out from the entire periphery of the buried N ⁺ (source) layer, and a structure intended to reduce the source resistance can be obtained. Further, the present invention is not limited to the above embodiments, and various modifications can be made based on the spirit of the present invention, and these modifications are not excluded from the scope of the present invention.

[0044]

As described above in detail, according to the present invention, the following effects can be obtained. (1) By reversing the positional relationship between the gate portion and the substrate region of the conventional vertical MOS transistor, the merit of high performance and large reduction that can be achieved only by the vertical MOS structure is affected by the required gate width. It is possible to maintain without being done.

(2) By extending the electrodes from the entire area around the source diffusion region located at the bottom of the vertical transistor, the additional resistance can be reduced and the performance can be improved. (3) According to the first manufacturing method of the present invention, it is possible to manufacture by a practical manufacturing process without using any technique having a high difficulty level.

(4) By performing the selective epitaxial growth technique according to the second manufacturing method of the present invention, the controllability of the effective channel length can be improved and the pattern can be reduced without forcing fine patterning. .. (5) According to the third manufacturing method of the present invention, by adding one step of polysilicon generation to the second manufacturing method, it is possible to extract electrodes from the entire periphery of the source diffusion region, which is the first structure of the present invention. It will be possible.

[Brief description of drawings]

FIG. 1 is a sectional image view of a vertical MOS transistor of the present invention.

FIG. 2 is a diagram showing a structure of a vertical MOS transistor showing a first embodiment of the present invention.

FIG. 3 is a diagram showing a structure of a vertical MOS transistor showing a second embodiment of the present invention.

FIG. 4 is a first-half vertical MOS showing a first embodiment of the present invention.
It is a manufacturing process sectional view of a transistor.

FIG. 5 is a vertical MOS of the latter half showing the first embodiment of the present invention.
It is a manufacturing process sectional view of a transistor.

FIG. 6 is a vertical MOS of the first half showing a second embodiment of the present invention.
It is a manufacturing process sectional view of a transistor.

FIG. 7 is a vertical MOS of the latter half showing a second embodiment of the present invention.
It is a manufacturing process sectional view of a transistor.

FIG. 8 is a first half vertical MOS showing a third embodiment of the present invention.
It is a manufacturing process sectional view of a transistor.

FIG. 9 is a vertical MOS of the latter half showing a third embodiment of the present invention.
It is a manufacturing process sectional view of a transistor.

FIG. 10 is a diagram showing a structure of a conventional STG.

FIG. 11 is a diagram showing the characteristics of the Si island dimension a of the conventional STG vs. substrate-threshold voltage swing.

FIG. 12 is a sectional image view of a conventional STG.

[Explanation of symbols]

41,51 Substrate 42,52,62,66,72,78,100,10
2, 108, 131, 133 Oxide film 43, 53 Source region 44, 68 Source extraction electrode 45, 55, 139 Insulation film 46, 56 Silicon layer 47, 57, 76, 106 Gate oxide film 48, 58, 107, 138 Gate Electrodes 49, 59 Drain region 50, 56a Drain extraction electrode 54 Source electrode 60 Source extraction electrode 61, 91, 121 P-type substrate 63, 93, 123 Active region 64, 94, 124 Source region (N ⁺ layer) 65, 95, 125 P-type epitaxial layer 67,74,97,127,136 Nitride film 69 Gate / drain part 70,92,122 Field oxide film 71 High concentration N ⁺ diffusion layer (source electrode extraction part) 73,96 Poly (polycrystalline) Silicon layer (drain electrode extraction part) 75 Gate region 77 Silicon (gate electrode) 79, 81 Metal electrode outlet 80, 82, 110, 142, 143 Metal electrode 98 Region (groove) 101, 128 Source electrode portion 103, 129, 134 Drain electrode portion 105 Gate region 109 Electrode outlet 126 , 135 Polysilicon (layer) 130 Isolation region 132 N ⁺ layer 137 Gate electrode opening 140, 141 Metal electrode extraction opening

Claims (6)

[Claims] 1. A tubular channel forming portion is embedded perpendicularly to an element forming surface, a gate electrode is provided inside the tubular channel forming portion with a gate insulating film interposed therebetween, and the gate electrode is sandwiched. Thus, the vertical MOS transistor is characterized in that the source / drain regions are formed above and below the end of the gate electrode of the tubular channel forming portion. 2. The vertical MOS transistor according to claim 1, wherein the extraction electrodes of the source / drain regions extend to the device surface, and from a part of the source region provided at the bottom of the tubular channel formation portion. A vertical MO having a structure in which a source electrode is drawn out to the device surface
S transistor. 3. The vertical MOS transistor according to claim 1, wherein the extraction electrodes of the source / drain regions extend to the device surface, and the source is formed from the entire periphery of the source region provided at the bottom of the tubular channel forming portion. Vertical M having a structure in which electrodes are drawn out to the device surface
OS transistor. 4. A step of (a) growing an epitaxial of the first conductivity type, and (b) sequentially depositing a pad oxide film and a nitride film, then removing the nitride film and the pad oxide film other than the active region, and performing selective oxidation. And (c) forming a field oxide film on the active region, forming a reverse conductivity type impurity diffusion layer in a part of the active region, converting a part of the surface of the active region into an oxide film, A step of removing the pad oxide film, and (d) forming a first polycrystalline silicon film on the entire surface, introducing impurities of opposite conductivity type, and then forming a nitride film, and forming an active region except a part of the active region. Leaving the nitride film / polycrystalline silicon layer in a desired region extending from the active region, (e) forming a second opening in the center of the active region other than a part of the active region, and Crystalline A step of removing the con-film and the epitaxial layer by reactive ion etching, and (f) thermal oxidation to form an oxide film in the second opening, and then a second polycrystalline silicon film into which impurities have been introduced over the entire surface. Depositing, leaving the second opening covered, and leaving polycrystalline silicon in a desired region extending to the field, and (g) on the oxide film on the first opening and on the first polycrystalline. And a step of forming a metal electrode by opening a desired portion of the silicon layer, and manufacturing a vertical MOS transistor. 5. A step of: (a) forming a field oxide film on a first conductivity type substrate and opening an active region, and then forming a reverse conductivity type diffusion layer; and (b) selecting an epitaxial region in the active region. With a first conductivity type single crystal silicon, and sequentially depositing a first polycrystalline silicon layer and a nitride film on the entire surface, (c) extending from the active region to the field region and dividing the active region. In the first opening and in the second opening that exists in the active region on one side divided by the first opening, and in the nitride film and polycrystalline silicon other than the desired region extending from the active region to the field region. A step of removing the layer by reactive ion etching, and (d) selectively removing the epitaxial layer in the first opening and the second opening by reactive ion etching. (E) filling the inside of the first opening and the second opening with an oxide film by thermal oxidation, and simultaneously forming an oxide film also on the side wall of the first polycrystalline silicon; (f) the first opening. Part of the polycrystalline silicon surface, which is divided into two parts and is connected to the active region where the second opening is not present, and a reverse conductivity type impurity is introduced, and (g) the polycrystalline silicon After forming an oxide film on the surface,
A step of selectively removing the remaining nitride film and introducing an impurity of opposite conductivity type to the exposed surface of the first polycrystalline silicon by an ion implantation method; and (h) selectively selecting the oxide film in the second opening. And forming a relatively thin oxide film in the second opening and on the surface of the first polycrystalline silicon, and (i) depositing a second polycrystalline silicon layer doped with an impurity of opposite conductivity type on the entire surface. After that, a step of removing the second polycrystalline silicon other than a desired region which covers the second opening and extends to the field region, and (j) after depositing an oxide film on the entire surface, first polycrystalline silicon And a step of forming an opening in a desired portion of the upper oxide film and forming a metal electrode. 6. A step of: (a) forming a field oxide film on a first conductivity type substrate, opening an active region, and then forming a reverse conductivity type diffusion layer; and (b) selecting an epitaxial region in the active region. Of the first conductivity type single crystal silicon, and sequentially depositing a first polycrystalline silicon layer and a nitride film on the entire surface, and (c) a closed loop in which the center portion remains, which is present at equal intervals from the end of the active region. Removing the nitride film and the first polycrystalline silicon in the first opening other than the desired region extending from the active region to the field region by reactive ion etching, and (d) epitaxially in the first opening. A step of selectively removing the layer by reactive ion etching, and (e) filling the inside of the first opening with an oxide film by thermal oxidation and simultaneously forming an oxide film on the side wall of the first polycrystalline silicon. And (f) removing the nitride film on the surface of the first polycrystalline silicon in the outer region in the active region separated by the first opening,
A step of introducing impurities of opposite conductivity type, and (g) a step of forming an oxide film on the surface of the polycrystalline silicon and then selectively removing the remaining nitride film to form a second polycrystalline silicon on the entire surface. And (h) a step of introducing an impurity of opposite conductivity type into the second polycrystalline silicon by an ion implantation method and then forming a nitride film on the entire surface, and (i) an active region separated by the first opening. Removing the nitride film and the second polycrystalline silicon layer other than a desired region extending from the active region to the field region in the second opening which is present in the substrate by reactive ion etching, (j) A step of selectively removing the epitaxial layer in the second opening by reactive ion etching, and (k) thermal oxidation to form a relatively thin oxide film in the second opening and on the side wall of the second polycrystalline silicon. After, full surface A step of producing a third polycrystalline silicon into which an impurity of opposite conductivity type is introduced, and (l) removing the third polycrystalline silicon other than a desired region which covers the second opening and extends to the field region. And (m) after depositing an oxide film on the entire surface, forming an opening in a desired portion of the first polycrystalline silicon and second polycrystalline silicon upper oxide film to form a metal electrode. A method of manufacturing a vertical MOS transistor, which is characterized by the above.