JPH0575313A - Hybrid integrated circuit device - Google Patents
Hybrid integrated circuit deviceInfo
- Publication number
- JPH0575313A JPH0575313A JP3231678A JP23167891A JPH0575313A JP H0575313 A JPH0575313 A JP H0575313A JP 3231678 A JP3231678 A JP 3231678A JP 23167891 A JP23167891 A JP 23167891A JP H0575313 A JPH0575313 A JP H0575313A
- Authority
- JP
- Japan
- Prior art keywords
- metallization layer
- dielectric substrate
- integrated circuit
- circuit device
- hybrid integrated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL
Landscapes
- Waveguides (AREA)
Abstract
(57)【要約】 （修正有）
【目的】 接続用金属細線の長さを短くしインダクタン
スの影響を少なくして、高周波特性に優れかつ小型化に
適した混成集積回路装置を提供すること。
【構成】 表面にマイクロ波ストリップライン（７）と
第３金属化層（５）とが形成され、裏面に第１金属化層
（６）が形成された第１の誘電体基板（２）と、表面が
第１の誘電体基板（２）の表面に密接し、裏面に第２金
属化層（４）が形成された第２の誘電体基板（３）と、
表面がマイクロ波ストリップライン（７）及び第３金属
化層（５）の表面と略同一面となるよう、裏面を第１の
誘電体基板（２）に形成された穴部に載置した半導体素
子（９）と、半導体装置の電極とマイクロ波ストリップ
ライン（７）及び第３金属化層（５）とを略同一面上で
接続する金属細線（８）とを設けた。
(57) [Summary] (Modified) [Purpose] To provide a hybrid integrated circuit device which has excellent high-frequency characteristics and is suitable for miniaturization by shortening the length of the metal wire for connection and reducing the influence of inductance. A first dielectric substrate (2) having a microwave stripline (7) and a third metallization layer (5) formed on the front surface and a first metallization layer (6) formed on the back surface. A second dielectric substrate (3) having a front surface in close contact with the front surface of the first dielectric substrate (2) and a second metallization layer (4) formed on the back surface,
A semiconductor in which the back surface is placed in the hole formed in the first dielectric substrate (2) such that the front surface is substantially flush with the surfaces of the microwave strip line (7) and the third metallization layer (5). An element (9) and a thin metal wire (8) for connecting the electrode of the semiconductor device with the microwave strip line (7) and the third metallization layer (5) on substantially the same plane were provided.
Description
【０００１】[0001]
【産業上の利用分野】本発明は混成集積回路装置に係
り、特に高周波特性が良好でかつ高密度実装に適した混
成集積回路装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a hybrid integrated circuit device, and more particularly to a hybrid integrated circuit device having good high frequency characteristics and suitable for high density mounting.
【０００２】[0002]
【従来の技術】従来のこの種の装置は、例えば特開平２
−１３５８０２号公報に開示されているものが知られて
いる。図３は上述の公報に開示された混成集積回路装置
を示す斜視図である。2. Description of the Related Art A conventional device of this type is disclosed in, for example, Japanese Patent Laid-Open No.
What is disclosed in Japanese Patent Publication No. 135802 is known. FIG. 3 is a perspective view showing the hybrid integrated circuit device disclosed in the above publication.
【０００３】第１の誘電体基板１０の表面にはマイクロ
波ストリップライン５０ａ，５０ｂ，５０ｃが形成さ
れ、裏面には第１の裏面金属化層３０が形成されてい
る。第１の誘電体基板１０には第２の誘電体基板２０が
表面同志が密着するように積層されており、その裏面に
は第２の裏面金属化層４０が形成されている。Microwave strip lines 50a, 50b, 50c are formed on the front surface of the first dielectric substrate 10, and a first back surface metallization layer 30 is formed on the back surface. A second dielectric substrate 20 is laminated on the first dielectric substrate 10 so that their surfaces are in close contact with each other, and a second back surface metallization layer 40 is formed on the back surface thereof.
【０００４】第２の誘電体基板２０の所定部分には部品
を搭載して接続するための穴部が形成され、この穴部を
介してストリップライン５０ａ，５０ｂ間又はストリッ
プライン５０ｂと第２の裏面金属化層４０とを図示しな
い半田で接合するチップコンデンサー６０ａ，６０ｂが
搭載される。A hole for mounting and connecting a component is formed in a predetermined portion of the second dielectric substrate 20, and the strip line 50a or 50b or the strip line 50b and the second line are formed through this hole. Chip capacitors 60a and 60b for joining the back surface metallization layer 40 with solder (not shown) are mounted.
【０００５】また、別の穴部にはストリップライン５０
ｃ上に半田で接合された半導体素子７０が搭載される。
そしてこの半導体素子７０上の図示しない電極と第２の
裏面金属化層４０とは金属細線８０により接続されてい
る。A strip line 50 is provided in another hole.
The semiconductor element 70 joined by solder is mounted on c.
Then, an electrode (not shown) on the semiconductor element 70 and the second back surface metallization layer 40 are connected by a thin metal wire 80.
【０００６】更に誘電体基板１０，２０の側面には第１
の裏面金属化層３０と第２の裏面金属化層４０とを電気
的に接続する側面金属化層９０ａ，９０ｂが形成されて
いる。Further, the side surfaces of the dielectric substrates 10 and 20 have a first
Side metallization layers 90a and 90b for electrically connecting the back metallization layer 30 and the second back metallization layer 40 are formed.
【０００７】このように従来の混成集積回路装置ではマ
イクロ波ストリップライン５０ａ，５０ｂ，５０ｃをグ
ランド層を形成する第１及び第２の裏面金属化層３０，
４０で両側から挟み込む構造を採用している。これによ
りシールド効果を高め、外部からの電磁波の影響やスト
リップライン間の相互干渉を軽減するようにしている。As described above, in the conventional hybrid integrated circuit device, the microwave strip lines 50a, 50b, and 50c are connected to the first and second backside metallization layers 30 forming the ground layer.
It has a structure in which it is sandwiched by 40 from both sides. This enhances the shield effect and reduces the influence of external electromagnetic waves and mutual interference between strip lines.
【０００８】又第２の誘電体基板２０の所望部分に穴部
を形成し、チップコンデンサー６０ａ，６０ｂ、半導体
素子７０を搭載し、チップコンデンサー６０ｂの一部電
極をグランド層となる第２の金属化層４０と接続し、半
導体素子７０のグランド用電極を金属細線８０を介して
グランド層となる第２の裏面金属化層４０へ接続するよ
うにして、ビアホール（Ｖｉａ Ｈｏｌｅ）によるイン
ダクタンスの悪影響を防止している。A hole is formed in a desired portion of the second dielectric substrate 20, the chip capacitors 60a and 60b, and the semiconductor element 70 are mounted, and a part of the electrode of the chip capacitor 60b serves as a ground layer for the second metal. And the ground electrode of the semiconductor element 70 is connected to the second backside metallization layer 40 serving as a ground layer through the thin metal wire 80 so as to prevent the adverse effect of the inductance due to the via hole. To prevent.
【０００９】[0009]
【発明が解決しようとする課題】しかし上述した従来の
混成集積回路装置では、半導体素子の表面とグランド層
となる第２の裏面金属化層との間及び半導体素子表面と
マイクロ波ストリップラインの接続表面との間に段差が
存在した。However, in the above-mentioned conventional hybrid integrated circuit device, the connection between the surface of the semiconductor element and the second backside metallization layer serving as the ground layer, and the connection between the semiconductor element surface and the microwave strip line. There was a step between the surface and the surface.
【００１０】従ってこれらの間を金属細線により接続し
た場合金属細線が長くなり、これに伴いインダクタンス
が増加してその影響が大きくなるという問題点があっ
た。Therefore, when these are connected by a thin metal wire, there is a problem that the thin metal wire becomes long, and along with this, the inductance increases and its influence becomes large.
【００１１】本発明は上述した問題点を解消するために
なされたもので、接続用金属細線の長さを短くしインダ
クタンスの影響を少なくして高周波特性が優れかつ小型
化に適した混成集積回路装置を提供することを目的とす
る。The present invention has been made in order to solve the above-mentioned problems, and it is a hybrid integrated circuit which is excellent in high-frequency characteristics and suitable for downsizing by shortening the length of the metal thin wire for connection and reducing the influence of inductance. The purpose is to provide a device.
【００１２】[0012]
【課題を解決するための手段】本発明の混成集積回路装
置は、表面にマイクロ波ストリップラインと第３金属化
層とが形成され、裏面に第１金属化層が形成された第１
の誘電体基板と、表面が前記第１の誘電体基板の表面に
密接し、裏面に第２金属化層が形成された第２の誘電体
基板と、表面が前記マイクロ波ストリップライン及び前
記第３金属化層の表面と略同一面となるよう、裏面を前
記第１の誘電体基板に形成された穴部に載置した半導体
素子と、前記半導体装置の電極と前記マイクロ波ストリ
ップライン及び前記第３金属化層とを略同一面上で接続
する金属細線とを設けたものである。In a hybrid integrated circuit device of the present invention, a microwave stripline and a third metallization layer are formed on the front surface, and a first metallization layer is formed on the back surface.
Dielectric substrate, a second dielectric substrate having a front surface in close contact with the front surface of the first dielectric substrate and a second metallization layer formed on the back surface, and the front surface having the microwave strip line and the second dielectric substrate. 3 a semiconductor element having a back surface placed in a hole formed in the first dielectric substrate so as to be substantially flush with the front surface of the metallization layer, an electrode of the semiconductor device, the microwave strip line, and the A thin metal wire that connects the third metallization layer on substantially the same plane is provided.
【００１３】[0013]
【作用】本発明では第１の誘電体基板表面に、載置され
る半導体素子の厚みと略同一の深さを有する開口部を設
けて、この開口部内に半導体素子を載置している。従っ
てこの半導体素子の電極面は第１の誘電体基板の表面と
略同一面となる。In the present invention, an opening having a depth substantially the same as the thickness of the semiconductor element to be mounted is provided on the surface of the first dielectric substrate, and the semiconductor element is mounted in this opening. Therefore, the electrode surface of this semiconductor element is substantially flush with the surface of the first dielectric substrate.
【００１４】そこで、第１の誘電体基板上に形成されて
いるストリップラインや第３の金属化層と半導体素子の
電極とを金属細線により接続した場合、この金属細線自
身も略同一面上で接続されることになる。これにより金
属細線の長さを最小限にすることができるためインダク
タンスが減りその影響を小さくすることができるのであ
る。Therefore, when the strip line or the third metallized layer formed on the first dielectric substrate and the electrode of the semiconductor element are connected by a metal thin wire, the metal thin wire itself is also on the substantially same plane. Will be connected. As a result, the length of the thin metal wire can be minimized, so that the inductance can be reduced and its influence can be reduced.
【００１５】[0015]
【実施例】以下本発明の実施例を図１及び図２に基づい
て詳細に説明する。図１は本発明の１実施例に係る混成
集積回路装置の斜視図を示したものである。Embodiments of the present invention will be described in detail below with reference to FIGS. 1 and 2. FIG. 1 is a perspective view of a hybrid integrated circuit device according to one embodiment of the present invention.
【００１６】第１の誘電体基板２と、第２の誘電体基板
３とがその表面同志を密着させて積層構造を形成してい
る。第１の誘電体基板の裏面及び第２の誘電体基板３の
裏面にはそれぞれ第１及び第２の金属化層６，４が形成
されている。Surfaces of the first dielectric substrate 2 and the second dielectric substrate 3 are in close contact with each other to form a laminated structure. First and second metallization layers 6 and 4 are formed on the back surface of the first dielectric substrate and the back surface of the second dielectric substrate 3, respectively.
【００１７】これらの第１及び第２の金属化層６，４は
グランド層として用いられ、図示しない接続手段により
相互接続される。These first and second metallization layers 6, 4 are used as ground layers and are interconnected by connecting means not shown.
【００１８】第１の誘電体基板の表面にはマイクロ波ス
トリップライン７ａ，７ｂが形成されると共に、第３の
金属化層５ａ及び５ｂがマイクロ波ストリップライン７
ａ，７ｂの形成部分以外の部分に形成されている。この
第３の金属化層５ａ，５ｂも第１及び第２の金属化層
６，４と同様に第グランド層として用いられ、図示しな
い結合手段により第１及び第２の金属化層６，４と相互
接続される。Microwave strip lines 7a and 7b are formed on the surface of the first dielectric substrate, and the third metallized layers 5a and 5b are formed on the surface of the microwave strip line 7.
It is formed in a portion other than the portions where a and 7b are formed. The third metallization layers 5a and 5b are also used as the first ground layer similarly to the first and second metallization layers 6 and 4, and the first and second metallization layers 6 and 4 are formed by a coupling means (not shown). Interconnected with.
【００１９】第１の誘電体基板の所望部分には開口部が
設けられ、この開口部の深さは搭載される半導体素子９
の厚さと略同一となるように形成する。従って、半導体
素子９がこの開口部に搭載された場合、その表面はマイ
クロ波ストリップライン７ａ，７ｂ及び第３の金属化層
５ａ，５ｂと略同一面となる。An opening is provided in a desired portion of the first dielectric substrate, and the depth of this opening is the semiconductor element 9 to be mounted.
Is formed to have a thickness substantially the same as that of. Therefore, when the semiconductor element 9 is mounted in this opening, its surface becomes substantially flush with the microwave strip lines 7a, 7b and the third metallization layers 5a, 5b.
【００２０】半導体素子９の表面に設けられた図示しな
い電極とマイクロ波ストリップライン７ａ，７ｂ及び第
３の金属化層５ａ，５ｂとは金属細線８により所望の箇
所が接続される。この結果、接続用の金属細線８は最短
距離で略同一面上になるように接続されるため、インダ
クタンスが最小となり高周波におけるインダクタンスの
影響を低減することができる。The electrodes (not shown) provided on the surface of the semiconductor element 9, the microwave strip lines 7a and 7b, and the third metallized layers 5a and 5b are connected to each other at a desired position by a thin metal wire 8. As a result, the metal thin wires 8 for connection are connected so as to be on the same plane at the shortest distance, so that the inductance is minimized and the influence of the inductance at high frequencies can be reduced.
【００２１】図２は本発明の他の実施例を示す斜視図
で、グランド層として設けられた第３の金属化層５ａ，
５ｂを第１及び第２の誘電体基板２，３の所定部分に設
けたビアホール１０ａ，１０ｂ，１０ｃにより第１及び
第２の金属化層６，４と相互接続してグランド層を形成
したものである。FIG. 2 is a perspective view showing another embodiment of the present invention, in which a third metallization layer 5a provided as a ground layer,
5b is interconnected with the first and second metallization layers 6 and 4 by via holes 10a, 10b and 10c provided in predetermined portions of the first and second dielectric substrates 2 and 3 to form a ground layer. Is.
【００２２】このように金属化層同志をビアホールによ
り適宜接続することにより誘電体基板の面積が大きい場
合に高周波に対するシールド効果が充分でなかった欠点
を補うことができる。By properly connecting the metallization layers to each other by via holes in this manner, it is possible to compensate for the drawback that the high frequency shielding effect is not sufficient when the area of the dielectric substrate is large.
【００２３】さらに図２に示す実施例では第２の誘電体
基板３の開口部を覆うように金属製の蓋１を設けてい
る。この金属製の蓋１により開口部を覆ってこれを第２
の金属化層４と電気的に接続することにより、半導体素
子９及びマイクロ波ストリップライン７ａ，７ｂを外部
の高周波から完全にシールドすることができる。Further, in the embodiment shown in FIG. 2, a metallic lid 1 is provided so as to cover the opening of the second dielectric substrate 3. This metal lid 1 covers the opening and
The semiconductor element 9 and the microwave strip lines 7a and 7b can be completely shielded from external high frequency by electrically connecting to the metallization layer 4 of FIG.
【００２４】[0024]
【発明の効果】以上実施例に基づいて詳細に説明したよ
うに、本発明では第１の誘電体基板に搭載される半導体
素子の表面とこれに接続されるマイクロ波ストリップラ
イン及びグランド層となる第３の金属化層とが略同一面
上に位置するように構成される。従って相互接続のため
の金属細線によるインダクタンスの影響を低減すること
ができる。As described above in detail with reference to the embodiments, the present invention forms the surface of the semiconductor element mounted on the first dielectric substrate, the microwave strip line connected to the surface, and the ground layer. It is configured such that the third metallization layer is substantially coplanar. Therefore, the influence of the inductance due to the thin metal wires for interconnection can be reduced.
【００２５】又マイクロ波ストリップラインを上下に吸
収される金属化層によるグランド層で挟む構造となるた
め、マイクロ波ストリップライン間の相互干渉を抑制す
ることができる。Further, since the microwave strip lines are sandwiched between the ground layers of the metallized layers which are vertically absorbed, mutual interference between the microwave strip lines can be suppressed.
【図１】本発明の一実施例に係る混成集積回路装置の構
成を示す斜視図。FIG. 1 is a perspective view showing a configuration of a hybrid integrated circuit device according to an embodiment of the present invention.
【図２】本発明の他の実施例を示す斜視図。FIG. 2 is a perspective view showing another embodiment of the present invention.
【図３】従来の混成集積回路装置の構成を示す斜視図。FIG. 3 is a perspective view showing a configuration of a conventional hybrid integrated circuit device.
１ 金属製の蓋 ２ 第１の誘電体基板 ３ 第２の誘電体基板 ４ 第２の金属化層 ５ａ，５ｂ 第３の金属化層 ６ 第１の金属化層 ７ａ，７ｂ マイクロ波ストリップライン ８ 金属細線 ９ 半導体素子 １０ａ，１０ｂ，１０ｃ ビアホール 1 Metal Lid 2 1st Dielectric Substrate 3 2nd Dielectric Substrate 4 2nd Metallization Layer 5a, 5b 3rd Metallization Layer 6 1st Metallization Layer 7a, 7b Microwave Stripline 8 Fine metal wires 9 Semiconductor elements 10a, 10b, 10c Via holes
Claims (3)
３金属化層とが形成され、裏面に第１金属化層が形成さ
れた第１の誘電体基板と、 表面が前記第１の誘電体基板の表面に密着し、裏面に第
２金属化層が形成された第２の誘電体基板と、 表面が前記マイクロ波ストリップライン及び前記第３金
属化層の表面と略同一面となるよう、裏面を前記第１の
誘電体基板に形成された開口部に載置した半導体素子
と、 前記半導体素子の電極と前記マイクロ波ストリップライ
ンおよび前記第３金属化層とを略同一面上で接続する金
属細線とを具備してなる混成集積回路装置。1. A first dielectric substrate having a microwave stripline and a third metallization layer formed on a front surface thereof, and a first metallization layer formed on a rear surface thereof, and the first dielectric substrate having a front surface thereof. A second dielectric substrate which is in close contact with the surface of the second metallization layer and which has a second metallization layer formed on the back surface thereof, and the back surface of which is substantially flush with the surfaces of the microwave stripline and the third metallization layer. A metal that connects the semiconductor element mounted on the opening formed in the first dielectric substrate, and the electrode of the semiconductor element, the microwave strip line, and the third metallization layer on substantially the same plane. A hybrid integrated circuit device comprising: a thin wire.
び第２の誘電体基板を貫通して設けたビアホール（Ｖｉ
ａ Ｈｏｌｅ）を介して電気的に接続したことを特徴と
する請求項１記載の混成集積回路装置。2. A via hole (Vi) provided with the first to third metallization layers penetrating the first and second dielectric substrates.
2. The hybrid integrated circuit device according to claim 1, wherein the hybrid integrated circuit device is electrically connected via a hole.
子及びその接続部を露出させる開口部を設け、この開口
部を覆い、前記第１金属化層と電気的に接続される金属
製の蓋を設けたことを特徴とする請求項１記載の混成集
積回路装置。3. The second dielectric substrate is provided with an opening that exposes the semiconductor element and its connecting portion, and is made of a metal that covers the opening and is electrically connected to the first metallization layer. 2. The hybrid integrated circuit device according to claim 1, further comprising a lid.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3231678A JPH0575313A (en) | 1991-09-11 | 1991-09-11 | Hybrid integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3231678A JPH0575313A (en) | 1991-09-11 | 1991-09-11 | Hybrid integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0575313A true JPH0575313A (en) | 1993-03-26 |
Family
ID=16927275
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3231678A Pending JPH0575313A (en) | 1991-09-11 | 1991-09-11 | Hybrid integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0575313A (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5923540A (en) * | 1993-11-30 | 1999-07-13 | Fujitsu Limited | Semiconductor unit having semiconductor device and multilayer substrate, in which grounding conductors surround conductors used for signal and power |
| US6166613A (en) * | 1996-07-18 | 2000-12-26 | Matsushita Electric Industrial Co., Ltd. | Voltage-controlled resonator, method of fabricating the same, method of tuning the same, and mobile communication apparatus |
| US6426686B1 (en) * | 1999-06-16 | 2002-07-30 | Microsubstrates Corporation | Microwave circuit packages having a reduced number of vias in the substrate |
| US6774748B1 (en) | 1999-11-15 | 2004-08-10 | Nec Corporation | RF package with multi-layer substrate having coplanar feed through and connection interface |
| KR100686003B1 (en) * | 2000-02-23 | 2007-02-23 | 엘지전자 주식회사 | High frequency device package and its manufacturing method |
| US20090244869A1 (en) * | 2008-04-01 | 2009-10-01 | Nec Electronics Corporation | Semiconductor device having wiring formed on wiring board and electric conductor formed in wiring board and conductor chip formed over wiring |
| WO2014083967A1 (en) * | 2012-11-29 | 2014-06-05 | オリンパスメディカルシステムズ株式会社 | Board structure |
-
1991
- 1991-09-11 JP JP3231678A patent/JPH0575313A/en active Pending
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5923540A (en) * | 1993-11-30 | 1999-07-13 | Fujitsu Limited | Semiconductor unit having semiconductor device and multilayer substrate, in which grounding conductors surround conductors used for signal and power |
| US6166613A (en) * | 1996-07-18 | 2000-12-26 | Matsushita Electric Industrial Co., Ltd. | Voltage-controlled resonator, method of fabricating the same, method of tuning the same, and mobile communication apparatus |
| US6426686B1 (en) * | 1999-06-16 | 2002-07-30 | Microsubstrates Corporation | Microwave circuit packages having a reduced number of vias in the substrate |
| US6774748B1 (en) | 1999-11-15 | 2004-08-10 | Nec Corporation | RF package with multi-layer substrate having coplanar feed through and connection interface |
| KR100686003B1 (en) * | 2000-02-23 | 2007-02-23 | 엘지전자 주식회사 | High frequency device package and its manufacturing method |
| US20090244869A1 (en) * | 2008-04-01 | 2009-10-01 | Nec Electronics Corporation | Semiconductor device having wiring formed on wiring board and electric conductor formed in wiring board and conductor chip formed over wiring |
| US8363421B2 (en) * | 2008-04-01 | 2013-01-29 | Renesas Electronics Corporation | Semiconductor device having wiring formed on wiring board and electric conductor formed in wiring board and conductor chip formed over wiring |
| WO2014083967A1 (en) * | 2012-11-29 | 2014-06-05 | オリンパスメディカルシステムズ株式会社 | Board structure |
| JP5548324B1 (en) * | 2012-11-29 | 2014-07-16 | オリンパスメディカルシステムズ株式会社 | Board structure |
| US9060447B2 (en) | 2012-11-29 | 2015-06-16 | Olympus Medical Systems Corp. | Substrate structure |
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