JPH057797B2 - - Google Patents
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- Publication number
- JPH057797B2 JPH057797B2 JP61156041A JP15604186A JPH057797B2 JP H057797 B2 JPH057797 B2 JP H057797B2 JP 61156041 A JP61156041 A JP 61156041A JP 15604186 A JP15604186 A JP 15604186A JP H057797 B2 JPH057797 B2 JP H057797B2
- Authority
- JP
- Japan
- Prior art keywords
- transistor
- emitter
- double
- type
- base
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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Classifications
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E60/00—Enabling technologies; Technologies with a potential or indirect contribution to GHG emissions mitigation
- Y02E60/30—Hydrogen technology
- Y02E60/50—Fuel cells
Landscapes
- Static Random-Access Memory (AREA)
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、PNPN交差結合型メモリセルの改
良に関するもので、書き込みパルス幅を小さくす
るためのメモリセルを提供するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an improvement of a PNPN cross-coupled memory cell, and provides a memory cell for reducing the write pulse width.
第１図に、従来のPNPN交差結合型メモリセ
ルとその周辺回路の一部を示した。このようなセ
ルは、例えば特開昭50−38428号公報等に開示さ
れる。第１図においてセル１の有する情報“１”
を“０”に書きかえる場合を考える。すなわち、
トランジスタＴ４とＴ６とがオンでＴ３とＴ５と
がオフの状態から、トランジスタＴ４とＴ６とが
オフ、Ｔ３とＴ５とがオンとなる状態にする。今
ワード線Ｗ１が選択され、Ｗ１の電位がWXHの
時、トランジスタＴ４，Ｔ６がオン、トランジス
タＴ３，Ｔ５がオフとすると、Ｔ６から、デイジ
ツト線Ｄ２へ読み出し電流IRが流れている。この
時、Ｔ１２のベース電位VrefcをＴ６のベース電
位Ｖ１より高い電位VWHへ上げると同時に、Ｔ１
１のベース電位をVrefcからＴ５のベース電位Ｖ
２より低い電位VWLへ下げると、Ｔ５がオンし
て、IRがＴ５からデイジツト線Ｄ１に流れ出る。
この時、読み出し電流IRが、Ｔ５から流れ始めた
時点では、Ｖ１の電位が高く、Ｔ３がオフ、Ｔ４
がオンのため、Ｔ５のコレクタに流れこむ電流
は、Ｔ４のコレクタおよび飽和により蓄積された
電荷があるＴ６のベースから供給される（第２
図）。Ｔ６のベースから蓄積電荷が引き抜かれな
がら、Ｖ１の電位がゆつくりと降下するため、Ｔ
３がオンとなるまでに、長時間を要す。やがて、
Ｔ５のコレクタ電流が、Ｔ３から供給されるよう
になると、Ｖ２の電位が上昇し、Ｔ４はオフとな
り書き込みが完了する。
FIG. 1 shows a conventional PNPN cross-coupled memory cell and part of its peripheral circuitry. Such a cell is disclosed in, for example, Japanese Patent Laid-Open No. 50-38428. In Fig. 1, information “1” possessed by cell 1
Consider the case where is rewritten to "0". That is,
The state where transistors T4 and T6 are on and T3 and T5 are off is changed to a state where transistors T4 and T6 are off and transistors T3 and T5 are on. When word line W1 is selected and the potential of W1 is WXH , transistors T4 and T6 are turned on and transistors T3 and T5 are turned off, then a read current I R flows from T6 to digit line D2. At this time, while raising the base potential V refc of T12 to a potential V WH higher than the base potential V1 of T6,
1's base potential from V refc to T5's base potential V
When the voltage is lowered to a potential V WL lower than 2, T5 turns on and I R flows out from T5 to the digit line D1.
At this time, when the read current I R starts flowing from T5, the potential of V1 is high, T3 is off, and T4
is on, the current flowing into the collector of T5 is supplied from the collector of T4 and the base of T6, where there is a charge accumulated due to saturation (the second
figure). As the accumulated charge is extracted from the base of T6, the potential of V1 slowly drops, so T
3 takes a long time to turn on. Eventually,
When the collector current of T5 is supplied from T3, the potential of V2 rises, T4 is turned off, and writing is completed.
このように、従来のPNPN交差結合型メモリ
セルは、トランジスタＴ５のコレクタ電流が流れ
た時点で、オン状態にあるＴ４が障害になつて、
Ｔ６のベースに蓄積された電荷を引き抜くのに使
用される電流が少なく、時間を要するため、書き
込み完了までに相当の時間を要し、書き込みパル
ス幅が大きくなるという欠点を有していた。
In this way, in the conventional PNPN cross-coupled memory cell, when the collector current of transistor T5 flows, T4, which is in the on state, becomes a failure.
Since the current used to draw out the charge accumulated in the base of T6 is small and it takes time, it has the disadvantage that it takes a considerable amount of time to complete writing and the writing pulse width becomes large.
本発明は、前述の如き欠点を改善したものであ
り、その目的は、書き込みパルス幅の小さい
PNPN交差結合型メモリセルを得ることにある。 The present invention improves the above-mentioned drawbacks, and its purpose is to reduce the write pulse width.
The objective is to obtain a PNPN cross-coupled memory cell.
この目的を達成するために、本発明の半導体メ
モリセルは、従来のPNPN交差結合型メモリセ
ルに抵抗を付加したものである。
To achieve this objective, the semiconductor memory cell of the present invention is a conventional PNPN cross-coupled memory cell with an added resistor.
抵抗は、PNPトランジスタのコレクタとNPN
トランジスタのベース間にあつて、書き込み開始
時に、抵抗に流れる電流によつて、オン側の
NPNトランジスタのベース電位の降下をすみや
かに引き起こすと同時に、前記抵抗によりPNP
トランジスタＴ４から流れる電流を押えて、
NPNトランジスタＴ６のベース蓄積電荷の引き
抜きを速くし、書き込みパルス幅を低減させる手
段を提供する。
The resistor is the collector of the PNP transistor and the NPN
Located between the base of the transistor, at the start of writing, the on side is turned on by the current flowing through the resistor.
At the same time, the base potential of the NPN transistor is caused to drop quickly, and at the same time, the resistor causes the PNP
By suppressing the current flowing from transistor T4,
A means is provided for speeding up extraction of the charge accumulated in the base of the NPN transistor T6 and reducing the write pulse width.
以下実施例について詳細に説明する。 Examples will be described in detail below.
第３図を用いて、本発明の作用を説明する。い
まセル１の情報“１”を“０”に書きかえる場合
を考える。ワード線Ｗ１が選択され、Ｗ１の電位
がVXHの時、トランジスタＴ４，Ｔ６がオン、ト
ランジスタＴ３，Ｔ５がオフとすると、Ｔ６から
デイジツト線Ｄ２へ読み出し電流IRが流れてい
る。一方、デイジツト線Ｄ１には、トランジスタ
Ｔ１１からIRが流れている。この時、Ｔ１２のベ
ース電位VrefcをＴ６のベース電位Ｖ１より高い
電位VWHへ上げると同時に、Ｔ１１のベース電位
をVrefcから、Ｔ５のベース電位Ｖ２より低い電
位VWLへ下げるとＴ５がオンして、IRがＴ５から
Ｄ１に流れ出る。この際、Ｔ５のコレクタ電流
は、流れ始めた時点では、Ｔ３がオフ、Ｔ４がオ
ンのため、飽和による電荷が蓄積されているＴ６
のベースおよび抵抗Ｒ２を介して、Ｔ４のコレク
タから供給されるが、Ｒ２に流れる電流が電圧降
下を引き起こす。この電圧降下によりＴ５のコレ
クタ電流の多くがＴ６のベース蓄積電荷の引き抜
きに使用される。この結果、Ｉ＝Ｃ×dv／dt
（Ｃ：拡散容量）より、Ｔ６のベースに蓄積され
ている電荷を速く引き抜くと同時に、Ｖ１の電位
がすみやかに降下する（第４図）。このため、Ｔ
３が、迅速にオンとなり、Ｔ５のコレクタ電流
は、Ｔ３のベースから供給されるようになる。こ
の結果Ｔ４がオフとなる。すなわち、Ｔ３，Ｔ５
がオン、Ｔ４，Ｔ６がオフの状態になり、メモリ
セルのフリツプフロツプが迅速に反転し、セル１
の“１”から“０”への書き込みがすみやかに行
なわれる。 The operation of the present invention will be explained using FIG. Now consider the case where information "1" in cell 1 is rewritten to "0". When word line W1 is selected and the potential of W1 is VXH , transistors T4 and T6 are on and transistors T3 and T5 are off, then a read current I R flows from T6 to digit line D2. On the other hand, I R flows through the digit line D1 from the transistor T11. At this time, when the base potential V refc of T12 is raised to a potential V WH higher than the base potential V1 of T6, and at the same time the base potential of T11 is lowered from V refc to a potential V WL lower than the base potential V2 of T5, T5 is turned on. Then, I R flows out from T5 to D1. At this time, when the collector current of T5 starts flowing, T3 is off and T4 is on, so T6 has accumulated charge due to saturation.
is supplied from the collector of T4 through the base of T4 and the resistor R2, but the current flowing through R2 causes a voltage drop. Due to this voltage drop, most of the collector current of T5 is used to extract the charge accumulated in the base of T6. As a result, I=C×d v /d t
(C: diffusion capacitance), the electric charge accumulated at the base of T6 is quickly extracted, and at the same time, the potential of V1 quickly drops (FIG. 4). For this reason, T
3 is quickly turned on and the collector current of T5 is now supplied from the base of T3. As a result, T4 is turned off. That is, T3, T5
is on, T4 and T6 are off, the flip-flop of the memory cell is quickly reversed, and cell 1 is turned on.
Writing from "1" to "0" is performed promptly.
次に本発明の抵抗付加方法の一例としてメモリ
セルの断面図を示す。 Next, a cross-sectional view of a memory cell is shown as an example of the resistance adding method of the present invention.
第５図に本発明のメモリセルの回路図とその半
導体集積回路用の横断面を示した。回路図で１０
はPNPトランジスタのエミツタ、２０はPNPト
ランジスタのベース、３０はPNPトランジスタ
のコレクタとダブルエミツタ型NPNトランジス
タのベースとの間に付加した抵抗、４０はダブル
エミツタ型NPNトランジスタのエミツタで情報
保持電流を流す。５０はダブルエミツタ型NPN
トランジスタのエミツタで読み出し電流を流す。
６０は、ダブルエミツタ型NPNトランジスタの
ベースである。又横断面図で、１はｐ形領域でラ
テラルPNPトランジスタのエミツタ、２はｎ形
エピタキシヤル領域でラテラルPNPトランジス
タのベース、３はｐ形領域でラテラルPNPトラ
ンジスタのコレクタおよび、PNPトランジスタ
のコレクタとダブルエミツタ型NPNトランジス
タのベースとの間に付加する抵抗および、ダブル
エミツタ型NPNトランジスタのベースを表わす
領域である。４はN+領域でダブルエミツタ型
NPNトランジスタのエミツタで情報保持電流を
流す。５はN+領域でダブルエミツタ型NPNトラ
ンジスタのエミツタで読み出し電流を流す。６は
ダブルエミツタ型トランジスタのベース電極、７
はN+領域でダブルエミツタ型トランジスタのコ
レクタ、８は、酸化膜、９はｐ形基板である。 FIG. 5 shows a circuit diagram of a memory cell of the present invention and a cross section thereof for use in a semiconductor integrated circuit. 10 in circuit diagram
20 is the emitter of the PNP transistor, 20 is the base of the PNP transistor, 30 is a resistor added between the collector of the PNP transistor and the base of the double emitter type NPN transistor, and 40 is the emitter of the double emitter type NPN transistor, through which the information holding current flows. 50 is double emitter type NPN
The read current flows through the emitter of the transistor.
60 is the base of a double emitter type NPN transistor. In the cross-sectional view, 1 is a p-type region, which is the emitter of the lateral PNP transistor, 2 is an n-type epitaxial region, which is the base of the lateral PNP transistor, and 3 is a p-type region, which is the collector of the lateral PNP transistor and the collector of the PNP transistor. This area represents the resistance added between the base of the double emitter type NPN transistor and the base of the double emitter type NPN transistor. 4 is a double emitter type in the N + region
Information retention current flows through the emitter of the NPN transistor. 5 is the N + region, and the read current flows through the emitter of a double emitter type NPN transistor. 6 is the base electrode of the double emitter transistor, 7
is an N + region and is the collector of a double emitter transistor; 8 is an oxide film; and 9 is a p-type substrate.
ところで、メモリセルの回路図における抵抗３
０は、従来のｐ形領域の寄生抵抗を利用するだけ
では、出来ない。しかし、抵抗式Ｒ＝ρ×ｌ／
（ａ×ｂ）、ρ：抵抗率、ｌ：長さ、ａ：幅、ｂ：
深さで示されるように、ｐ形領域の抵抗率ρを増
すか、長さｌを増すか、幅ａを減らすか、深さｂ
を小さくして抵抗３０を必要な値にすることが出
来る。 By the way, resistor 3 in the memory cell circuit diagram
0 cannot be achieved simply by using the conventional parasitic resistance of the p-type region. However, the resistance formula R=ρ×l/
(a×b), ρ: resistivity, l: length, a: width, b:
Either increase the resistivity ρ of the p-type region, increase the length l, decrease the width a, or decrease the depth b, as indicated by the depth
It is possible to reduce the value of the resistor 30 to the required value.
以上説明した如く、本発明の半導体メモリセル
は、メモリセルの書き込みの際、書き込まれるダ
ブルエミツタ型NPNトランジスタのコレクタ電
流が、交差結合した反対側のダブルエミツタ型
NPNトランジスタのベースに蓄積されている電
荷を速く引き抜き、サイリスタを構成するPNP
トランジスタから、すみやかに前記コレクタ電流
を供給するようにしているので、書き込みパルス
幅を低減出来、その特徴を遺憾なく発揮すること
が出来る。
As explained above, in the semiconductor memory cell of the present invention, when writing to the memory cell, the collector current of the double emitter type NPN transistor to be written is transferred to the cross-coupled double emitter type NPN transistor on the opposite side.
A PNP that quickly extracts the charge accumulated in the base of an NPN transistor and forms a thyristor.
Since the collector current is promptly supplied from the transistor, the write pulse width can be reduced and its characteristics can be fully utilized.
第１図は、従来のPNPN交差結合型メモリセ
ルとその周辺回路図、第２図は、PNPN交差結
合型メモリセルの書き込み時における各部の電
圧、電流を示した説明図、第３図は、本発明の一
実施例の半導体メモリセルとその周辺回路図、第
４図は、従来のPNPN交差結合型メモリセルと
本発明の半導体メモリセルとの書き込み時におけ
る比較図、第５図は、本発明の一実施例の断面図
及び回路図である。
Ｔ１〜Ｔ１２……トランジスタ、Ｉ１〜Ｉ４…
…定電流源。
FIG. 1 is a diagram of a conventional PNPN cross-coupled memory cell and its peripheral circuitry, FIG. 2 is an explanatory diagram showing the voltages and currents of various parts during writing in the PPNN cross-coupled memory cell, and FIG. FIG. 4 is a diagram of a semiconductor memory cell according to an embodiment of the present invention and its peripheral circuit. FIG. 4 is a comparison diagram of a conventional PNPN cross-coupled memory cell and a semiconductor memory cell of the present invention at the time of writing. FIG. 5 is a diagram of the present invention. FIG. 1 is a cross-sectional view and a circuit diagram of an embodiment of the invention. T1-T12...transistor, I1-I4...
...constant current source.
Claims (1)
エミツタ型NPNトランジスタのコレクタに接続
し、 上記第1PNPトランジスタのコレクタを第１の
抵抗の一端に接続し、 上記第１の抵抗の他端を上記第１ダブルエミツ
タ型NPNトランジスタのベースに接続し、 第2PNPトランジスタのベースを第２ダブルエ
ミツタ型NPNトランジスタのコレクタに接続し、 上記第2PNPトランジスタのコレクタを第２の
抵抗の一端に接続し、 上記第２の抵抗の他端を上記第２ダブルエミツ
タ型NPNトランジスタのベースに接続し、 上記第１の抵抗の上記他端と上記第１ダブルエ
ミツタ型NPNトランジスタの上記ベースとの第
１共通接続点を上記第２ダブルエミツタ型NPN
トランジスタの上記コレクタに接続し、 上記第２の抵抗の上記他端と上記第２ダブルエ
ミツタ型NPNトランジスタの上記ベースとの第
２共通接続点を上記第１ダブルエミツタ型NPN
トランジスタの上記コレクタに接続し、 上記第１ダブルエミツタ型NPNトランジスタ
の一方のエミツタと上記第２ダブルエミツタ型
NPNトランジスタの一方のエミツタには情報保
持電流を流す電流源に接続され、 上記第１ダブルエミツタ型NPNトランジスタ
の他方のエミツタと上記第２ダブルエミツタ型
NPNトランジスタの他方のエミツタはデイジツ
ト線に接続されてなる半導体メモリセルであつ
て、 上記第1PNPトランジスタおよび上記第2PNP
トランジスタは半導体基板のＮ型不純物領域でベ
ースが形成され、該Ｎ型不純物領域を上記半導体
基板の表面で挟むよう形成された第１と第２のＰ
型不純物領域によつてエミツタとコレクタとがそ
れぞれ形成されたラテラルトランジスタであり、 上記第１ダブルエミツタ型NPNトランジスタ
トランジスタおよび上記第２ダブルエミツタ型
NPNトランジスタは上記ラテラルトランジスタ
の上記コレクタである上記第２のＰ型不純物領域
によつてベースが形成され、該ベース中の二つの
Ｎ型不純物層によつてダブルエミツタが形成さ
れ、上記Ｎ型不純物領域によつてコレクタが形成
され、 該ダブルエミツタを形成する上記二つのＮ型不
純物層のうち半導体メモリセルの上記情報保持電
流を流すほうのＮ型不純物層よりも、読み出し／
書き込み電流を流す方のＮ型不純物層を上記ラテ
ラルトランジスタの上記エミツタを形成する上記
第１のＰ型不純物領域から遠方に配置せしめてな
り、 上記情報保持電流を流すほうの上記Ｎ型不純物
層と上記Ｎ型不純物領域とによつて挟まれた上記
ラテラルトランジスタの上記コレクタである上記
第２のＰ型不純物領域によつて上記第１の抵抗お
よび上記第２の抵抗が形成されてなることを特徴
とする半導体メモリセル。 ２ 上記半導体メモリセルの周囲は酸化膜によつ
て周辺から分離されてなることを特徴とする特許
請求の範囲第１項に記載の半導体メモリセル。[Claims] 1. The base of the first PNP transistor is connected to the collector of the first double emitter type NPN transistor, the collector of the first PNP transistor is connected to one end of the first resistor, and the other end of the first resistor is connected to the collector of the first double emitter type NPN transistor. is connected to the base of the first double-emitter NPN transistor, the base of the second PNP transistor is connected to the collector of the second double-emitter NPN transistor, the collector of the second PNP transistor is connected to one end of the second resistor, and the The other end of the second resistor is connected to the base of the second double emitter type NPN transistor, and the first common connection point between the other end of the first resistor and the base of the first double emitter type NPN transistor is connected to the base of the second double emitter type NPN transistor. 2nd double emitter type NPN
A second common connection point between the other end of the second resistor and the base of the second double-emitter NPN transistor is connected to the collector of the first double-emitter NPN transistor.
Connected to the collector of the transistor, one emitter of the first double emitter type NPN transistor and the second double emitter type of the transistor.
One emitter of the NPN transistor is connected to a current source that flows an information retention current, and the other emitter of the first double emitter type NPN transistor and the second double emitter type
The other emitter of the NPN transistor is a semiconductor memory cell connected to a digit line, and the first PNP transistor and the second PNP
The transistor has a base formed of an N-type impurity region of a semiconductor substrate, and first and second P-type transistors formed to sandwich the N-type impurity region between the surfaces of the semiconductor substrate.
It is a lateral transistor in which an emitter and a collector are each formed by a type impurity region, and the first double emitter type NPN transistor transistor and the second double emitter type NPN transistor transistor are described above.
The NPN transistor has a base formed by the second P-type impurity region which is the collector of the lateral transistor, a double emitter formed by two N-type impurity layers in the base, and a double emitter formed by the second P-type impurity region which is the collector of the lateral transistor. Of the two N-type impurity layers forming the double emitter, the N-type impurity layer through which the information retention current of the semiconductor memory cell flows is more sensitive to read/write.
The N-type impurity layer through which the write current flows is disposed far from the first P-type impurity region forming the emitter of the lateral transistor, and the N-type impurity layer through which the information retention current flows. The first resistor and the second resistor are formed by the second P-type impurity region, which is the collector of the lateral transistor, sandwiched between the N-type impurity region and the N-type impurity region. Semiconductor memory cell. 2. The semiconductor memory cell according to claim 1, wherein the periphery of the semiconductor memory cell is separated from the periphery by an oxide film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61156041A JPS6212999A (en) | 1986-07-04 | 1986-07-04 | Semiconductor memory cell |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61156041A JPS6212999A (en) | 1986-07-04 | 1986-07-04 | Semiconductor memory cell |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6212999A JPS6212999A (en) | 1987-01-21 |
| JPH057797B2 true JPH057797B2 (en) | 1993-01-29 |
Family
ID=15619024
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61156041A Granted JPS6212999A (en) | 1986-07-04 | 1986-07-04 | Semiconductor memory cell |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6212999A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9449669B2 (en) * | 2014-09-25 | 2016-09-20 | Kilopass Technology, Inc. | Cross-coupled thyristor SRAM circuits and methods of operation |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4433471A (en) * | 1982-01-18 | 1984-02-28 | Fairchild Camera & Instrument Corporation | Method for the formation of high density memory cells using ion implantation techniques |
-
1986
- 1986-07-04 JP JP61156041A patent/JPS6212999A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6212999A (en) | 1987-01-21 |
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