JPH0578251B2 - - Google Patents

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a protection device for a reactive power compensator,
In particular, the present invention relates to a protection device for a reactive power compensator suitable for protecting a device that compensates for reactive power of a power transmission bus.

[Conventional technology]

In a system that supplies power to a load via a power transmission bus, when the load changes, both active power and reactive power of the power supplied to the load change.
Therefore, in order to suppress voltage fluctuations due to load fluctuations, a reactor is connected to the bus bar to compensate for the reactive power of the bus bar.

A conventional device of this type is, for example, Figure 17 on page 28 of the Nissin Electric Technical Report (published in 1983, VOL.28.No.
As described in 3), connect a Δ-Y connected high impedance transformer to the power transmission bus through a circuit breaker, and connect each output of the transformer to
A system has been proposed in which a reactor is connected by firing a thyristor to compensate for the reactive power of the bus bar. According to this device, it is possible to compensate for reactive power on the busbar due to load fluctuations, and when a failure occurs inside the transformer output side, it can detect zero-sequence current due to unbalance in the transformer output circuit. However, based on this detection output, the circuit breaker can be tripped to protect the reactive power compensator.

[Problem that the invention seeks to solve]

However, in the above conventional technology, even when an external failure of the transformer occurs, that is, a failure of 1 wire to ground, 2 wire to ground, or 2 wire short circuit occurs in the bus system, zero-sequence current flows to the output circuit of the transformer. No consideration was given to this, and there was a problem that the circuit breaker would trip even in the event of an external failure.

The present invention has been made in view of the above-mentioned conventional problems, and an object thereof is to provide a protection device for a reactive power compensator that can trip a circuit breaker only when an internal failure occurs in the non-signal power compensator. It is in.

[Means for solving problems]

In order to achieve the above object, the present invention connects a three-phase transformer to a power transmission bus through a circuit breaker, and connects a reactor to each output of the transformer to compensate for the reactive power of the bus. , trip command means for outputting a trip command signal when the fundamental wave component of the zero-sequence current of the transformer output circuit exceeds a set level; trip means for tripping the circuit breaker by the trip command signal; failure detection means that outputs a failure signal when the input voltage of The present invention constitutes a protection device for a reactive power compensator, which is provided with signal transmission control means for prohibiting the transmission of a signal to the trip means.

[Effect]

If a failure occurs inside the reactive power compensator,
A trip command signal is output from the trip command means, and the circuit breaker is tripped by the operation of the trip means. On the other hand, if a failure occurs outside the reactive power compensator, the voltage of the power transmission bus becomes unbalanced, and the failure detection means outputs a failure signal, and the trip command means outputs a trip command signal. . When the trip command signal and the fault signal are respectively input to the signal transmission command means, transmission of the trip command signal to the trip means is prohibited and the circuit breaker is maintained in the on state.

[Embodiments of the invention]

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 shows the configuration of a preferred embodiment of the present invention. In FIG. 1, power from a power source 10 is supplied to a load via a power transmission bus 12. As shown in FIG. A three-layer high impedance transformer 1 is connected to the bus line 12 via a circuit breaker 14.
6 is connected. The transformer 16 is connected in a Δ-Y manner, and the Δ side is connected to the bus bar 12 via the circuit breaker 14 . The output side of the transformer 16 is the reactor 1
8, 20, 22, thyristor valve 24, 26,
28, 30, 32, and 34, and is also grounded via a neutral wire 36.
Transformer 16, reactor 18, 20, 22, thyristor valve 24, 26, 28, 30, 32, 3
4. The neutral wire 36 connects the reactive power compensator (hereinafter referred to as
It is called SVC. ) is configured, and the reactor 1 is activated by firing the thyristor valves 24 to 34.
8, 20, and 22 are connected to the bus bar 12 via a transformer 16, so that the reactive power of the bus bar 12 is compensated.

A CT 38 is provided in the middle of the neutral line 36, and the output of the CT 38 is outputted to a comparator 42 via a filter 40. The filter 40 suppresses the third harmonic component of the output signal of the CT 38 and allows only the fundamental component to pass. Comparator 42 is adapted to output a trip command signal when the output signal of filter 40 exceeds a set level. That is, CT38,
The filter 40 and the comparator 42 constitute a trip command means, and when a current of the fundamental wave component of the zero-sequence current flows through the neutral wire 36 and this current exceeds a set level, the comparator 42 issues a trip command. A signal is now being output. When the SVC is in steady operation, the neutral wire 36 has a second
As shown in A of the figure, a third harmonic current is constantly flowing, and when an internal failure occurs due to a short circuit in the thyristor valve 24, a current containing a fundamental wave component in addition to the third wave current flows. Therefore, in this example,
In order to reliably detect internal failures in SVC, CT3
A filter 40 that suppresses the third harmonic current and outputs only the fundamental wave current is inserted into the output of 8.

Furthermore, when an external fault occurs in the SVC, such as a two-wire short circuit on the bus bar 12, the voltage on the bus bar 12 becomes unbalanced, as shown in FIG. As shown in Figure C, a composite current of the third harmonic current and the fundamental current flows. Therefore, the trip command signal is output from the comparator 42 even in the event of an external failure of the SVC.

PT44 is installed on the bus bar 12 near the input side of the transformer 16.
is provided, and the output signal of PT 44 is connected to undervoltage relay 46. Undervoltage relay 46 is adapted to output a fault signal when the voltage detected by PT 44, ie, the input voltage of transformer 16, falls below a set level.
That is, the PT 44 and the undervoltage relay 46 constitute a failure detection means.

The timer 48 is configured to take in the output signal of the comparator 42 and delay the rise time of the trip command signal by a certain period of time _Td1 . The timer 50 receives the output signal of the undervoltage relay 46 and delays the falling time of the failure signal by a certain period of time Td ₂ . and timer 48,
Each of the output signals 50 is supplied to an AND gate 52 serving as a gate circuit. AND
The gate 52 takes in the output signal of the timer 48, takes in the inverted output signal of the timer 50, and outputs a signal obtained by ANDing each signal to a trip device 54 as a trip means. That is, timers 48, 50,
The AND gate 52 transmits the output signal from the comparator 42 to the trip device 54 except when a fault signal is generated, and when a fault signal occurs, the AND gate 52 controls signal transmission to prohibit the transmission of the trip command signal to the trip device 54 using the fault signal. It functions as a means. In addition,
When a trip command signal is output from the AND gate 52, the circuit breaker 14 is tripped by the operation of the trip device 54.

In the above configuration, if an internal failure occurs in the SVC due to a short circuit in the thyristor valve 24, the CT3
8 detects the fundamental wave component of zero current. When the level of this fundamental wave component exceeds the set level,
A trip command signal is output from the comparator 42.
At this time, since the output of the timer 50 is at a low level, a trip command signal is transmitted to the trip device 54 via the timer 48 and the AND gate 52, and the circuit breaker 14 is tripped by the operation of the trip device 54. This allows the SVC to be protected against internal failures of the SVC.

On the other hand, when an external failure such as a two-wire short circuit occurs in the bus bar 12, the voltage of the bus bar 12 decreases and a zero-sequence current containing a fundamental wave component flows in the neutral wire 36, as shown in FIG. This allows comparator 4
2 outputs a trip command signal, and the undervoltage relay 46 outputs a failure signal.
The trip command signal is outputted from the timer 48 with its rise time delayed by a fixed time Td ₁ , and the timer 50 is outputted with its fall time delayed by a fixed time Td ₂ . That is, even if the trip command signal and the fault signal are generated simultaneously, the trip command signal is delayed for a certain period of time, so the output of the AND gate 52 is maintained at a low level by the fault signal. Furthermore, since the fault signal continues to be output until the generation of the trip command signal stops, the output of the AND gate 12 is maintained at a low level from the time an external fault occurs until the external fault is recovered, and the trip device 54 operates. This can prevent the circuit breaker 14 from being tripped.

FIG. 4 shows the configuration of another embodiment of the present invention.

In this embodiment, each line of the bus bar 12 has PT56,5
Connect the primary side of 8,60, PT56,58,6
On the secondary side of 0, PT62, 64, 66, 68, 7
0, 72, full wave rectifier circuit 74, 76, 78, 8
The low value priority circuit 89 is connected through 0, 82, 84, and the output of the low value priority circuit 86 is connected to the undervoltage relay 4.
6, and the other configurations are the same as those shown in FIG. 1, so a description of the other configurations will be omitted.

In this embodiment, the phase voltage of the bus 12 is detected by PT62, 64, 66, and PT68, 70,
72 detects the line voltage of the bus 12, and activates the undervoltage relay 46 by the lowest level output signal among the outputs of the full-wave rectifier circuits 74, 76, 78, 80, 82, and 84. This is what I did.

In this embodiment, in the event of an external two-wire short circuit failure, etc.
Even if the level difference between the faulty phase voltage and the healthy phase voltage is small, an external failure can be reliably detected by detecting the line voltage at the same time as the phase voltage. Furthermore, according to this embodiment, since the undervoltage relay 46 is activated by the output of the low value priority circuit 86, it is not necessary to provide the undervoltage relay 46 for the output of each full-wave rectifier circuit. A fault signal can be generated by one undervoltage relay 46.

In each of the above embodiments, a method was described in which the current flowing through the neutral wire 36 is detected as a zero-sequence current. The above embodiment can also be applied to a system using a CT for zero-phase current detection in the circuit.

〔Effect of the invention〕

As explained above, according to the present invention, SVC
Since the circuit breaker can be tripped only when an internal failure occurs, it is possible to prevent the SVC from malfunctioning due to an external failure.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram showing one embodiment of the present invention, and FIG.
The figure is a waveform diagram of each part at the time of an internal failure and an external failure. Figure 3 is a time chart for explaining the operation of each part at the time of an external failure. Figure 4 is a main part configuration showing another embodiment of the present invention. It is a diagram. 12... Bus bar, 14... Circuit breaker, 16... Transformer, 18, 20, 22... Reactor, 24, 2
6, 28, 30, 32, 34...Thyristor valve, 36...Neutral line, 38...CT, 40...Filter, 42...Comparator, 40...PT, 46...
...Undervoltage relay, 48, 50...Timer, 52
...AND gate, 54...Trip device, 86
...Low value priority circuit.

Claims (1)

[Scope of Claims] 1. A three-phase transformer is connected to a power transmission bus through a circuit breaker, and a reactor is connected to each output of the transformer to compensate for the reactive power of the bus, wherein the transformer trip command means for outputting a trip command signal when the fundamental wave component of the zero-sequence current of the transformer output circuit exceeds a set level; trip means for tripping the circuit breaker by the trip command signal; A fault detection means that outputs a fault signal when the level falls below a set level; a means for transmitting the output signal of the trip command means to the trip means except when a fault signal is generated; and a means for tripping the trip command signal using the fault signal when a fault signal is generated. a signal transmission control means for prohibiting transmission to;
A protection device for a reactive power compensator, characterized in that it is provided with: 2. In claim 1, the signal transmission control means receives a trip command signal and delays transmission of the trip command signal for a certain period of time.
and a second timer that receives the fault signal and outputs the fault signal, and continues to output the fault signal until the generation of the trip command signal is stopped.
The output signals of the timer and the first and second timers are taken in, and the signal from the first timer is output to the trip means except when a failure signal is input, and the failure signal from the second timer is output when a failure signal is input. According to the first
A protection device for a reactive power compensator, comprising: a gate circuit for cutting off a signal transmission path connecting a timer and a trip means.