JPH0580751B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an optical disk processing device used for recording and reproducing information processing data.

Summary of the Invention The present invention generates a multi-byte boundary pattern to indicate a data start position following a synchronization pattern, and each of the boundary patterns includes a code corresponding to the number of bytes up to the data start position. The read signal from the medium is
In the optical disk processing apparatus, if a predetermined number or more of the plurality of boundary patterns are detected, the data start position is determined by referring to the code included in the plurality of boundary patterns. Even if there is a defect in the medium, the data start position can be determined accurately and data reliability can be improved.

Prior Art In a conventional optical disk processing device, following a synchronization pattern of a fixed period for synchronization pull-in,
Write a byte boundary pattern (for example, (19 _H ) in hexadecimal), then write data, and when reading, when the above 1-byte boundary pattern is detected, the actual It is determined that the data is necessary for

The conventional method described above can be used satisfactorily for devices with a good data error rate, but when applied to optical disks with high-density recording, the error rate worsens and the probability of erroneous data start positions increases. . If the data start position is correct, even if a few dozen bits drop after that, the data error can be corrected using the error correction circuit and the correct data can be reproduced. However, if the data start position is incorrect error correction is not possible. That is, there is a drawback that if a drop occurs in the boundary pattern, correct data cannot be reproduced.

Problems to be Solved by the Invention The present invention makes it possible to determine the correct data start position even when a drop occurs in the boundary pattern due to a defect in the medium, etc., and provides highly reliable data suitable for high-density recording. Provides optical disk processing equipment.

Means for Solving the Problems The optical disk processing device of the present invention has a boundary pattern that generates a plurality of bytes of a boundary pattern including a code and an illegal code, each of which corresponds to the number of bytes up to the start position of data, following a synchronization pattern. A data writing section having a generating circuit detects each of the boundary patterns of the plurality of bytes using an illegal code in a read signal from a medium on which the output of the data writing section is recorded, and detects a specified number or more of boundary patterns. The present invention is characterized in that it comprises a data reading section having a boundary pattern detection section capable of determining a data start position based on the code in the detected boundary pattern.

Embodiments of the Invention Next, the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. In other words, when writing data,
When the control circuit 1 receives the write command 102, it instructs the boundary pattern generation circuit 3 to send its output to the selector circuit 4. The boundary pattern generation circuit 3 outputs a boundary pattern 106 of multiple bytes following a synchronization pattern of a constant period. On the other hand, the write data 101 is modulated by the modulation circuit 2 and supplied to the selector circuit 4, and the selector circuit 4 outputs the output of the modulation circuit 2 following the synchronization pattern input from the boundary pattern generation circuit 3 and the plurality of boundary patterns. 105 is selectively output, write data 107 is supplied to the write amplifier 5, and written on the medium. A code corresponding to the number of bytes up to the data start position is added to each of the plurality of boundary patterns.

During reading, the reproduced data 108 output from the read sense section 10 is input to the synchronization circuit 8, separated into synchronization clock bits and data bits, and sent to the boundary pattern detection section 7. When the boundary pattern detection unit 7 detects at least one of the plurality of boundary patterns, it determines the data start position by referring to the code added to the boundary pattern. Boundary pattern detection section 7
The details will be described later. Further, the data after the data start position is sent to the error correction circuit 6, error corrected, and output as corrected data 103.

Note that if the boundary pattern detection unit 7 erroneously detects the data start position early, an illegal code is detected again after that, and the boundary pattern error detection circuit 9 determines that the first detected position is an error. The code is then reported to the control circuit 1, and the number of times the illegal code is detected is counted. The data of the number of bytes corresponding to the count value is an extra byte before the data start position, and is truncated before being input to the error correction circuit 6. Therefore, subsequent data is sent to the error correction circuit 6 and correct data is reproduced.

FIG. 2 shows an example of a boundary pattern. Same figure A
indicates the information arrangement format recorded on sector #N of the medium, and the track number sector number 2 follows the synchronization pattern section 20 and the boundary pattern section 21.
2 is written, and after a certain space, the synchronization pattern section 20 and the boundary pattern section 21 are written again,
Following this, the data section 23 is written, and finally the data end pattern section 24 is written. FIG. B is a diagram showing details of the boundary pattern section 21, and includes 3-byte boundary pattern information 81 _H , 41 _H ,
It is composed of 21 _H. In reality, as shown in FIG. 3C, a signal is recorded in which the pattern information is modulated according to a certain rule. The law of modulation in this example is that information “1” is 2 of “01”.
It is converted into bits, and information “0” is converted into “00” or “10”. However, the above “00” is “01”
"10" is used after "00" or "10". According to this modulation law, odd numbered bits do not contain information, information can be restored using only even numbered bits, and bit synchronization information can be obtained using odd numbered bits, so bit synchronization information is lost. never be done. Hereinafter, the odd numbered bits will be referred to as clock bits and the even numbered bits will be referred to as data bits. However, in Figure 2 C
Note that the bits surrounded by are in violation of the modulation law described above.

In the figure, the first even-numbered 3 bits (3 data bits) of each byte are underlined.
“100”, “010” and “001” respectively correspond to the number of bytes from each boundary pattern to the data start position. Furthermore, the latter 8 bits (indicated by IC in the figure) of each boundary pattern are a code (illegal code) that does not occur in the data section due to a violation of the modulation rule. The illegal code can be identified by the code "1010", which is underlined in the figure and consists only of odd-numbered bits (clock bits), so this will be referred to as an illegal clock pattern. .

FIG. 3 is a block diagram showing details of the boundary pattern detection section 7 and boundary pattern error detection circuit 9 shown in FIG. The clock bit shift register 51 receives clock bits from the synchronizing circuit 8 (shown in FIG. 1).
CLK is input and taken into clock bit shift register 51 by strobe signal 202. The data bit DATA input from the synchronization circuit 8 to the data bit shift register 56 is taken into the data bit shift register 56 by a strobe signal 209. The output of the clock bit shift register 51 is input to a decoding circuit 52, and when the decoding circuit 52 detects an illegal clock pattern of "1010", it outputs an illegal detection signal 204 and sets a flip-flop 53. When gate circuit 54 is opened by the output of flip-flop 53, byte counter circuit 5
5 operates, and the byte counter circuit 55 reads the first register 57 and second register 58 at 1-byte intervals.
send a shift signal to. Illegal detection signal 204
is also sent to the load clock generation circuit 64 and the data position error detection circuit 63. Each time the illegal detection signal 204 is input, the load clock generation circuit 46 outputs the first to third registers 57 to 59.
are set sequentially.

On the other hand, the upper 3 bits of data bit DATA are
The strobe signal 209 loads the data bit shift register 56, the output of the data bit shift register 56 is set in the first register 57 by the first illegal detection signal 204, and the output is set in the first register 57 by the next illegal detection signal 204. 2
The next illegal detection signal 2 is stored in the register 58.
04 is set in the third register 59.
Therefore, when a normal boundary pattern is input, the code “100” is loaded into the first register 57 in the first first boundary pattern byte, and “010” is loaded in the second boundary pattern byte. 2 register 58, and “001” is loaded into the third register 59 in the final third boundary pattern byte. Since the first register 57 and the second register 58 each perform a shift operation based on the output of the byte counter circuit 55, when the third boundary pattern byte is input, the first register 57
7 becomes “001” by two shift operations,
The second register 58 is also set to "001" by one shift operation. Therefore, at the time when the third boundary pattern is input, the first to third registers 57 to 59 all become "001".

FIGS. 4A to 4C are diagrams showing states in which the contents of the first register 57 to the third register 59 are shifted, respectively. That is, the first register 57 and the second register 58 are both set to "001" at the time of input of the third boundary pattern byte.

When the decode circuit 60 decodes "001", it sets the data area detection circuit 62 via the OR circuit 61. Therefore, if any one or more of the first to third boundary pattern bytes are correct, it is possible to determine the data start position based on the output of the data area detection circuit 62.
For example, if the first illegal clock pattern is not detected because the first boundary pattern byte is incorrect, and the illegal clock pattern is detected for the first time in the second boundary byte, the second The code “010” of the boundary pattern byte is set in the first register 57, and when the next third boundary pattern byte is input, the first register 57 is shifted to “001”, so the decoding circuit 60 is decoded to set the data area detection circuit 62. Further, even if an illegal clock pattern is not detected in either the first or second boundary pattern byte, if the third boundary pattern byte is correct, “001” in the third boundary pattern byte is set to the first register 57. This is because the data area detection circuit 62 is immediately set when the data area detection circuit 62 is decoded by the decoding circuit 60.

Next, when the data area detection circuit 62 is set at a point earlier than the correct data start position due to an error in the read data, the data position error detection circuit 63 sets the number of illegal detection signals 204 that will be input thereafter. and sends the count value to the control circuit 1 and error correction circuit 6. The control circuit 1 and the error correction circuit 6 can perform a process of deleting the first few unnecessary bytes for realignment based on the above count number. For example, when the first boundary pattern byte is input, if the code "001" is loaded into the first register 57 due to an error in the data bit, the data start position will be erroneously detected two bytes earlier. . In this case, since illegal clock patterns are detected when the second and third boundary pattern bytes are input, the data position error detection circuit 63 counts them and reports them to the control circuit. deletes 2 bytes of data.

As described above, in this embodiment, if any one of the three boundary patterns is detected correctly, the data start position can be recognized correctly, so even if several drop bits are in the boundary pattern, This has the effect that data can be read. Furthermore, as a result, it is possible to effectively utilize the error correction circuit and provide a high-density optical disk device.

Effects of the Invention As described above, in the present invention, a code corresponding to the number of bytes up to the data start position is added to each of a plurality of boundary pattern bytes and written to the medium, and when reading, one of the plurality of boundary pattern bytes is , if any one of them can be detected correctly,
Since the configuration is configured so that the data start position can be correctly recognized by referring to the above code, even if there is a defect in part of the boundary pattern byte, the correct data start position can be recognized and the data can be read. be. Furthermore, as a result, it is possible to fully utilize the capability of the data correction circuit to provide a high-density optical disk device.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention;
FIG. 2 is a diagram showing an example of the structure of the boundary pattern in the above embodiment, FIG. 3 is a block diagram showing details of the boundary pattern detection section and the boundary pattern error detection circuit in the above embodiment, and FIG. 4 is a diagram showing the details of the border pattern detection circuit in the above embodiment. 1st of
- It is a figure for explaining an example of the shift operation of a 3rd register. In the figure, 1: control circuit, 2: modulation circuit,
3: Boundary pattern generation circuit, 4: Selector circuit,
5: Write amplifier, 6: Error correction circuit, 7: Boundary pattern detection section, 8: Synchronization circuit, 9: Boundary pattern error detection circuit, 10: Read sense section, 2
0: Synchronization pattern section, 21: Boundary pattern section, 2
2: Track number sector number, 23: Data section,
24: Data end pattern section, 51: Clock bit shift register, 52: Decode circuit, 5
3: Flip-flop, 54: Gate circuit, 5
5: Byte counter circuit, 56: Data bit shift register, 57: First register, 58: Second
Register, 59: Third register, 60: Decode circuit, 61: OR circuit, 62: Data area detection circuit, 63: Data position error detection circuit, 64: Load clock generation circuit, 101: Write data,
102: Write command, 103: Correction data, 20
2,209: Strobe signal, 204: Illegal detection signal.

Claims (1)

[Scope of Claims] 1. A data writing unit having a boundary pattern generation circuit that generates a plurality of bytes of boundary patterns each including a code and an illegal code, each of which corresponds to the number of bytes up to the start position of the data, following the synchronization pattern; Each of the plurality of byte boundary patterns is detected based on the illegal code in the read signal from the medium on which the output of the data writing unit is recorded, and when more than a specified number of boundary patterns are detected, the code in the detected boundary pattern is detected. What is claimed is: 1. An optical disk processing apparatus comprising: a data readout section having a boundary pattern detection section capable of determining a data start position based on the data readout section. 2. In the optical disk processing device according to claim 1, the data reading unit detects the data start position by detecting the illegal code after the boundary pattern detection unit erroneously detects the data start position. The device is characterized by being equipped with a data position error detection circuit that detects detection errors.