JPH0580873B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a reproducing apparatus that demodulates a modulated video signal reproduced from a recording tape, writes it into a memory, and uses a read signal from the memory as a reproduced output.

[Summary of the invention]

The present invention includes a demodulation circuit that demodulates a video signal reproduced from a magnetic tape, a sync signal separation circuit that separates a sync signal from the video signal, and an A/C converter that converts an analog output signal from the demodulation circuit into a digital signal.
A D converter and a clamp that supplies the output signal of this A/D converter to a digital low-pass filter, latches pedestal data for each horizontal synchronization signal, and clamps it to a predetermined value based on this pedestal data and a reference value. a memory circuit that stores the output signal of the clamp circuit in accordance with the separated synchronization signal, and a pseudo synchronization signal generator that generates a pseudo synchronization signal when the magnetic tape is being played back at a speed different from that during recording. and a circuit for outputting the output signal from the memory circuit during variable speed playback to play back at a speed different from that for recording, and switching to the output signal from the pseudo synchronization signal generation circuit instead of the normal synchronization signal. By using a playback device that is characterized by outputting images, stable clamping is performed, and high-quality images without bar noise etc. can be obtained, and synchronization is prevented from being disturbed. .

[Conventional technology]

Rotating head video tape recorder (VTR)
When performing variable speed playback such as slow speed, double speed playback, picture search, etc. by changing the tape running speed, the playback magnetic head scans across a plurality of recording tracks T formed diagonally on the magnetic tape. (See dashed line in Figure 3). In this case, for example, if a guard band is formed between tracks, or if, for example, inclined azimuth recording is performed in which the recording azimuth is different between adjacent tracks, the modulated video signal obtained from the reproducing magnetic head may be The envelope becomes as shown in FIG. 4A.
That is, when scanning between tracks, the output of the modulated video signal becomes extremely small. Conventionally, during variable speed reproduction, the modulated video signal obtained from the reproduction magnetic head is demodulated and output as is.

[Problem that the invention seeks to solve]

Conventionally, when performing variable-speed playback, the modulated video signal obtained from the playback magnetic head is demodulated and the playback output is directly output. This has the disadvantage that bar noise appears on the screen, synchronization is disrupted in this area, and skew distortion occurs on the screen.

In view of these points, the present invention also provides the following features during variable speed playback:
This makes it possible to obtain a video signal with a good S/N ratio and a stable synchronization signal.

[Means for solving problems]

In order to solve the above problems, the present invention includes a demodulation circuit 15 that demodulates the video signal reproduced from the magnetic tape 2, a sync signal separation circuit 15 that separates the sync signal from the video signal, and an analog output from the demodulation circuit 5. An A/D converter 6 converts the signal into a digital signal, and the output signal of this A/D converter 6 is supplied to a digital low-pass filter 10, which latches the pedestal data for each horizontal synchronization signal. A clamp circuit 7 that clamps to a predetermined value based on a reference value, memory circuits 9A and 9B that store the output signal of this clamp circuit 7 in accordance with a separated synchronization signal, and a magnetic tape 2 that is different from the one at the time of recording. A pseudo synchronization signal generating circuit 27 generates a pseudo synchronization signal when the speed is being reproduced at a different speed, and outputs the output signal from the memory circuits 9A and 9B during variable speed reproduction when reproducing at a speed different from that during recording. This reproducing apparatus is characterized in that the output signal from the pseudo synchronization signal generating circuit 27 is switched to and outputted instead of the normal synchronization signal.

[Operation] During variable speed reproduction, only demodulated video signals when the reproduced modulated video signal is at a predetermined level or higher are intermittently and sequentially supplied to the memories 9A and 9B and written to predetermined addresses. As a result, memory 9
Continuous video signals with good S/N ratio are read from A and 9B. Also, during variable speed playback, memory 9
A synchronization signal P _syoc is added to the read signals from A and 9B, and a video signal with a stable synchronization signal and a good S/N ratio is obtained as a playback output.

〔Example〕

Hereinafter, one embodiment of the present invention will be described with reference to FIG.

In the figure, 1 is a tape guide drum;
A magnetic tape 2 is wound diagonally around this drum 1 with an angular range of approximately 180°, and is made to run at a predetermined speed. On this magnetic tape 2, for example, one of the FM modulated video signals is stored.
A field is recorded on one track, and adjacent tracks have different recording azimuths.

Further, 3A and 3B are rotating magnetic heads having different azimuth angles, and are arranged with an angular interval of 180°. These heads 3A and 3B are made to rotate once in one frame, and therefore,
The heads 3A and 3b are configured to scan the magnetic tape 2 every other field.

The above is similar to the conventionally known rotary two-head type reproducing apparatus, and the modulated video signal is reproduced field by field by the heads 3A and 3B.

The modulated video signals reproduced by heads 3A and 3B are supplied to FM demodulation circuit 5 via reproduction amplifier 4. The demodulated video signal is converted into digital data by an A/D converter 6, and after being subjected to, for example, pedestal clamping by a clamp circuit 7, it is sent to field memories 9A and 9B via fixed terminals on the A side and B side of the changeover switch 8, respectively. is supplied to This changeover switch 8 is alternately switched to the A side and the B side for each field.

Further, the clamp circuit 7 is configured as shown in FIG. 2, for example. That is, the digital data of the video signal from the A/D converter 6 is supplied to the digital low-pass filter 10, and high frequency component noise is removed. Further, this digital data from which noise has been removed is supplied to the D flip-flop 11, and the pedestal data is latched every horizontal period by the signal _fH . The adder 12 outputs differential voltage data between this pedestal data and the reference voltage data V _R. Then, interpolation of this differential voltage data is performed by a digital low-pass filter 13, the differential voltage data is subtracted from the digital data of the video signal by an adder 14, and the output thereof, that is, the output of the clamp circuit 7, is subjected to pedestal clamping. Digital data of the video signal is obtained. This clamp circuit 7 is of a feed-forward type, has a fast response speed, and performs accurate clamping. Furthermore, since the video signal does not pass through a capacitor or the like, sag is less likely to occur.
Incidentally, a sink tip clamp is also possible.

Further, the video signal obtained from the FM demodulation circuit 5 is supplied to a synchronization separation circuit 15, and the horizontal synchronization signal P _H obtained from this is supplied to a PLL circuit 16.
A write clock signal CLK _W synchronized with the synchronization signal P _H is obtained from the PLL circuit 16 and supplied to the write address signal generation circuit 17 .
The write address signal W _AD from this generation circuit 17 is supplied to field memories 9A and 9B.

Further, the modulated video signal obtained from the amplifier 4 is supplied to a level discrimination circuit 18. When the level of the modulated video signal is higher than a predetermined level, the determination circuit 18 outputs a high level "1", for example.
At other times, a discrimination signal S _D having a low level "0" is obtained. This discrimination signal S _D is supplied as a write control signal to the field memories 9A and 9B via fixed terminals on the A side and B side of the changeover switch 19, respectively. The field memories 9A and 9B are in a write state only when the discrimination signal S _D is at a high level "1", and are in a read state at other times. In addition, the changeover switch 19
is switched for each field in conjunction with the changeover switch 8. That is, when the changeover switch 8 is switched to the A side and the B side, the changeover switch 19 is switched to the A side and the B side, respectively.

Further, 20 is an oscillator, and a read clock signal CLK _R from this oscillator 20 is supplied to a read address signal generation circuit 21. Then, the read address signal R _AD from this generation circuit 21
is supplied to field memories 9A and 9B.

Further, the digital data of the video signals read from the field memories 9A and 9B are supplied to fixed terminals on the A side and B side of the changeover switch 22, respectively. The changeover switch 22 is switched for each field in conjunction with the changeover switch 8. That is, when the changeover switch 8 is switched to the A side and the B side, the changeover switch 22 is switched to the B side and the A side, respectively.

The digital data of the video signal obtained from this changeover switch 22 is supplied to a fixed terminal on the N side of a changeover switch 23. The digital data of the video signal obtained from this changeover switch 23 is converted into an analog signal by a D/A converter 24 and obtained at an output terminal 25.

Further, an oscillation signal is supplied from the oscillator 20 to a timing generation circuit 26, and a timing signal _ST from this generation circuit 26 is supplied to a synchronization signal generation circuit ₂₇ . A horizontal/vertical synchronizing signal _Psyoc is generated and supplied to the fixed terminal on the T side of the changeover switch 23.

Further, the timing signal _ST from the generation circuit 26 is supplied as a control signal to the changeover switch 23 via the AND gate 28, and the changeover switch 23
Based on this timing signal S _T , the synchronization signal
It is connected to the T side during the P _syoc period, and connected to the A side at other times. The AND gate 28 is supplied with a signal S _TR that becomes high level “1” only during variable speed reproduction.
The timing signal _ST is supplied to the changeover switch 23 only during variable speed reproduction.

Incidentally, a servo reference signal S _REF is generated from the oscillator 20, and the drum servo and capstan servo are operated by this servo reference signal S _REF , so that the read phase and write phase of the field memories 9A and 9B are synchronized. ing.

This example is configured as described above, and in a certain field, changeover switches 8 and 19 are connected to the A side,
The digital data of the video signal is supplied to the field memory 9A to enable writing, and the changeover switch 22 is connected to the B side, and the digital data of the video signal read from the field memory 9B is transferred from the changeover switch 22. can get. In addition, in the field next to a certain field, the changeover switches 8 and 19 are connected to the B side,
The digital data of the video signal is supplied to the field memory 9B to enable writing, and the changeover switch 22 is connected to the A side, and the digital data of the video signal read from the field memory 9A is transferred from the changeover switch 22. can get.

When performing variable speed reproduction such as slow speed, double speed, and picture search by changing the tape running speed, the heads 3A and 3B scan across multiple recording tracks formed on the magnetic tape. The envelope of the modulated video signal obtained from 3B is as shown in FIG. 4A, as described above. That is, when scanning between tracks, the output of the modulated video signal becomes extremely small. In this case, a discrimination signal S _D as shown in FIG. 4B, for example, is obtained from the discrimination circuit 18. Therefore, when performing this variable speed reproduction, when the discrimination signal S _D is at a high level "1", the write address signal W _AD of the field memory 9A or 9B on the switched side of the changeover switch 8 is Digital data of the video signal is written to the address. Incidentally, at this time, the digital data written in the same manner before the previous frame remains at the address of the field memory 9A or 9B to which no writing is performed. Therefore, when variable speed reproduction is performed, digital data is written intermittently into the field memory 9A or 9B, but after several frames have elapsed, one field's worth of digital data is written. Therefore, digital data of a continuous video signal can be obtained from the changeover switch 22.

In addition, when performing this variable speed playback, the signal S _TR supplied to the AND gate 28 becomes high level, so the timing signal S _T is supplied to the changeover switch 23, and the video signal obtained from the changeover switch 22 is digitalized. The synchronization signal portion of the data is replaced with the synchronization signal P _syoc generated by the synchronization signal generation circuit 27, which is output via the D/A converter 24.

Note that during normal playback, the heads 3A and 3B correctly scan the recording tracks on the magnetic tape 2, so the modulated video signals played back from the heads 3A and 3B are always at a high level, and the discrimination signal S _D is always at a high level. The level becomes “1”. Also, and gate 28
Since the signal _STR supplied to the switch 22 has a low level "0", the digital data of the video signal obtained from the changeover switch 22 is supplied as is to the output terminal 25 via the D/A converter 24. Other than that, the operation is the same as when performing variable speed playback.

As described above, according to this example, when performing variable speed playback, the digital data of the video signal when the modulated video signal from the heads 3A, 3B is at a predetermined level or higher is intermittently written into the field memories 9A, 9B. , this field memory 9A, 9B
Since it is obtained by reading digital data of a more continuous video signal, it is possible to obtain a video signal with a good S/N ratio, and it is possible to prevent bar noise from appearing on the screen. Further, according to this example, when performing variable speed playback, the field memory 9
Since the synchronization signal portion of the digital data of the video signal read from A and 9B is replaced with the synchronization signal P _syoc from the synchronization signal generation circuit 27, a video signal with a stable synchronization signal is obtained and skew distortion is prevented from occurring. can do.

Also, according to this example, the read address signal
R _AD is the stable clock signal from oscillator 20.
Since it is generated based on CLK _R , a stable video signal without jitter can be obtained. Also,
According to this example, when performing variable speed playback, head 3
Only when the level of the modulated video signal obtained from A and 3B is above a predetermined level, the field memories 9A and 9
Since writing is performed on B, for example, in the case of so-called segment recording in which recording is performed only on a part of each track, it can also be applied to simultaneous two-track recording.

Further, according to this example, since the clamp circuit 7 is provided, the DC level between each track is kept constant during variable speed reproduction, for example, and horizontal stripe noise can be prevented.

In the above embodiment, the AND gate 28
A timing signal S _T to the changeover switch 23 is provided.
Although the supply of is controlled, AND gate 2
8, the synchronizing signal generating circuit 27 and the timing generating circuit 26 may be configured to operate only during variable speed reproduction. Further, for example, the timing generation circuit 26 may be connected to another circuit (for example, the generation circuit 2
1), an AND gate 28 may be provided and the synchronizing signal generating circuit 27 may be configured to operate only during variable speed reproduction.

Further, in the above-mentioned embodiment, the discrimination circuit 18 is configured to operate even during normal playback, but during normal playback, the discrimination operation of this discrimination circuit 18 is stopped and the signal S _D is always at a high level "1". ”.

〔Effect of the invention〕

According to the present invention described above, during variable speed playback, only the demodulated video signal when the played modulated video signal is at a predetermined level or higher is written into the memory,
A continuous video signal is obtained from this memory, and a synchronization signal is added to the video signal from this memory to be used as a playback output, so a video signal with a good S/N and a stable synchronization signal is obtained as a playback output. be able to. Therefore, bar noise and skew distortion on the playback screen can be prevented. Further, according to the present invention, during variable speed playback,
Since only the demodulated video signal when the reproduced modulated video signal is at a predetermined level or higher is written into the memory, the present invention can also be applied to the case of reproducing a tape on which segment recording has been performed. Additionally, by adding a clamp circuit, the gap between tracks during variable speed playback can be increased.
The DC level is kept constant and horizontal stripe noise can be prevented.
Furthermore, when considered as a clamp circuit, the response is quick and a highly accurate configuration can be achieved.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram showing one embodiment of the present invention, and FIG.
The figure is a block diagram of a clamp circuit used in one embodiment, and FIGS. 3 and 4 are diagrams for explaining the present invention, respectively. 2 is a magnetic tape, 3A and 3B are rotating magnetic heads, 5 is an FM demodulation circuit, 8, 19, 22 and 23
is a changeover switch, 9A and 9B are field memories, 17 is a write address signal generation circuit, 18
21 is a level discrimination circuit, 21 is a read address signal generation circuit, 25 is an output terminal, 26 is a timing generation circuit, 27 is a synchronization signal generation circuit, and 28 is an AND gate.

Claims (1)

[Scope of Claims] 1. A demodulation circuit that demodulates a video signal reproduced from a magnetic tape, a sync signal separation circuit that separates a sync signal from the video signal, and converts an analog output signal from the demodulation circuit into a digital signal. An A/D converter that supplies the output signal of the A/D converter to a digital low-pass filter, latches pedestal data for each horizontal synchronization signal, and clamps it to a predetermined value based on this pedestal data and a reference value. a clamp circuit for storing the output signal of the clamp circuit in accordance with the separated synchronization signal; and a synchronization signal generation circuit, which outputs the output signal from the memory circuit during variable speed playback to reproduce at a speed different from that during recording, and outputs the output signal from the pseudo synchronization signal generation circuit in place of the normal synchronization signal. A playback device characterized in that the playback device outputs the output by switching to.