JPH0582652A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To output a logic signal required for analyzing the caused defect of a logic action on an LSI to the outside of the LSI and to accurately measure the signal by a method wherein one part of an interconnection in the uppermost layer is corrected and an output circuit in which an unused cell in an external interface buffer region is connected to the output of an arbitrary internal logic cell is formed. CONSTITUTION:Interconnection layers are formed selectively, by using an FIB apparatus, between a terminal 4 installed in the uppermost layer and a GND interconnection 7, between a terminal 5 and a power-supply interconnection 8 as well as between a terminal 6 and an output line for an arbitrary internal logic cell. Then, connecting parts 4a, 5a, 6a are formed. An inverter circuit which is provided with a voltage driving ability which is nearly the same as that of an external output buffer is constituted; an output inversion signal from the internal logic cell is output to a bonding pad 9. Thereby, a logic signal required for analyzing the caused defect of a logic action on an LSI is output to the outside of the LSI, the signal can be measured accurately, and the time for the analysis can be shortened.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device.

[0002]

2. Description of the Related Art In an LSI such as a gate array system, the degree of redesign due to a logic design mistake or the like is increasing with the increase in logic scale in recent years.

In the conventional semiconductor integrated circuit device, only the logic signal set in the design is output to the outside of the LSI.
Since an arbitrary internal logic signal cannot be output to the outside of the LSI, if a logic operation failure occurs, apply a probe to the output line of the internal logic cell to directly output the logic signal necessary for analysis. I was taking it out.

[0004]

In this conventional semiconductor integrated circuit, the power supply driving capability of the internal cell is low, and the signal taken out from the output line of the internal logic cell is affected by the load capacitance and connection resistance of the measuring instrument. Analysis was difficult because accurate measurements were not possible.

Further, in order to obtain a sufficient output by utilizing an unused external output buffer, it is necessary to redesign a plurality of masks to form a measuring circuit, which increases the development period. There was a problem of inviting.

[0006]

In a semiconductor integrated circuit device of the present invention, an unused cell composed of a CMOS transistor provided in an external interface buffer region of an LSI having an internal cell region, a GND provided in the uppermost layer, and a power supply wiring are provided. A first terminal connected to one transistor of the unused cell in the uppermost layer near the GND wiring, and a second terminal connected to the other transistor in the uppermost layer near the power wiring. A terminal and a third terminal provided on the uppermost layer connected to the input signal wiring of the unused cell are provided.

[0007]

1 is a layout diagram showing an embodiment of the present invention.

As shown in FIG. 1, an N channel MOS transistor 2 and a P channel transistor 3 provided in an external interface buffer region of an LSI having an internal cell region of a gate array system, and a source region of the N channel MOS transistor 2 are provided. A terminal 4 provided near the uppermost GND wiring 7 connected to the connected lower wiring 10;
The terminal 5 connected to the lower layer wiring 11 connected to the source region of the channel MOS transistor 3 and provided near the uppermost power supply wiring 8 and the lower layer connected to the gate electrodes of the N-channel and P-channel MOS transistors 2 and 3 The terminal 6 provided on the uppermost layer connected to the input signal wiring 12 and the bonding pad 9 provided on the uppermost layer connected to the output wiring 13 on the lower layer connected to the drain regions of the N-channel and P-channel MOS transistors 2 and 3. And the unused cell 1 is configured.

FIG. 2 is a layout diagram showing an application example of the present invention.

As shown in FIG. 2, the terminal 4 provided on the uppermost layer
To the GND wire 7 and between the terminal 5 and the power supply wire 8 and between the terminal 6 and the output line of an arbitrary internal logic cell.
Using an IB (Focus Ion Beam) device, a wiring layer is selectively formed to provide connection portions 4a, 5a, 6a, and an inverter circuit having substantially the same voltage drive capability as an external output buffer is configured to configure an internal logic cell. An output inversion signal is output to the bonding pad 9.

Instead of using the FIB, only the uppermost wiring forming mask may be modified.

Further, by applying the technique of the present invention, the output of an arbitrary internal logic cell is taken out, and a part of the circuit is modified or another LSI is used.
By combining with, there is an advantage that circuit correction and conversion to a new model are possible without redesign.

[0013]

As described above, the present invention is configured as an output circuit in which an unused cell in the external interface buffer area is connected to the output of an arbitrary internal logic cell by modifying a part of the wiring of the uppermost layer. Logic signals that are necessary for analysis when a logic operation failure occurs on the LSI.
There is an effect that it is possible to output the signal to the outside of the LSI to accurately measure the signal and to shorten the analysis time.

[Brief description of drawings]

FIG. 1 is a layout diagram showing an embodiment of the present invention.

FIG. 2 is a layout diagram showing an application example of the present invention.

[Explanation of symbols]

 1 Unused Cell 2 N-Channel MOS Transistor 3 P-Channel MOS Transistor 4, 5, 6 Terminals 4a, 5a, 6a Connection 7 GND Wiring 8 Power Wiring 9 Bonding Pad 10, 11 Lower Layer Wiring 12, 13 Signal Wiring

Claims (2)

[Claims] 1. An unused cell composed of a CMOS transistor provided in an external interface buffer area of an LSI having an internal cell area, a GND and a power supply wiring provided in an uppermost layer, and connected to one transistor of the unused cell. A first terminal provided on the uppermost layer near the GND wiring and a second terminal provided on the uppermost layer near the power supply wiring connected to the other transistor and an input signal wiring of the unused cell. And a third terminal provided on the uppermost layer as a semiconductor integrated circuit device. 2. A connection part for connecting the first terminal and the GND wiring, the second terminal and the power supply wiring, and the third terminal and the internal logic cell to form an output circuit of the internal logic cell. Item 1. A semiconductor integrated circuit device according to item 1.