JPH0583142A - Encoded data processing device - Google Patents

Abstract

(57) [Summary] [Purpose] To significantly reduce the circuit scale for executing LOT and inverse LOT operations. [Structure] The Y stage in the first half of the LOT operation is divided into a Y ₁ stage 22 that can be operated by closing it in one block and a Y ₂ stage 23 that allows two blocks to be operated together, and the following A one-block line memory 24 is provided for storing data until the calculation of the block line is completed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a coded data processing device used for compression processing of image data, and more particularly to a LOT (Lapped) for reducing block distortion at the time of coding.
OrthogonalTransform).

[0002]

2. Description of the Related Art DCT (Discrete Cosine Transform) is becoming the mainstream of high-efficiency coding techniques in high-efficiency image coding techniques based on ISDN and CD-ROM. Not limited to this DCT, if the high-efficiency encoding is performed to reduce the average number of bits per pixel, the image quality deteriorates, and if the compression rate is increased, the image quality deteriorates. When the current standard television signal is compressed to 1.5 Mbit / sec, the problem is
The block distortion is generated in the contour unit and the block unit (for example, 8 × 8 pixels) processed by DCT. When the inverse conversion is performed to reproduce the pixels, the DCT outputs in the block are all linearly summed. However, if even one of the 64 DCT outputs of the block including 8 × 8 pixels has information loss, The reproduced pixels in the entire block are deteriorated.

Therefore, in order to reduce such block distortion as much as possible, in order to reduce the block distortion as much as possible, the reference document IEEE TRANSACTIONS ON ACO
USTICS, SPEECH, AND SIGNAL PROCESSING.VOL.37.NO.4.AP
RIL1989 (The LOT Transform Coding Without Blockig E
ffects, HENRIQUE S. MALVAR, DAVID H. STAELIN) has been proposed. Figure 12 shows this LO
1 shows a LOT calculation device for performing T calculation processing,
1 shows a block diagram of a one-dimensional LOT. In FIG. 12, 1 is a LOT operation device, 2 and 3 are DCT devices,
Various arithmetic units shown in FIGS. 13 to 16 are connected to the DCT devices 2 and 3. Here, in FIG. 13, subtraction c = a + (-
b), FIG. 14 shows an operation showing addition c = a + b, FIG. 15 shows an operation for adjusting a predetermined gain (for example, 1/2), and FIG. 16 shows an operation for performing vector rotation. There is. The outputs of the DCT devices 2 and 3 are even (e
ven: even number output 0, 2, 4, 6 and odd:
(Odd number) outputs 1, 3, 5, and 7 are added and subtracted separately, and finally only the odd number component is vector-rotated by the arithmetic unit shown in FIG. 16 to become LOT data. In the one-dimensional LOT configuration shown in FIG.
The output of the pixel _{(X 0 ~X 7, X 0} '~X 7') 8 data by by entering the LOT calculation (Y ₀ ~Y ₇₎ is obtained. That is, in the first stage of input, one-dimensional DCT calculation is performed,
16 data are obtained, and after performing various butterfly operations on these 16 data, vector rotation is performed to finally obtain 8 data. Since this LOT operation is one-dimensional, it outputs 8 × 16 for 16 × 16 input pixels, and the same LOT operation is performed again by changing the vertical and horizontal directions to obtain 8 × 8 data.

FIG. 17 shows the LOT arithmetic unit 1 shown in FIG.
It is a block diagram which shows the calculating part of. In FIG. 17, Y
The stage 11 represents the butterfly operation processing unit for addition / subtraction and gain adjustment shown in FIGS.
The stages 12 and 13 represent the butterfly operation processing unit for vector rotation shown in FIG. Also,
Reference numeral 10 denotes a 1-block line memory that reads data delayed by 1 block from the next DCT (DCT 1 to DCT 1) and temporarily stores the data until the operation of 1-block line is completed in order to perform a butterfly operation. Reference numerals 13 to 17 are switches that change the flow of data by switching the bus, for example.

The arithmetic processing using such a LOT arithmetic unit 1 is shown in FIG. 1 in the case of LOT during data compression.
Inverse L when decompressing data by performing operation from 7 left to right
In the case of OT (ILOT), the calculation is executed from right to left. That is, the data flow will be specifically described with reference to FIGS. 18 and 19. As shown in FIG. 18, the data flow at the time of LOT is the data after the DCT operation at the time of the LOT, after passing through the Y stage 11 and then at the Z stage And is output as LOT output data. in this case,
There are two Z stages 12 used in the Z stage,
Only one out of thirteen.

On the other hand, FIG. 19 shows the data flow at the time of reverse LOT.
As shown in (2), at the time of inverse LOT, two blocks of the LOT-processed data are output to the Z stages 12 and 13, and the outputs of the Z stages 12 and 13 are input to the Y stage 11 to perform the inverse LOT operation. ing. in this case,
The one block line memory 10 is not used.

[0007]

However, in such a LOT arithmetic device, since it is configured to have two Z stages for performing vector rotation,
Although two Z stages are used during the reverse LOT shown in FIG. 19, only one of the two Z stages is used during the LOT shown in FIG. However, there is a drawback that the circuit scale becomes large. That is, the butterfly computing unit constituting the Z stage performs multiplication and addition / subtraction as shown in FIG. 16, and since the multiplication is particularly involved, the circuit scale is considerably larger than that of the Y stage which performs addition / subtraction.
Conventionally, Z for vector rotation with such a large circuit scale is used.
Two stages have to be prepared, and since only one Z stage is used at the time of LOT, there is a problem that the circuit use efficiency is poor and the circuit scale cannot be reduced. Therefore, an object of the present invention is to provide an encoded data processing device capable of executing LOT and inverse LOT operations with a small circuit scale.

[0008]

In order to achieve the above object, a coded data processing device according to the present invention performs an arithmetic operation for performing a superposition orthogonal transformation or an inverse superposition orthogonal transformation using a basic function for superposing data between adjacent blocks. A coded data processing device having means, wherein the calculating means calculates data of one block at the time of LOT and calculates data of a plurality of blocks at the time of ILOT, and data of one block at the time of ILOT. To calculate data of a plurality of blocks at the time of LOT, storage means for storing data of an odd component of the output data of the first and second calculation means, and the first at the time of LOT. The even number component of the output data of the calculating means is supplied to the second computing means, and the odd number component of the output data of the first calculating means is supplied to the storage means, The odd component of the output data of the first arithmetic unit for the immediately preceding block stored in the storage unit is supplied to the second arithmetic unit, and the second arithmetic unit is supplied with the odd-numbered component for the current block. The even component of the output data of the first calculation means and the odd component of the output data of the first calculation means for the immediately preceding block are subjected to Hadamard transform, and the output of the second calculation means at the time of ILOT. The even component of the data is supplied to the first arithmetic means, the odd component of the output data of the second arithmetic means is supplied to the storage means, and the previous block stored in the storage means is stored. The odd component of the output data of the second arithmetic means is supplied to the first arithmetic means, and the first arithmetic means is supplied with the even component of the output data of the second arithmetic means for the current block. And a calculation control means for causing the Hadamard transform to the odd components of the output data of said second arithmetic means for previous block One.

[0009]

The operation of the present invention is as follows. The calculation means
At the time of overlapping orthogonal transformation and its inverse transformation by using a storage means, it is divided so as to include a first arithmetic means capable of arithmetic operation using only one block of data and a second arithmetic means operable by a plurality of blocks. Then, the calculation in the block is executed by different calculation means. Therefore, the circuit is used efficiently, and the circuit scale of the arithmetic processing unit for vector rotation at the time of inverse transformation is significantly reduced.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings. 1 to 11 are views showing an embodiment of an encoded data processing device according to the present invention.

First, the structure will be described. FIG. 1 is a block diagram showing a calculation unit of the LOT calculation device. In FIG.
21 is a LOT arithmetic unit, and the LOT arithmetic unit 21 is
The Y ₁ stage 22 that can be operated in its own block (a certain block) by closing it, the Y ₂ stage 23 that can be operated only when _two blocks are aligned, and the Y ₁ stage 22 and the Y ₂ stage 23 1 block line memory that is inserted between the odds of two and temporarily stores the data of the odd component from the Y ₁ stage (the data of the odd component from the Y ₂ stage at the reverse LOT) until the operation of the next block line is completed. 24, a Z stage 25 for performing vector rotation, and a switch 26 for switching the flow of data.
And 33.

Hereinafter, the Y ₁ stage 22 and the Y ₂ stage 23
The Z stage 25 will be specifically described with reference to FIGS. The Z stage 25 is for rotating the operation at the time of LOT in FIG. 2 and the operation at the time of reverse LOT for rotating the odd component of the input data, and its butterfly operation is shown in FIG. .. K in FIG. 7 is a coefficient for giving vector rotation, for example, 0.13, 0.16.
It is set to 0.13. This Z stage 25 is shown in FIG.
It is similar to the conventional Z stage shown in, but only one. In addition, the Y ₁ stage 22 and the Y ₂
The stage 23 is obtained by dividing the Y stage shown in FIG. 2 (this Y stage corresponds to the conventional Y stage 11 shown in FIGS. 12 to 19) into two stages as shown in FIGS. 8 and 9. There is an operation unit that can be closed and operated in one block Y ₁ stage 22 (first operation processing unit), and an operation unit that can perform operations only when the operation results by the Y ₁ stage 22 between different blocks are complete. This is the Y ₂ stage 23 (second arithmetic processing unit). The 1-block line memory 24 is a memory for temporarily storing the calculation result of the Y ₁ stage in a certain block until the calculation of the Y ₁ stage in the next block is completed. 4 to 7 show various butterfly operations in each stage, and show the same operation contents as the butterfly operation in FIGS. 13 to 16.

Next, the operation of this embodiment will be described. Operation during LOT Calculation (see FIG . 10) FIG. 10 is a diagram showing a data flow during LOT. As a basic idea, Y ₁ can be done only in the same block
The calculation of the stage 22 should be performed first.
First, as shown in FIG. 2, the DCT calculation outputs F _{0 to} F ₇ are
It is converted by the Y ₁ stage 22 to become G _{0 to} G ₇ .
Of these, even sides G ₀ , G ₂ , G ₄ , and G ₆ (hereinafter, referred to as Ge) are directly input to the Y ₂ stage 23 (FIG. 10).
reference). In addition, the odd side G ₁ , G ₃ , G ₅ , G ₇ (hereinafter, G
(represented as o) must be mixed with the even when the next block is calculated (addition and subtraction), so Y ₂
It is temporarily stored in the one-block line memory 24 in order to align the calculation time points in the stage 23. Then, the block data F ₀ 'based on the next DCT calculation output
~ F ₇ 'is converted by the Y ₁ stage 22 and G ₀ '
~ G ₇ '. In this case, Ge 'as well as Ge and Go
Is directly input to the Y ₂ stage 23, and Go ′ is stored in the 1-block line memory 24. At this time, at the same time as inputting to the Y ₂ stage 23, Go is input to the Y ₂ stage 2
Input to 3 and execute Y ₂ stage operation. Here, the operation between different blocks is the Y ₂ stage 2 at the time of LOT.
Do in 3. Then, the outputs H _{0 to} H ₇ of the Y ₂ stage 23.
Is input to the Z stage 25, and Y _{0 to} Y ₇ , which are the results of the LOT calculation, are obtained on the Z stage 25 (see FIG. 2). By the way, it can be considered that the execution time will be delayed by the amount of memory access added when the output of the Y ₁ stage 22 is input to the Y ₂ stage 23.
Since the above calculation is repeated, the total time is
Almost no change. In addition, the above G _{0 to} G ₇ , G ′ ₀ to
G ₇ 'corresponds to that of FIG.

Operation at the time of inverse LOT calculation (see FIG . 11) FIG. 11 is a diagram showing a data flow at the time of inverse LOT. First, input data Y ₀ 'to Y ₇ ' as shown in FIG.
Is converted to J ₀ '-J ₇ ' by the Z stage and Y ₂
The stage 23 is further converted into K ₀ ′ to K ₇ ′. In this case, the Z stage 25 rotates only on the odd side and the through on the even side. Therefore, the Z stage 25 at the time of ILO changes the odd-numbered data input and output from 1 →
It is necessary to twist like 7,3 → 5,5 → 3,7 → 1. Then, the operation of the Y ₂ stage 23 is performed with respect to the one rotated on the odd side by the Z stage 25 and the even side which comes in as it is. Here, FIG.
Then, although the even side is not actually performing any calculation, it is input to the Z stage 25 as input data for convenience. And the Y ₁ stage 22 at the time of the LOT
As with the output, Ke 'directly Y ₁ stage 22
, And Ko ′ is stored in the 1-block line memory 24. Similarly, the following input data is input to the Z stage 25, Y
Converted from K _{0 to} K ₇ by ₂ stages, and Ke is directly Y ₁
It is input to the stage 22 and Ko is stored in the 1-block line memory 24. At this time, as in the case of LOT, K
At the same time as e, the Ko ′ data previously stored in the memory 24 is input to the Y ₁ stage 22. And Y ₁ stage 2
IOT output F ₀ ~
Get F ₇ . That is, at the time of ILOT, the Y ₁ stage 22 takes charge of the operation between different blocks. The data in this case corresponds to that in FIG.

As described above, the LOT is used in this embodiment.
The Y stage in the first half of the operation is divided into a Y ₁ stage 22 that can be operated by closing it in one block, and a Y ₂ stage 23 that allows the two blocks to be operated together, and
In the meantime, since the one block line memory 24 that stores data until the calculation of the next block line is completed is provided, the processing in the Y ₁ stage 22 and the Y ₂ stage 23 is completed within that stage, and , LOT time and ILOT time, the operation between blocks is performed by the operation units of different stages, so that one Z stage 25 can be provided as shown in FIG. Therefore, even if only the Z stage that requires a relatively large circuit scale is prepared at the time of reverse LOT, the circuit scale in this portion can be halved. Further, since the one-block line memory 24 needs to store only the data on the even side, the memory capacity can be reduced.

[0016]

According to the present invention, the LOT calculation means is divided into a first calculation means capable of calculation using only one data and a second calculation means capable of calculation by a plurality of blocks,
The operation between blocks is performed at the time of LOT and ILO using the storage means.
Since it is executed by different operation means at the time of T, the circuit scale of the LOT operation device for executing the LOT and the inverse LOT operation can be greatly reduced, and the encoded data processing device for compressing image data etc. It is suitable to be applied to.

[Brief description of drawings]

FIG. 1 is a block diagram of a LOT calculation device according to the present invention.

FIG. 2 is a configuration diagram for explaining an operation during LOT of the LOT operation device according to the present invention.

FIG. 3 is a configuration diagram for explaining an operation at the time of ILOT of the LOT operation processing according to the present invention.

FIG. 4 is a diagram showing a computing unit for butterfly computing of the LOT computing device according to the present invention.

FIG. 5 is a diagram showing a computing unit for butterfly computation of the LOT computing device according to the present invention.

FIG. 6 is a diagram showing a computing unit for butterfly computation of the LOT computing device according to the present invention.

FIG. 7 is a diagram showing a computing unit for butterfly computing of the LOT computing device according to the present invention.

FIG. 8 is a configuration diagram of a Y ₁ stage of the LOT operation device according to the present invention.

FIG. 9 is a configuration diagram of a Y ₂ stage of the LOT operation device according to the present invention.

FIG. 10 is a block diagram for explaining a data flow at the time of LOT of the LOT calculation device according to the present invention.

FIG. 11 is a block diagram for explaining a data flow at the time of ILOT of the LOT calculation device according to the present invention.

FIG. 12 is a configuration diagram of a conventional LOT calculation device.

FIG. 13 is a diagram showing a computing unit for butterfly computation of a conventional LOT computing device.

FIG. 14 is a diagram showing a computing unit for butterfly computation of a conventional LOT computing device.

FIG. 15 is a diagram showing a computing unit for butterfly computation of a conventional LOT computing device.

FIG. 16 is a diagram showing a computing unit for butterfly computation of a conventional LOT computing device.

FIG. 17 is a block diagram of a conventional LOT calculation device.

FIG. 18 is a diagram for explaining a data flow at the time of LOT of the conventional LOT calculation device.

FIG. 19 is a diagram for explaining a data flow at the time of ILOT of the conventional LOT calculation device.

[Explanation of symbols]

21 LOT arithmetic unit 22 Y ₁ stage (first arithmetic processing unit) 23 Y ₂ stage (second arithmetic processing unit) 24 1 block line memory 25 Z stage 26-33 switch

Claims (1)

[Claims] 1. A coded data processing device having arithmetic means for executing superposition orthogonal transformation (LOT) or inverse superposition orthogonal transformation (ILOT) by using a primitive function for superposing data between adjacent blocks. The means calculates the data of one block at the time of LOT and calculates the data of a plurality of blocks at the time of ILOT, and the data of one block at the time of ILOT,
Second computing means for computing data of a plurality of blocks, storage means for storing odd component data of output data of the first and second computing means, output of the first computing means at LOT The even component of the data is supplied to the second arithmetic means, the odd component of the output data of the first arithmetic means is supplied to the storage means, and the previous block stored in the storage means is stored. The odd-numbered component of the output data of the first arithmetic means is converted into the second component.
Of the output data of the first arithmetic means for the current block and the odd number of output data of the first arithmetic means for the preceding block to the second arithmetic means. The component is subjected to Hadamard transformation, and at the time of ILOT, the even component of the output data of the second computing means is supplied to the first computing means, and the odd component of the output data of the second computing means is stored in the memory. Means for supplying the odd number component of the output data of the second arithmetic means for the immediately preceding block stored in the storage means to the first arithmetic means, and to the first arithmetic means. Arithmetic control for causing Hadamard transformation on the even component of the output data of the second arithmetic means for the current block and the odd component of the output data of the second arithmetic means for the previous block An encoded data processing device comprising: