JPH0583190B2 - - Google Patents

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a high-power Darlington transistor, and particularly relates to a semiconductor device having a diode between an emitter and a base (conventional technology). ) Conventionally, this type of semiconductor device has been configured as shown in FIG. 3, for example. In Figure 3, 1
0 is a semiconductor substrate, and this semiconductor substrate 10 has an N ⁺ type impurity region 11 formed by implanting impurity ions on the back surface, and the N type region 12 on the front surface has ρ = 45 to 50 Ω·cm, The thickness is approximately 85 μm.

On the surface of the N-type region 12, P-type impurity diffusion regions 13 ₁ and 13 ₂ (N _S =5×10 ¹⁸ /cm ³ , diffusion depth
18-20 μm) is formed. The surface regions of the impurity diffusion regions 13 ₁ and 13 ₂ have N ⁺ type impurity diffusion regions 14 ₁ and 14 ₂ as emitter regions, respectively.
(N _S =1×10 ²¹ /cm ³ , diffusion depth 10 μm) is formed. Further, in the surface region _of the P type impurity diffusion region 13 ₂ , ^{an N + type} impurity diffusion region 15 (N _S =1×10 ²⁰ / cm ³ , diffusion depth
2 μm) is formed. An oxide film 16 is formed on the semiconductor substrate 10, and on the P-type impurity diffusion regions 13 ₁ and 13 ₂ of this oxide film 16,
Contact holes are formed on the N ⁺ type impurity diffusion regions 14 ₁ and 14 ₂ and on the N ⁺ type impurity diffusion region 15, respectively. Various electrodes 17 ₁ made of aluminum are disposed on the oxide film 16.
~17 ₄ is formed. An electrode 17 ₂ is connected to the electrode 17 1 via a base terminal 18, an electrode 17 ₃ and _a resistor R ₁ . The electrode 17 2 is connected to the electrode 17 ₄ via the emitter terminal 19 and _the resistor R ₂ .
is connected. Further, a collector terminal 20 is connected to the back surface of the semiconductor substrate 10.

FIG ^. 4 shows _an equivalent circuit _of the device shown in FIG _. configured. Further, the semiconductor substrate 10, the P-type impurity diffusion region 1
3 ₂ and N ⁺ type impurity diffusion region 14 ₂
An NPN transistor TR ₂ is configured, and a diode D is configured by the P type impurity diffusion region 13 ₂ and the N ⁺ type impurity diffusion region 15. This diode D is for shortening the turn-off time of the transistors TR ₁ and TR ₂ and is for drawing out the minority carriers accumulated in the base region 13 ₂ of the transistor TR ₂ to the base terminal 18 .

Incidentally, in the semiconductor device shown in FIGS. 3 and 4 above, as shown in the equivalent circuit shown in FIG. , from the power supply 22 between the collector terminal 19 and the emitter terminal 20.
Used with 300V applied. At this time, the semiconductor substrate 10 is placed in the portion of the diode D in FIG _.
An NPN transistor is parasitically formed with N ⁺ type impurity diffusion region 15 as an emitter.
A base current I _B is supplied to TR ₃ , the diode D section performs a transistor operation, and a collector current I _C flows. This current I _C becomes the leakage current I _CEX .

In order to reduce the leakage current I _CEX , it is desirable to reduce the collector current I _C by reducing the current amplification factor h _FE of the transistor TR ₃ . However, with the current manufacturing process, it is not possible to reduce the current to 1 to 10 mA or less. Therefore, there is a drawback that power loss is large, heat is generated, and reliability is reduced.

(Problems to be Solved by the Invention) As described above, conventional semiconductor devices have the disadvantage that a large leakage current flows, resulting in large power loss and low reliability.

Therefore, the present invention is intended to eliminate the above-mentioned drawbacks, and aims to provide a highly reliable semiconductor device in which power loss can be reduced by reducing leakage current.

[Structure of the Invention] (Means and Effects for Solving Problems) That is, in order to achieve the above object, in this invention, the anode region of the diode in FIG. 3 is made larger than the base region of the transistor. It is formed deep enough.

By doing so, the base width of the transistor parasitically formed in the diode portion becomes wider, so that the current amplification factor of this parasitic transistor can be reduced, and leakage current can be reduced.

(Example) Hereinafter, an example of the present invention will be described with reference to the drawings. In FIG. 1, the same components as in FIG. 3 are given the same reference numerals. First, impurity ions are implanted into the back surface of an N type semiconductor substrate 10 to form an N ⁺ type impurity region 11. Here, in the N-type region 12 without implanting impurities, ρ=45
~50Ω・cm, thickness is about 85μm. Next, on the surface of this N-type region 12, a P-type impurity diffusion region 23 as an anode region of the diode D is formed by diffusion (N _S =5×10 ¹⁸ /cm ³ , depth 40 μm). Next, a transistor is placed on the surface of the N-type region 12.
P-type impurity diffusion regions 13 ₁ and 13 ₂ which will become the base regions of TR ₁ and TR ₂ are formed by diffusion (N _S =5×10 ¹⁸ /cm ³ ,
(depth 20μm). Thereafter, N ⁺ type impurity diffusion regions 14 ₁ and 14 ₂ as emitter regions are formed by diffusion in the surface regions of the impurity diffusion regions 13 ₁ and 13 ₂ , respectively (N _S =1×10 ²¹ /cm ³ , depth 10 μm). )do. At this time, the depth of diffusion of these regions 14 ₁ and 14 ₂ is set according to the desired characteristics (for example, current amplification factor h _FE ) of the transistors TR ₁ and TR ₂ . Next, in the surface region of the P-type impurity diffusion region 13 ₂ ,
An N ⁺ type impurity diffusion region 15 as a cathode region of the diode D is formed by diffusion at a distance from the N ⁺ type impurity diffusion region 14 ₂ (N _S =1×10 ²⁰ /cm ³ , depth
2 μm). Next, after forming an oxide film 16 on the semiconductor substrate 10, photoetching is performed to form an oxide film 16 on the P-type impurity diffusion regions 13 ₁ and 13 ₂ .
Contact holes are formed in the oxide film 16 on the N ⁺ type impurity diffusion regions 14 ₁ and 14 ₂ and on the N ⁺ type impurity diffusion region 15 . Then, an aluminum layer is deposited on the oxide film 16 and patterned to form each electrode 17 ₁ to 17 ₄ .

According to such a configuration, the diffusion depth of the P-type impurity diffusion region 23, which is the base of the NPN-type transistor _TR3 parasitically formed in the diode D section, is set to be sufficiently deep, so that this transistor
The base of TR ₃ becomes wider and the current amplification factor h _FE can be reduced. Therefore, leakage current can be reduced, power loss can be reduced, heat generation can also be suppressed, and reliability can be improved.

In the above embodiment, the diffusion depth of the anode region 23 of the diode D is 40 μm, and the transistor TR ₂
The diffusion depth of the base region 13 ₂ is set to 20 μm, but the diffusion depth of the anode region 23 is set to 20 μm in consideration of ease of manufacture and leakage current characteristics.
3 ₂ is preferably 1.5 to 3.0 times. Further, in the above embodiment, a substrate in which impurities were implanted into the back surface of the semiconductor substrate was used, but a substrate in which a low concentration epitaxial layer of the same conductivity type was deposited on the surface of the semiconductor substrate may also be used.

FIGS. 2a and 2b show the leakage current I _CEX when a voltage from 0V to 7V is applied to the base terminal 18 and emitter terminal 19 of the semiconductor device in FIGS. 3 and 1, respectively. Here, a voltage of 300V was applied between the emitter terminal 19 and the collector terminal 20, and the results were obtained by measuring 100 samples. Figure a shows the characteristics of the semiconductor device shown in FIG. 3, and Figure b shows the characteristics of the semiconductor device shown in FIG. 1. As shown in the figure, for example, when a voltage of 6V is applied between the base terminal 18 and the emitter terminal 19,
In conventional semiconductor devices, the leakage current I _CEX is distributed around 1 mA, whereas in the semiconductor device of the present invention, it is distributed around 1 μm, which reduces the leak current I _CEX to 1/1.
It can be seen that it can be reduced to about 100. This made it possible to reduce heat generation due to power loss to a non-problematic level.

[Effects of the Invention] As described above, according to the present invention, power loss can be reduced by reducing leakage current, and a highly reliable semiconductor device can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a semiconductor device according to an embodiment of the present invention, FIG. 2 is a diagram showing base-to-emitter voltage-leakage current characteristics of a conventional semiconductor device and a semiconductor device according to an embodiment of the present invention, and FIG. 4 is a diagram showing a conventional semiconductor device, FIG. 4 is a diagram showing an equivalent circuit of FIG. 3, and FIG. 5 is an equivalent circuit diagram for explaining leakage current in the semiconductor device of FIG. 3. TR ₁ , TR ₂ ... transistor, D ... diode, 13 ₂ ... base region, 23 ... anode region.

Claims (1)

[Claims] 1 A semiconductor substrate of a first conductivity type; a first impurity diffusion region of a second conductivity type formed on the main surface of the semiconductor substrate and electrically connected to the first terminal; a second impurity diffusion region formed apart from the first impurity diffusion region; and a second impurity diffusion region formed within the first impurity diffusion region and electrically connected to the second impurity diffusion region, and a first load. a third impurity diffusion region of a first conductivity type connected to the first terminal via an element; a third impurity diffusion region formed within the second impurity diffusion region and electrically connected to the second terminal; a fourth impurity diffusion region of a first conductivity type connected to the third impurity diffusion region through a second load element; and a fourth impurity diffusion region formed within the second impurity diffusion region and separated from the fourth impurity diffusion region;
a fifth impurity diffusion region of a first conductivity type that is electrically connected to the first terminal; and a fifth impurity diffusion region that is formed on the back surface of the semiconductor substrate, has a higher impurity concentration than the semiconductor substrate, and is connected to the third terminal. a sixth impurity diffusion region of a first conductivity type;
The impurity diffusion region and the third impurity diffusion region are
the semiconductor substrate, the second
The impurity diffusion region and the fourth impurity diffusion region constitute a second transistor Darlington-connected to the first transistor, and the second impurity diffusion region and the fifth impurity diffusion region constitute a second transistor connected to the first transistor. The diffusion depth of the second impurity diffusion region in the portion that acts as a diode to extract fractional carriers accumulated in the base region of the second transistor at turn-off and serves as the anode region of the diode is defined as the diffusion depth of the second impurity diffusion region in the base region of the second transistor. By forming the region deeper than the second impurity diffusion region in the portion that functions as a region, the semiconductor substrate is formed parasitically with the semiconductor substrate as a collector, the second impurity diffusion region as a base, and the fifth impurity diffusion region as an emitter. A semiconductor device characterized in that a transistor has a wide base width.