JPH0584716B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a video signal processing device, and in particular to a disk on which a video signal including a line-sequential color difference signal in which two types of color difference signals appear sequentially every horizontal scanning period is recorded. The present invention relates to an apparatus for processing line-sequential color difference signals included in a video signal reproduced from a recording medium.

<Description of Prior Art> Generally, when synchronizing line sequential signals, the type of the line sequential signals must be determined for each horizontal scanning period H, and when recording or transmitting, the type must be determined in some form. The signal format is such that it can be distinguished by For example, when recording two types of signals line-sequentially, a 2H cycle DC component DC offset and a frequency offset are performed, or a flag signal is added at a 2H cycle. However, when determining the type of line sequential signal that has been subjected to these processes using a reproduction system, it is not possible to accurately determine the type due to effects such as dropout and transmission distortion.

The following is an example of a device that reproduces a still image by continuously reproducing a video signal containing a line-sequential color difference signal recorded for one field on a circular recording track on a magnetic sheet and having a DC offset of 2H period as an identification signal. Let me explain.

FIG. 1 is a block diagram showing the main structure of a conventional reproducing apparatus of this type. Also, Figure 2 is Figure 1 a~
g is a waveform diagram showing waveforms at various parts.

In FIG. 1, _t1 is a terminal to which a line-sequential color difference signal obtained from a reproduced video signal is supplied, and _t2 is a terminal to which a horizontal synchronization signal obtained from a reproduced video signal is supplied. Further, 1 is a sample and hold circuit, 2 is an amplification unit that amplifies the output of the sample and hold circuit 1, 3 is a comparator that compares the output of the amplifier with a predetermined level, and 4 is a comparator 3.
The horizontal synchronization signal (Fig. 2 d) is used as the data input.
6 is a 1H (63.556 μsec) delay line, and 7 is a second flip-flop triggered by the horizontal synchronization signal d.
Monomulti, SW that forms the signal as shown in Figure b
When the output signal of DFF4 is high level, SW1's E is connected to A and SW2's F is connected to C. When it is low level, SW1's E is connected to B and SW2's F is connected to C, respectively, and the lines are synchronized. The color difference signals are
It will be supplied at t ₃ and t ₄ .

Now, the line-sequential color difference signal consists of red (R)-luminance (Y) and blue (B)-luminance (Y) signals, and R-Y has a higher center level than B-Y and is recorded with a line offset. Suppose that At this time, if R-Y is being reproduced at a certain H level, the signal sampled and held at the falling edge of the output signal b of the monomulti 7 is at a high level during that period. Therefore, the next H
The output signal e of the DFF4 becomes high level. That is, if the output signal of the 1H delay line 6 is R-Y, E of SW1 is connected to A, and the synchronized R-Y is output from the terminal _t3 . Similarly, the synchronized B-Y is output from the terminal _t4 .

However, when obtaining a line simultaneous color difference signal from a line sequential color difference signal with the above configuration, if there is some kind of flaw in the line sequential color difference signal at the sampling timing, such as S/N deterioration due to dropout, it is difficult to obtain a sample with the correct DC offset. You will not be able to get hold results. Therefore, there is a drawback that switching errors occur between SW1 and SW2, and switching between RY and BY becomes reversed. For example, the second
S/N of dropouts, etc. shown in the direction of arrow A in the figure
Due to deterioration, the period shown in B becomes reversed. This becomes very noticeable on the playback screen. For example, if the screen is all blue, a red line will appear on the screen. In particular, in still image playback devices such as those mentioned above, S/D by dropout etc.
Since there is a high possibility of N deterioration, a conspicuous line always appears in the same area.

<Object of the Invention> The present invention has been made in view of the above-mentioned drawbacks, and provides a video signal processing device capable of line-synchronizing line-sequential color signals without error even when the S/N is very poor. The purpose is to

<Description by Example> The present invention will be described below using an example in which the present invention is applied to the above-mentioned still image reproduction device.

FIG. 3 is a timing chart for explaining necessary synchronization control signals prior to explaining this embodiment.

In FIG. 5, a is a reproduced horizontal synchronizing signal, and b is a signal PG synchronized with the rotation of the magnetic sheet, one pulse being obtained in one field. c is PG,
b is waveform-shaped using a horizontal synchronization signal. d is a timing signal formed from the horizontal synchronizing signal a and inverted every H. e is a discrimination signal obtained by reading an identification signal superimposed on a directly reproduced line sequential signal to discriminate the type of line sequential signal. In the diagram
F1 to F4 each represent a field number,
1/2H at the boundary point between F1 field and F2 field
Skew correction is performed, and the RY signal is continuously reproduced over 2H. The timing signals d and e have opposite phases at time t ₂ '. This state is the end of the F3 field, that is, the time
Continues until t ₄ ′. From this point on, the timing signal d and the discrimination signal e become in phase again, and one cycle continues at time _t5 . That is, in this example, the timing signal d for free-running switching and the discrimination signal for direct readout switching are in opposite phases between times t ₂ ' and t ₄ ', that is, for two field periods, and are in phase during the other two field periods. There is. Therefore, the timing signal d is determined by the discrimination signal e.
In order to match the phase of , create a timing signal that is inverted every frame using PG,b,
If the phase of the timing signal d is inverted during the period when the timing signal f is at high level, g
It is possible to obtain a switching control signal that is completely in phase with the discrimination signal e shown in FIG.

FIG. 4 shows a block diagram showing an example of a circuit configuration for obtaining this timing signal and switching control signal g.

A line-sequential color difference signal is inputted from a terminal 11 and guided to a sample and hold circuit 12 . Here, the above-mentioned line sequential identification signal is sampled using a signal delayed by a predetermined timing in the mono multivibrator 13 from the reproduced horizontal synchronization signal inputted from the terminal 15, and the level difference is detected in the comparator circuit 14, and the switching is performed. A signal e for use is formed. The horizontal synchronizing signal a inputted from the terminal 15 is further inputted to the inverting circuit 17 through the monomulti 16, where a timing signal d which is inverted every 1H is generated. A signal c synchronized with PG and b is inputted from the terminal 8 and is led to the OR circuit 19 and serves as a reset input for the counter 25. The output of the OR circuit 19 becomes the input of the inverting circuit 20, where a signal is inverted every field, which is further inverted by the OR circuit 20.
1 to an inverting circuit 22. Here, a timing signal that is inverted every two fields is created, and both the timing signal d and the timing signal are input to the exclusive OR circuit 23, and the output thereof becomes the actual line switching control signal g. This line switching control signal g is also led to an exclusive OR circuit 27, the output of which is supplied to an AND circuit 26 together with a horizontal synchronizing signal a, and the output of the AND circuit 26 becomes the clock input of the counter 25. There is. After counting a predetermined number of clocks supplied from the AND circuit 26, the counter 25 supplies a carry-out signal to the control circuit 24 and the other input terminal of the OR circuit 21. The θ output of the inverting circuit 20 is also input to the control circuit 24 as another input.
Based on these two inputs, the control circuit 24
is supplied to the other input terminal of the OR circuit 19.

FIGS. 5 and 6 are timing charts for explaining the operation form of each block diagram.

Figure 5 c' shows the trailing edge of Figure 3 signal c, with ia and
ib is an output waveform of the inverting circuit 20 representing two types of phases. ₁ and ₂ are the output waveforms of the inversion circuit 22 representing two more types of phases in ia, and ₃ and ₄ are the output waveforms of ib.
It is that in . Now, assuming that ₁ shown in FIG. 5, that is, FIG. 6 ₁ is the output waveform of the inverting circuit 22,
₂ , ₃ , _{and 4} all have a different phase relationship from the correct phase inversion timing signal.

Now, if there is a phase difference between the direct readout determination signal e and the switching control signal g output from the exclusive OR circuit 23, the exclusive OR circuit 27 outputs a high level signal for a period of time during which the phase difference exists. An output signal appears. Therefore, a horizontal synchronizing signal is obtained as an output signal of the AND circuit 26 during this period, and this horizontal synchronizing signal is counted by the counter 25. In this way, when a certain number is counted, that is, when it is determined that the phases are different, a carry-out output is obtained from the counter 25, and the output of the inverting circuit 22 is also inverted with this carry-out output. In FIG. 5, j2 _{and 2} ' represent the correction operation when the combination of the outputs of the two inversion circuits 20 and 22 is ia- ₂ , and _j2 means the internal count value of the counter 25. . The counter value increases from time _t1 due to the phase difference, and a carry-out output is produced at time tb (not shown). At the same time as this
₂ ′ is the time when the level changes from high level to low level.
At t ₂ ′, when ia falls, it becomes high level again. After that, the phase becomes normal ₁ .

Next, the phase correction for the combination of ib- ₃ and ib- ₄ will be described. Figure 6 shows this.ia
₋₁ indicates a normal phase as described above.
₃ ', _j3 , and _ib3 ', the solid line is the original operating waveform, the broken line is the internal value of the operating waveform counter 24 of ₂ (inverting circuit 22) of this embodiment, and similar i (inverting circuit 22).
0) is the operating waveform. The same applies to ₄ ′, j ₄ , and ib ₄ ′.

To explain from the former point of view, since the phase is the same from time t ₁ to t ₂ ', the counter 25 does not count anything other than an error such as a dropout, and operates from time t ₂ ' to t ₇ . Then, ₃ ' is inverted to high level due to the carry out output at _t7 . Next, at time t ₃ ′, ib ₃ ′ is reversed to low level, so ₃ ′
becomes low level, a phase difference occurs at this point, the counter 25 starts operating, and a carry-out output is generated at time _t8 . At this time, if ib ₃ ' is at a low level, if it is controlled to be at a high level, since _{ib 3} ' is simultaneously at a high level at this time, the phase becomes normal from time t ₄ '.

Considering the latter in the same way, the counter 25 is activated due to the difference in phase from time _t1 , and at time _t6 , the carry-out output ₄ ' becomes low level. Then, the counter 25 is activated again from t ₂ ′, and ₄ ′ becomes high level at time t ₇ . At this time
Since ib ₄ ' is inverted at the same time as the carry-out output of the counter 25 and ib ₄ ' is inverted to low level, ib ₄ ' is inverted at time t ₃ '. Through this series of controls, the phase becomes normal after time t ₃ '.

FIG. 7 is a flowchart showing an algorithm for the operation of the control circuit 25. As shown in FIG.

The starting condition is that the motor rotation is stable. k is the number of carry-outs of the counter 25. Check whether there is a carry out in the first field, and check this again in the next field. If there is no carry out in both fields (if the phase is correct from the beginning; ₁ )
If there is no carry-out in the second field (case ₂ ), there is no need to correct the phase of the inverting circuit 20 and the operation continues as it is. On the other hand, if there is a carry-out output in the second field, it is determined whether it is the Nth field (N=2 in the example), and if so, the output signal of the inverting circuit 10 is set to high as explained in the previous embodiment. This phase inversion control is performed depending on whether the level is high or low.

Now, let us consider a case where the timings of the phase discontinuity point of the switching control signal and the PG do not ideally match. Although this is not so much of a problem in the case of self-recording/playback, the following problems arise when compatibility with other devices is achieved. In other words, there are differences in the characteristics of the detectors that detect the rotation of the magnetic sheet, deviations in the PG timing due to errors in their mounting positions, and the fact that the rotation servo is not applied to the PG pins embedded in such small radius points of the magnetic sheet. The control signal phase near the phase discontinuity point may be caused by deviation of the PG on the recording track existing at a large radius position due to It is inverted with respect to the phase of

FIG. 8 explains the malfunction of the switching signal caused by this PG timing shift. For each alphabet, the solid line is the current operating waveform and the broken line is the waveform when there is no shift in PG, as in FIG.
According to this, it can be seen that the phase of the 2H switching signal g from time t ₂ ' to t ₁₀ is inverted with respect to the original phase, and a switching error occurs when line synchronization is performed.

Next, an embodiment of the present invention based on such a concept will be described.

FIG. 9 is a block diagram showing one embodiment of the present invention, and FIG. 10 is an operating waveform diagram thereof. In FIGS. 9 and 10, the same numbers and symbols as in FIGS. 4 and 5 indicate blocks and operation waveforms having similar functions.

Similar to FIG. 4, the discrimination signal output from the level comparison circuit 14 is supplied not only to the exclusive OR circuit 27 but also to the retriggerable Kino multi 29, which has an unstable period of time slightly longer than 1H. When a point where the switching signal does not invert for a time longer than the horizontal synchronization period, that is, a phase discontinuity point comes, the output becomes low level from then on. This signal is supplied to the A terminal of the switch circuit 30. Also PG
A signal o based on this is supplied from the terminal 8 to the B terminal of the switch circuit 30 in addition to the counter 25.
The output of the switch circuit 30 is input to the inverting circuit 20 through the OR circuit 19, and this θ output is also supplied to the OR circuit 21, the control circuit 24, and the switch circuit 31. The output of the switch circuit 31 is input to a monomulti 32 which has an unstable period of (2 fields - 3H), and the output k of this mono multi 32 is
is supplied to the monomulti 33, from which the gate signal l for the 6H period is generated. Here, 3H is not limited to 3H, which is the specifically raised value, but may be anything that exceeds the absolute value of the PG variation. The gate signal 1 controls the switch circuit 30, and when the gate signal 1 is at a low level, the connection of the switch circuit 30 is switched to the B side and when it is at a high level, to the A side. The control circuit 34 has almost the same function as the control circuit 24 in FIG.
2,33 is operating.

FIG. 12c shows the pulses obtained from the horizontal synchronizing signal and PG, and the broken line shows the timing when there is no deviation. The phase with i is normalized in field F1, and at the next pulse c (time t ₁₁ ), the monomulti 32 enters an unstable period (2V-3H), and at time t ₁₂ the next monomulti 23 enters the unstable period for 6H period. Meanwhile, the switch 20 is switched to the A side, so the output m of the retriggerable mono multi 29 falls at the discontinuous phase point t ₄ ' of the switching signal, and at the same time, i is inverted and the mono multi 3
2 enters the unstable period. Thereafter, the phase switching of the inverting circuits 20 and 22 is controlled at the discontinuous point seen from the superimposed identification signal, so that a reliable line synchronization switching control signal g can be obtained despite the PG generation deviation.

According to the above-mentioned configuration, when a line-synchronized control signal is formed using PG, even if a PG generation phase shift occurs due to differences between devices, the phase shift of the line-sequential signal can be avoided. Since the phase of the control signal described above can be reliably inverted at consecutive points, it has become possible to always perform good line synchronization.

It is more preferable to perform this operation again when the rotation of the magnetic sheet is extremely disturbed or when a long dropout occurs in the line-sequential signal, and such a configuration can be easily realized. can do.

<Description of Effects> As explained above, according to the present invention, a video signal processing device can be obtained that can line-synchronize line-sequential color difference signals without malfunction even when the S/N is poor. It is.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of main parts of a conventional playback device, FIG. 2 is a waveform diagram showing waveforms of each part in FIG. 1, and FIG. 3 is a timing chart for explaining the synchronization control signal of the embodiment. , FIG. 4 is a block diagram showing an example of the circuit configuration for obtaining the control signal shown in FIG. 3, FIGS. 5 and 6 are timing charts showing waveforms of each part in FIG. 4, and FIG. A flowchart showing the operation algorithm of the control circuit shown in the figure, FIG. 8 is a diagram for explaining the influence of PG deviation, and FIG. 9 is a block diagram showing the main part configuration of an apparatus according to an embodiment of the present invention. FIG. 10 is a timing chart showing the operation of the device shown in FIG. 9. 11...Terminal to which a line sequential signal is input, 12...
... Sample hold circuit, 13 ... Mono multivibrator, 14 ... Comparison circuit, 16 ... Mono multivibrator, 17, 20, 22 ... Inverting circuit, 25 ... Counter, 28 ... Control signal output circuit, 32, 33...mono multivibrator, 34...control circuit.

Claims (1)

[Claims] 1. Two types of color difference signals are included in a video signal reproduced from a disk-shaped recording medium on which a video signal including a line-sequential color difference signal that appears sequentially in each horizontal scanning period is recorded. A device for processing a line-sequential color difference signal, which inputs a line-sequential color difference signal included in a video signal reproduced from the disc-shaped recording medium, synchronizes the input line-sequential color difference signal, and processes the two types of line-sequential color difference signals. a synchronizing means for simultaneously outputting the color difference signals; and inputting a first signal that is inverted every horizontal scanning period and a second signal that is inverted at the rotation period of the disc-shaped recording medium, and control signal forming means for forming a control signal for controlling the synchronization operation in the synchronization means using the signal and the second signal; inputting a line sequential color difference signal, and determining the types of two types of color difference signals that appear sequentially in each horizontal scanning period in the input line sequential color difference signal;
a discriminating means for outputting a discriminating signal according to a discriminating result; and a discriminating means for outputting a discriminating signal according to a discriminating signal output from the discriminating means during a part of the period determined by the timing at which the second signal is inverted. A video signal processing device comprising phase setting means for setting the phase of a control signal to be formed.